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Extended Low Power Bus Binding Combined with Data Sequence Reordering

Authors: Jihyung Kim, Taejin Kim, Sungho Park, Jun-Dong Cho


In this paper, we address the problem of reducing the switching activity (SA) in on-chip buses through the use of a bus binding technique in high-level synthesis. While many binding techniques to reduce the SA exist, we present yet another technique for further reducing the switching activity. Our proposed method combines bus binding and data sequence reordering to explore a wider solution space. The problem is formulated as a multiple traveling salesman problem and solved using simulated annealing technique. The experimental results revealed that a binding solution obtained with the proposed method reduces 5.6-27.2% (18.0% on average) and 2.6-12.7% (6.8% on average) of the switching activity when compared with conventional binding-only and hybrid binding-encoding methods, respectively.

Keywords: low power, bus binding, switching activity, multiple traveling salesman problem, data sequence reordering

Digital Object Identifier (DOI):

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[1] J. Chang and M. Pedram, "Module assignment for low power," in Proc. Eur. Design Automation Conf., pp. 376-381, 1996.
[2] C. Lyuh and T. Kim, "High-level synthesis for low power based on network flow method," IEEE Trans. VLSI, vol. 1, no. 3, pp. 309-320, 2003.
[3] C. Lyuh and T. Kim, "Coupling-Aware High-Level Interconnect Synthesis," IEEE Trans. Computer-aided design of integrated circuits and systems, vol. 23, no. 1, pp. 157-164, 2004.
[4] Y. Choi and T. Kim, "An efficient low-power binding algorithm in high-level synthesis," IEEE Int. Symp. On Circuits and Systems, vol. 4, pp. 321-324, 2002.
[5] X. Xing and C. C. Jong, "A look-ahead synthesis technique with backtracking for switching activity reduction in low power high-level synthesis," Microelectronics Journal, vol. 38, no. 4-5, pp. 595-605, 2007.
[6] M. Yoon, "Sequence-switch coding for low-power data transmission," IEEE Trans. on VLSI Syst., vol. 12, no. 12, pp. 1381-1385, 2004.
[7] V. Dabholkar, S. Chakravarty, I. Pomeranz, and S. Reddy, "Techniques for minimizing power dissipation in scan and combinational circuits during test application," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 12, pp. 1325-1333, 1998.
[8] S. K. Wong and C. Y. Tsui, "Re-configurable bus encoding scheme for reducing power consumption of the cross coupling capacitance for deep sub-micron instruction bus," in Proc. DATE, vol. 1, pp. 130-135, 2004.
[9] M. R. Stan and W. P. Burleson, "Bus-invert coding for low-power I/O," IEEE Trans. VLSI Syst., vol. 3, pp. 49-58, 1995.
[10] H. Sankaran and S. Katkoori, "Bus Binding, Re-ordering, and Encoding for Crosstalk-producing Switching Activity Minimization during High Level Synthesis," in Proc. 4th IEEE Intl. Symp. On Electronics Design, Test & Applications, pp. 454-457, 2008.
[11] T. Bektas, "The multiple traveling salesman problem: an overview of formulations and solution procedures," Omega, vol. 34, no. 3, pp. 209-219, 2006.
[12] J. Kim and J. Cho, "Low power bus binding exploiting optimal substructure," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E94-A, no. 1, 2011.