Jitter Transfer in High Speed Data Links

Authors: Tsunwai Gary Yip

Abstract:

Phase locked loops for data links operating at 10 Gb/s or faster are low phase noise devices designed to operate with a low jitter reference clock. Characterization of their jitter transfer function is difficult because the intrinsic noise of the device is comparable to the random noise level in the reference clock signal. A linear model is proposed to account for the intrinsic noise of a PLL. The intrinsic noise data of a PLL for 10 Gb/s links is presented. The jitter transfer function of a PLL in a test chip for 12.8 Gb/s data links was determined in experiments using the 400 MHz reference clock as the source of simultaneous excitations over a wide range of frequency. The result shows that the PLL jitter transfer function can be approximated by a second order linear model.

Keywords: Intrinsic phase noise, jitter in data link, PLL jitter transfer function, high speed clocking in electronic circuit

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1058141

References:

[1] Terabyte Bandwidth Initiative, Rambus Developer Forum, Tokyo, Japan, November 28-29, 2007.
[2] Ken Chen et al, "Clock and Circuit Design for a Parallel IO on a First Generation Cell Processor", Session 28, Paper 28.9, IEEE International Solid-State Circuit Conference, San Francisco, California, Feb. 6, 2005.
[3] T.G. Yip, Phase Noise Initiative: Characterizing Intrinsic Phase Noise and Phase Noise for Diagnostic. Rambus Technical Forum, Nov. 16, 2007.
[4] T.G. Yip et al, "Clock Jitter Reduction in High Speed Interfaces", Accepted for presentation at DesignCon 2009, Santa Clara, California USA, February 2009.