Encoding and Compressing Data for Decreasing Number of Switches in Baseline Networks
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 32804
Encoding and Compressing Data for Decreasing Number of Switches in Baseline Networks

Authors: Mohammad Ali Jabraeil Jamali, Ahmad Khademzadeh, Hasan Asil, Amir Asil

Abstract:

This method decrease usage power (expenditure) in networks on chips (NOC). This method data coding for data transferring in order to reduces expenditure. This method uses data compression reduces the size. Expenditure calculation in NOC occurs inside of NOC based on grown models and transitive activities in entry ports. The goal of simulating is to weigh expenditure for encoding, decoding and compressing in Baseline networks and reduction of switches in this type of networks. KeywordsNetworks on chip, Compression, Encoding, Baseline networks, Banyan networks.

Keywords: Networks on chip, Compression, Encoding, Baseline networks, Banyan networks

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1055062

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1938

References:


[1] J. Kim, C. Nicopoulos, D. Park, R. Das, Y. Xie, V. Narayanan, M. S. Yousif, and C. R. Das. A novel dimensionally-decomposed router for on-chip communication in 3D architectures. In Proc. of ISCA, 2007.
[2] N. S. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. Hu, M. Irwin, M. Kandemir, and N. Vijaykrishnan. Leakage current: Moores law meets static power. Computer, 36(12):6577, December 2003.
[3] S. Kolson, A. Jantsch, J.-P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, and A. Hemani. A NoC architecture and design methodology.In Proc. of ISVLSI, 2002. World Academy of Science, Engineering and Technology 30 200938
[4] P. U. Tagle and N. K. Sharma, "Performance of Fault-Tolerant ATM Switch", IEE Proceedings on Communication, Vol. 143, No. 5 , pp. 318-324, October 1996
[5] Muhammad Anan and Mohsen Guizani Modeling and Simulation of A Fault Tolerant ATM Switching Architecture, proc. Of IEEE Simulation Symposium , pp. 42-47, 2000 .
[6] Neeraj K.Sharma Fault Tolerant Batcher Banyan Packet Switch , proc. Of IEEE Computing and Communications Conference, New Jersey, IEEE 1997 pp: 125-130, 1997.
[7] W.Syen E.Chen,Y.M.Kim ,Y.W.Yao and M.T.Liu FDB : A High Performance Fault Tolerant Switching Fabric for ATM Switching Systems, Proc. of the 10th IEEE International Phoenix Conference on Computers and communications, pp.703-709 , 1991 .
[8] soleymanpour m.javad Fault To levant Dedign of anyan Switch ,Communications Conference, Ikt Jan, IEEE 2004.
[9] Contribution of Packet Sizes to Packet and Byte Volumes, MCI vBNS http://www.nlanr.net/NA/Learn/ packetsize.html.
[10] Flow Counts as a Function of Flow Granularity, FIX-West,http://www.nlanr.ner/NA/Learn/aggregation.html.
[11] N. McKeown, Scheduling Algorithms for Input-Queued Cell Switches,Ph.D. thesis, Univ. Calif. Berkeley, May 1995.
[12] "Huffman encoding Data" URL:http://www.byui.edu/ricks/employee_ /C...5/chap10.5.pdf
[13] "Compressing Data" URL:http://ginger.cs.uwp.edu/C580/LZWovrhd.pdf
[14] N. McKeown, V. Anantharam, and J. Walrand, Achieving 100% Throughput in an Input-Queued Switch, Proc. IEEE INFOCOM 96, San Francisco, CA, Mar. 1996.
[15] C. Labovitz, G. R. Malan, and F. Jahanian, Internet Routing Instability, Proc. ACM SIGCOMM 97, Cannes, France, Sept. 1997.
[16] Han Wang, Hardware Designs for LT Coding, Faculty of Electrical Engineering, Mathematics and Computer Science, 2006 World Academy of Science, Engineering and Technology 30 200939