A Study of the Trade-off Energy Consumption-Performance-Schedulability for DVFS Multicore Systems

Authors: Jalil Boudjadar

Abstract:

Dynamic Voltage and Frequency Scaling (DVFS) multicore platforms are promising execution platforms that enable high computational performance, less energy consumption and flexibility in scheduling the system processes. However, the resulting interleaving and memory interference together with per-core frequency tuning make real-time guarantees hard to be delivered. Besides, energy consumption represents a strong constraint for the deployment of such systems on energy-limited settings. Identifying the system configurations that would achieve a high performance and consume less energy while guaranteeing the system schedulability is a complex task in the design of modern embedded systems. This work studies the trade-off between energy consumption, cores utilization and memory bottleneck and their impact on the schedulability of DVFS multicore time-critical systems with a hierarchy of shared memories. We build a model-based framework using Parametrized Timed Automata of UPPAAL to analyze the mutual impact of performance, energy consumption and schedulability of DVFS multicore systems, and demonstrate the trade-off on an actual case study.

Keywords: Time-critical systems, multicore systems, schedulability analysis, performance, memory interference, energy consumption.

References:

[1] G. M. Almeida, R. Busseuil, E. A. Carara, N. Hbert, S. Varyani, G. Sassatelli, P. Benoit, L. Torres, and F. G. Moraes. Predictive dynamic frequency scaling for multi-processor systems-on-chip. In ISCAS’11, pages 1500–1503, 2011.
[2] M. Bambagini, M. Marinoni, H. Aydin, and G. Buttazzo. Energy-aware scheduling for real-time systems: A survey. ACM Trans. Embed. Comput. Syst., 15(1):7:1–7:34, Jan. 2016.
[3] S. K. Baruah, L. Cucu-Grosjean, R. I. Davis, and C. Maiza. Mixed Criticality on Multicore/Manycore Platforms (Dagstuhl Seminar 15121). Dagstuhl Reports, 5(3):84–142, 2015.
[4] J.-P. Bodeveix, A. Boudjadar, and M. Filali. An alternative definition for timed automata composition. In Automated Technology for Verification and Analysis, pages 105–119, Berlin, Heidelberg, 2011. Springer Berlin Heidelberg.
[5] A. Boudjadar, A. David, J. H. Kim, K. G. Larsen, M. Mikucionis, U. Nyman, and A. Skou. Statistical and exact schedulability analysis of hierarchical scheduling systems. Sci. Comput. Program., 127:103–130, 2016.
[6] A. Boudjadar, A. David, J. H. Kim, K. G. Larsen, M. Mikuionis, U. Nyman, and A. Skou. A reconfigurable framework for compositional schedulability and power analysis of hierarchical scheduling systems with frequency scaling. Science of Computer Programming, 113:236 – 260, 2015.
[7] A. J. Boudjadar, A. David, J. H. Kim, K. G. Larsen, M. Mikucionis, U. Nyman, and A. Skou. Degree of schedulability of mixed-criticality real-time systems with probabilistic sporadic tasks. In 2014 Theoretical Aspects of Software Engineering Conference - TASE, pages 126–130, 2014.
[8] J. Boudjadar, A. David, J. Kim, K. Larsen, U. Nyman, and A. Skou. Schedulability and energy efficiency for multi-core hierarchical scheduling systems. In Proceedings of the European Congress on Embedded Real Time Systems and Software - ERTS2 2014, pages 1–4, 2014.
[9] J. Boudjadar, J. H. Kim, and S. Nadjm-Tehrani. Performance-aware scheduling of multicore time-critical systems. In 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, MEMOCODE, pages 105–114. IEEE, 2016.
[10] F. Cassez and K. G. Larsen. The impressive power of stopwatches. In CONCUR’00, volume 1877 of LNCS, pages 138–152, 2000.
[11] X. Chen, Z. Xu, H. Kim, P. V. Gratz, J. Hu, M. Kishinevsky, U. Ogras, and R. Ayoub. Dynamic voltage and frequency scaling for shared resources in multicore processor designs. In 50th ACM/EDAC/IEEE Design Automation Conference (DAC), pages 1–7, 2013.
[12] Y. L. Chen, M. F. Chang, and W. Y. Liang. Dynamic voltage and frequency scaling based parallel scheduling scheme for video recognition on multicore systems. In IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW), pages 1–2, 2016.
[13] A. K. Datta and R. Patel. Cpu scheduling for power/energy management on multicore processors using cache miss and context switch data. IEEE Transactions on Parallel and Distributed Systems, 25(5):1190–1199, May 2014.
[14] A. David, K. G. Larsen, A. Legay, M. Mikucionis, D. B. Poulsen, J. van Vliet, and Z. Wang. Statistical model checking for networks of priced timed automata. In FORMATS, volume 6919 of LNCS, pages 80–96. Springer, 2011.
[15] C. Ferdinand and R. Wilhelm. Efficient and precise cache behavior prediction for real-time systems. Real-Time Syst, 17(2-3):131–181, 1999.
[16] P. Huyck. Arinc 653 and multi-core microprocessors; considerations and potential impacts. In DASC’12, pages 6B4–1–6B4–7, 2012.
[17] C. Isci, A. Buyuktosunoglu, C.-Y. Cher, P. Bose, and M. Martonosi. An analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget. In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 39, pages 347–358. IEEE Computer Society, 2006.
[18] A. Kandhalu, J. Kim, K. Lakshmanan, and R. Rajkumar. Energy-aware partitioned fixed-priority scheduling for chip multi-processors. In 2011 IEEE 17th International Conference on Embedded and Real-Time Computing Systems and Applications, volume 1, pages 93–102, 2011.
[19] H. Karray, M. Paulitsch, B. Koppenhoefer, and D. Geiger. Design and implementation of a degraded vision landing aid application on a multicore processor architecture for safety-critical application. In 16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, ISORC, pages 1–8. IEEE Computer Society, 2013.
[20] B. Kim, L. Feng, L. T. X. Phan, O. Sokolsky, and I. Lee. Platform-specific timing verification framework in model-based implementation. In 2015 Design, Automation Test in Europe Conference Exhibition (DATE), pages 235–240, 2015.
[21] H. Kim, D. de Niz, B. Andersson, M. H. Klein, O. Mutlu, and R. Rajkumar. Bounding memory interference delay in COTS-based multi-core systems. In RTAS’14, pages 145–154, 2014.
[22] H. Kim, A. Kandhalu, and R. Rajkumar. A coordinated approach for practical os-level cache management in multi-core real-time systems. In ECRTS13, pages 80–89, 2013.
[23] J. H. Kim, A. Boudjadar, U. Nyman, M. Mikucionis, K. G. Larsen, and I. Lee. Quantitative schedulability analysis of continuous probability tasks in a hierarchical context. In 2015 18th International ACM SIGSOFT Symposium on Component-Based Software Engineering (CBSE), pages 91–100, 2015.
[24] Y. Li, J. Niu, M. Atiquzzaman, and X. Long. Energy-aware scheduling on heterogeneous multi-core systems with guaranteed probability. Journal of Parallel and Distributed Computing, 103:64 – 76, 2017. Special Issue on Scalable Cyber-Physical Systems.
[25] C. C. Lin, C. J. Chang, Y. C. Syu, J. J. Wu, P. Liu, P. W. Cheng, and W. T. Hsu. An energy-efficient task scheduler for multi-core platforms with per-core dvfs based on task characteristics. In 43rd International Conference on Parallel Processing, pages 381–390, 2014.
[26] A. L¨ofwenmark and S. Nadjm-Tehrani. Challenges in future avionic systems on multi-core platforms. In 2014 IEEE International Symposium on Software Reliability Engineering Workshops, pages 115–119, 2014.
[27] J. Lu and Y. Guo. Energy-aware fixed-priority multi-core scheduling for real-time systems. In 2011 IEEE 17th International Conference on Embedded and Real-Time Computing Systems and Applications, volume 1, pages 277–281, 2011.
[28] J. Nowotsch, M. Paulitsch, D. Buhler, H. Theiling, S. Wegener, and M. Schmidt. Multi-core interference-sensitive WCET analysis leveraging runtime resource capacity enforcement. In Proceedings of ECRTS’14, pages 109–118, 2014.
[29] C. Poellabauer, T. Zhang, S. Pande, and K. Schwan. An efficient frequency scaling approach for energy-aware embedded real-time systems. In M. Beigl and P. Lukowicz, editors, Systems Aspects in Organic and Pervasive Computing - ARCS 2005: 18th International Conference on Architecture of Computing Systems, 2005., pages 207–221, Berlin, Heidelberg, 2005. Springer Berlin Heidelberg.
[30] S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, and J. D. Owens. Memory access scheduling. In ISCA ’00, pages 128–138. ACM, 2000.
[31] RTCA. DO-297/ED-124 - Integrated Modular Avionics (IMA) Development Guidance and Certification Considerations, 2005.
[32] S. R. Sarangi, B. Greskamp, and J. Torrellas. Cadre: Cycle-accurate deterministic replay for hardware debugging. In Proceedings of the International Conference on Dependable Systems and Networks, pages 301–312, Washington, DC, USA, 2006. IEEE Computer Society.
[33] L. Subramanian, V. Seshadri, Y. Kim, B. Jaiyen, and O. Mutlu. Mise: Providing performance predictability and improving fairness in shared main memory systems. In HPCA’13, pages 639–650, 2013.
[34] J. R. Tramm and A. R. Siegel. Memory bottlenecks and memory contention in multi-core monte carlo transport codes. Annals of Nuclear Energy, 82:195 – 202, 2015. Joint International Conference on Supercomputing in Nuclear Applications and Monte Carlo 2013, SNA + MC 2013. Pluri- and Trans-disciplinarity, Towards New Modeling and Numerical Simulation Paradigms.
[35] G. Yao, R. Pellizzoni, S. Bak, H. Yun, and M. Caccamo. Global real-time memory-centric scheduling for multicore systems. IEEE Trans. Computers, 65(9):2739–2751, 2016.
[36] Y. Ye, R. West, Z. Cheng, and Y. Li. Coloris: A dynamic cache partitioning system using page coloring. In Proceedings of PACT ’14, pages 381–392, 2014.