Commenced in January 2007
Paper Count: 30077
An Analysis of Genetic Algorithm Based Test Data Compression Using Modified PRL Coding
Abstract:In this paper genetic based test data compression is targeted for improving the compression ratio and for reducing the computation time. The genetic algorithm is based on extended pattern run-length coding. The test set contains a large number of X value that can be effectively exploited to improve the test data compression. In this coding method, a reference pattern is set and its compatibility is checked. For this process, a genetic algorithm is proposed to reduce the computation time of encoding algorithm. This coding technique encodes the 2n compatible pattern or the inversely compatible pattern into a single test data segment or multiple test data segment. The experimental result shows that the compression ratio and computation time is reduced.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1338510Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1434
 X.Kavousianos, E. Kalligerous and D. Nikolos, “Optimal selective Huffman coding for test-data compression”, IEEE Trans. Comput., vol.56, no. 8, pp. 1146 – 1152, Aug 2007.
 Zhanglei Wang, Member, IEEE, and KrishnenduChakrabarty, “Test Data Compression Using SelectiveEncoding of Scan Slices”, IEEE Trans. on VLSI system, vol. 16, no. 11, Nov. 2008.
 P.T.Gonciari, B. Al-Hashimi, and N.Nicolici, “Variable – length input Huffman coding for system-on-a-chip test”, IEEE Trans. Comput. Aided Des.Integr. Circuits Syst., vol. 22, no. 6, pp. 783-796, Jun 2003.
 X.Raun and R.Katti, “A efficient data – independent technique for compression test vectors in systems –on – a – chip”, in Proc. IEEE comput. Soc. Annu. Symp.Emerging VLSI Technol. Archit., Washington, DC 2006, pp153-158.
 M.Tehranipoor, M.Nourani and K.Chakrabarty, “Nine-coded compression technique for testing embedded cores in SoCs,” IEEE Trans. VLSI Syst., vol.13, no.6, pp. 719-731, Jun.2005.
 Kedarnath J. Balakrishnan and NurA.Touba, “Relationship between Entropy and Test Data Compression”, in IEEE trans. on CAD of Integrated circuits and system, vol. 26, no.2, Feb 2007.
 Lung – Jen Lee, Wang – Dauh Tseng, Rung – Bin Lin, and Cheng – Ho Chang, “2n Pattern Run-Length for Test Data Compression”, in IEEE trans. on CAD of Integrated circuits and system, vol. 31, no.4, April 2012.
 Maoxiang Yi, Huaguo Liang, Lei Zhang and Wenfa Zhan, “A Novel Xploiting Strategy for Improving Performance of Test Data Compression”, in IEEE Trans. on VLSI system, vol. 18, no. 02, Feb. 2010.
 CinziaBernardeschi, Luca Cassano, Mario G.C.A. Cimino, Andrea Domenci, “GABES: A Genetic Algorithm Based Environment for SEU Testing in SRAM-FPGAs”, in journal of system architecture, pp 1243 – 1254, 2013.
 HalinaKwasnicka and Michal Przewozniczek, “Multi population Pattern Searching Algorithm: A New Evolutionary Method Based on the Idea of Messy Algorithm”, IEEE Trans. on evolution computation vol. 15 No. 5, pp 715 – 734, Oct. 2011.
 Jervan, G. Eles, P., ZeboPeng ,Ubar, R., and Jenihhin, M., “Test time minimization for hybrid BIST of core-based systems”, VLSI test symposium, 2014.
 Jervan, G. Eles, P., ZeboPeng ,Ubar, R., and Jenihhin, M., “Hybrid BIST time minimization for core-based systems with STUMPS architecture”, VLSI test symposium, 2014.
 T. Garbolino, G. Papa, Genetic algorithm for test pattern generator design, Applied Intelligence 32 (2) (2010) 193–204.
 A. Jas, J. Ghosh-Dastidar, and N. A. Touba, “Scan vector compression / decompression using statistical coding,” in Proc. IEEE VLSI Test Symp., Apr. 1999, pp. 114–121.
 A. Chandra and K. Chakrabarty, “System-on-a-chip test data compression and decompression architectures based on Golomb codes,” IEEE Trans. Computer-Aided Design, vol. 20, pp. 113–120, Mar. 2001.
 “Frequency-Directed Run-Length (FDR) codes with application to system-on-a-chip test data compression,” in Proc. IEEE VLSI Test Symp., Apr. 2001, pp. 114–121.
 P. T. Gonciari, B. M. Al-Hashimi, and N. Nicolici, “Variable-length input Huffman coding for system-on-a-chip test,” IEEE Trans. Comput.-Aided Design Integr. Circuit Syst., vol. 22, no. 6, pp. 783–796, Jun. 2003.