Commenced in January 2007
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I²C Master-Slave Integration

Authors: Rozita Borhan, Lam Kien Sieng

Abstract:

This paper describes I²C Slave implementation using I²C master obtained from the OpenCores website. This website provides free Verilog and VHDL Codes to users. The design implementation for the I²C slave is in Verilog Language and uses EDA tools for ASIC design known as ModelSim from Mentor Graphic. This tool is used for simulation and verification purposes. Common application for this I²C Master-Slave integration is also included. This paper also addresses the advantages and limitations of the said design.

Keywords: Verification, verilog, I²C, master, OpenCores, slave

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1338470

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References:


[1] Liang, “I2C Master Core Specification,” http://www.opencores.org, Rev:1.0 2004-7-28 , 2004
[2] Vishay Semiconductor datasheet, “Fully Integrated Proximity and Ambient Light Sensor with Infrared Sensor and I2C Interface”, http://vishay.com, 2011, page 12.
[3] Yifan L, and Fei M, “ Principle of I2C bus and its Application in IC Design”2007
[4] B. Matthew, “Overview of I2C”, http://components.about.com/od/Theory/a/Overview-Of-I2c.htm, date visited: 25 April 2015.
[5] C. S. Sansar, “Design & Implementation of I2C Master Controller Interfaced With RAM Using VHDL”, Journal of Engineering Research and Applications, Vol 4, Issue 7, July 2014, page 67-70