A 1.2-ns16×16-Bit Binary Multiplier Using High Speed Compressors

Authors: A. Dandapat, S. Ghosal, P. Sarkar, D. Mukhopadhyay

Abstract:

For higher order multiplications, a huge number of adders or compressors are to be used to perform the partial product addition. We have reduced the number of adders by introducing special kind of adders that are capable to add five/six/seven bits per decade. These adders are called compressors. Binary counter property has been merged with the compressor property to develop high order compressors. Uses of these compressors permit the reduction of the vertical critical paths. A 16×16 bit multiplier has been developed using these compressors. These compressors make the multipliers faster as compared to the conventional design that have been used 4-2 compressors and 3-2 compressors.

Keywords: Binary multiplier, Compressors, Counter, Column adder, Low power.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1334155

References:

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