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High-Speed Pipeline Implementation of Radix-2 DIF Algorithm

Authors: Christos Meletis, Paul Bougas, George Economakos, Paraskevas Kalivas, Kiamal Pekmestzi

Abstract:

In this paper, we propose a new architecture for the implementation of the N-point Fast Fourier Transform (FFT), based on the Radix-2 Decimation in Frequency algorithm. This architecture is based on a pipeline circuit that can process a stream of samples and produce two FFT transform samples every clock cycle. Compared to existing implementations the architecture proposed achieves double processing speed using the same circuit complexity.

Keywords: Digital Signal Processing, systolic circuits, FFTalgorithm

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1075597

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[1] C.-H. Chang, C.-L. Wang, Y.-T. Chang, "Efficient VLSI architectures for fast computation of the discrete Fourier transform and its inverse," IEEE Trans. on Signal Processing, vol. 48, Nov. 2000, pp. 3206-3216.
[2] J. Choi and V. Boriakoff, "A new linear systolic array for FFT computation," IEEE Trans. Circuits Syst. II, vol. 39, Apr. 1992, pp. 236-239.
[3] V. Boriakoff, "FFT computation with systolic arrays, a new architecture," IEEE Trans. Circuits Syst. II, vol. 41, Apr. 1994, pp. 278-284.
[4] L.-W Chang and M.-Y. Wu, "A new systolic array for discrete Fourier transform," IEEE Trans. Acoust., Speech, Signal Processing, vol.36, Oct. 1988, pp.1165-1167.
[5] N. R. Murphy and M. N. S. Swamy, "On the real-time computation of DFT and DCT through systolic architecture, " IEEE Trans. Signal Processing, vol. 42, Apr. 1993, pp. 988-991.
[6] E. H. Wold and A. M. Despain, "Pipeline and parallel-pipeline FFT processors for VLSI implementations," IEEE Trans. On Computers, vol. C-33, No 5, pp. 414-426, May 1984.
[7] N. Weste and D. J. Skellern, "VLSI for OFDM," IEEE Communications Magazine, pp. 127-131, Oct. 1998
[8] E. Bidet, D. Castelain, C. Joanblanq and P. Senn, "A Fast-Chip implementation of 8192 complex point FFT," IEEE Journal of Solid-State Circuits, vol 30, No.3, pp. 300-305, March 1995.
[9] K. Z. Pekmestzi, "Complex number multipliers," IEE Proceedings, Vol.136, Part E, No. 1, pp. 70-75, Jan. 1989.