Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 8

VHDL Related Publications

8 A High Level Implementation of a High Performance Data Transfer Interface for NoC

Authors: R. K. SHARMA, Mansi Jhamb, A. K. Gupta

Abstract:

The distribution of a single global clock across a chip has become the major design bottleneck for high performance VLSI systems owing to the power dissipation, process variability and multicycle cross-chip signaling. A Network-on-Chip (NoC) architecture partitioned into several synchronous blocks has become a promising approach for attaining fine-grain power management at the system level. In a NoC architecture the communication between the blocks is handled asynchronously. To interface these blocks on a chip operating at different frequencies, an asynchronous FIFO interface is inevitable. However, these asynchronous FIFOs are not required if adjacent blocks belong to the same clock domain. In this paper, we have designed and analyzed a 16-bit asynchronous micropipelined FIFO of depth four, with the awareness of place and route on an FPGA device. We have used a commercially available Spartan 3 device and designed a high speed implementation of the asynchronous 4-phase micropipeline. The asynchronous FIFO implemented on the FPGA device shows 76 Mb/s throughput and a handshake cycle of 109 ns for write and 101.3 ns for read at the simulation under the worst case operating conditions (voltage = 0.95V) on a working chip at the room temperature.

Keywords: FPGA, VHDL, Asynchronous, FIFO, GALS, Network-on- Chip (NoC)

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7 FPGA Implementation of RSA Encryption Algorithm for E-Passport Application

Authors: Khaled Shehata, Hanady Hussien, Sara Yehia

Abstract:

Securing the data stored on E-passport is a very important issue. RSA encryption algorithm is suitable for such application with low data size. In this paper the design and implementation of 1024 bit-key RSA encryption and decryption module on an FPGA is presented. The module is verified through comparing the result with that obtained from MATLAB tools. The design runs at a frequency of 36.3 MHz on Virtex-5 Xilinx FPGA. The key size is designed to be 1024-bit to achieve high security for the passport information. The whole design is achieved through VHDL design entry which makes it a portable design and can be directed to any hardware platform.

Keywords: FPGA, RSA, VHDL, modular multiplication, modular exponential

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6 Spacecraft Neural Network Control System Design using FPGA

Authors: Faten H. Fahmy, Hassen T. Dorrah, Hanaa T. El-Madany, Ninet M. A. El-Rahman

Abstract:

Designing and implementing intelligent systems has become a crucial factor for the innovation and development of better products of space technologies. A neural network is a parallel system, capable of resolving paradigms that linear computing cannot. Field programmable gate array (FPGA) is a digital device that owns reprogrammable properties and robust flexibility. For the neural network based instrument prototype in real time application, conventional specific VLSI neural chip design suffers the limitation in time and cost. With low precision artificial neural network design, FPGAs have higher speed and smaller size for real time application than the VLSI and DSP chips. So, many researchers have made great efforts on the realization of neural network (NN) using FPGA technique. In this paper, an introduction of ANN and FPGA technique are briefly shown. Also, Hardware Description Language (VHDL) code has been proposed to implement ANNs as well as to present simulation results with floating point arithmetic. Synthesis results for ANN controller are developed using Precision RTL. Proposed VHDL implementation creates a flexible, fast method and high degree of parallelism for implementing ANN. The implementation of multi-layer NN using lookup table LUT reduces the resource utilization for implementation and time for execution.

Keywords: Neural Network, Spacecraft, FPGA, VHDL

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5 Real-Time Digital Oscilloscope Implementation in 90nm CMOS Technology FPGA

Authors: Nasir Mehmood, Jens Ogniewski, Vinodh Ravinath

Abstract:

This paper describes the design of a real-time audiorange digital oscilloscope and its implementation in 90nm CMOS FPGA platform. The design consists of sample and hold circuits, A/D conversion, audio and video processing, on-chip RAM, clock generation and control logic. The design of internal blocks and modules in 90nm devices in an FPGA is elaborated. Also the key features and their implementation algorithms are presented. Finally, the timing waveforms and simulation results are put forward.

Keywords: VLSI, CMOS, VHDL, Oscilloscope, Field Programmable Gate Array (FPGA), Video Graphics Array (VGA)

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4 Hardware Prototyping of an Efficient Encryption Engine

Authors: Muhammad I. Ibrahimy, Mamun B.I. Reaz, Khandaker Asaduzzaman, Sazzad Hussain

Abstract:

An approach to develop the FPGA of a flexible key RSA encryption engine that can be used as a standard device in the secured communication system is presented. The VHDL modeling of this RSA encryption engine has the unique characteristics of supporting multiple key sizes, thus can easily be fit into the systems that require different levels of security. A simple nested loop addition and subtraction have been used in order to implement the RSA operation. This has made the processing time faster and used comparatively smaller amount of space in the FPGA. The hardware design is targeted on Altera STRATIX II device and determined that the flexible key RSA encryption engine can be best suited in the device named EP2S30F484C3. The RSA encryption implementation has made use of 13,779 units of logic elements and achieved a clock frequency of 17.77MHz. It has been verified that this RSA encryption engine can perform 32-bit, 256-bit and 1024-bit encryption operation in less than 41.585us, 531.515us and 790.61us respectively.

Keywords: Security, Communication, FPGA, RSA, VHDL

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3 Efficient Hardware Realization of Truncated Multipliers using FPGA

Authors: Muhammad H. Rais

Abstract:

Truncated multiplier is a good candidate for digital signal processing (DSP) applications including finite impulse response (FIR) and discrete cosine transform (DCT). Through truncated multiplier a significant reduction in Field Programmable Gate Array (FPGA) resources can be achieved. This paper presents for the first time a comparison of resource utilization of Spartan-3AN and Virtex-5 implementation of standard and truncated multipliers using Very High Speed Integrated Circuit Hardware Description Language (VHDL). The Virtex-5 FPGA shows significant improvement as compared to Spartan-3AN FPGA device. The Virtex-5 FPGA device shows better performance with a percentage ratio of number of occupied slices for standard to truncated multipliers is increased from 40% to 73.86% as compared to Spartan- 3AN is decreased from 68.75% to 58.78%. Results show that the anomaly in Spartan-3AN FPGA device average connection and maximum pin delay have been efficiently reduced in Virtex-5 FPGA device.

Keywords: VHDL, Digital Signal Processing (DSP), FieldProgrammable Gate Array (FPGA), Spartan-3AN, TruncatedMultiplier, Virtex-5

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2 Asynchronous Microcontroller Simulation Model in VHDL

Authors: M. Kovac

Abstract:

This article describes design of the 8-bit asynchronous microcontroller simulation model in VHDL. The model is created in ISE Foundation design tool and simulated in Modelsim tool. This model is a simple application example of asynchronous systems designed in synchronous design tools. The design process of creating asynchronous system with 4-phase bundled-data protocol and with matching delays is described in the article. The model is described in gate-level abstraction. The simulation waveform of the functional construction is the result of this article. Described construction covers only the simulation model. The next step would be creating synthesizable model to FPGA.

Keywords: FPGA, microcontroller, VHDL, Asynchronous

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1 FPGA Implementation of the “PYRAMIDS“ Block Cipher

Authors: A. AlKalbany, H. Al hassan, M. Saeb

Abstract:

The “PYRAMIDS" Block Cipher is a symmetric encryption algorithm of a 64, 128, 256-bit length, that accepts a variable key length of 128, 192, 256 bits. The algorithm is an iterated cipher consisting of repeated applications of a simple round transformation with different operations and different sequence in each round. The algorithm was previously software implemented in Cµ code. In this paper, a hardware implementation of the algorithm, using Field Programmable Gate Arrays (FPGA), is presented. In this work, we discuss the algorithm, the implemented micro-architecture, and the simulation and implementation results. Moreover, we present a detailed comparison with other implemented standard algorithms. In addition, we include the floor plan as well as the circuit diagrams of the various micro-architecture modules.

Keywords: Cryptography, Algorithm, Encryption, FPGA, VHDL, micro-architecture, data communication security

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