Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 2

stack effect Related Publications

2 Stack Ventilation for an Office Building with a Multi-Story Atrium

Authors: Wei-Hwa Chiang, Karina Natali

Abstract:

This study examines the stack ventilation performance of an office building located in Taipei, Taiwan. Atriums in this building act as stacks that facilitate buoyancy-driven ventilation. Computational Fluid Dynamic (CFD) simulations are used to identify interior airflow patterns, and then used these patterns to assess the building’s heat expulsion efficiency. Ambient temperatures of 20°C were adopted as the typical seasonal spring temperature range in Taipei. Further, “zero-wind” conditions are established to ensure simulation results reflected only the buoyancy effect. After checking results against neutral pressure level (NPL) level, airflow, air velocity, and indoor temperature stratification, the lower stack is modified to reduce the NPL in order to remove heat accumulated on the top floor.

Keywords: Thermal comfort, natural ventilation, stack effect, side outlet

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1 An Efficient VLSI Design Approach to Reduce Static Power using Variable Body Biasing

Authors: Md. Asif Jahangir Chowdhury, Md. Shahriar Rizwan, M. S. Islam

Abstract:

In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling. Recently, the power density has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. As a result static power consumption is becoming more dominant. This is a challenge for the circuit designers. However, the designers do have a few methods which they can use to reduce this static power consumption. But all of these methods have some drawbacks. In order to achieve lower static power consumption, one has to sacrifice design area and circuit performance. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using Variable Body Biasing technique without being penalized in area requirement and circuit performance.

Keywords: stack effect, variable body biasing, state saving technique, dual V-th, static power reduction

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