Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 7

SoC Related Publications

7 Test Data Compression Using a Hybrid of Bitmask Dictionary and 2n Pattern Runlength Coding Methods

Authors: C. Kalamani, K. Paramasivam

Abstract:

In VLSI, testing plays an important role. Major problem in testing are test data volume and test power. The important solution to reduce test data volume and test time is test data compression. The Proposed technique combines the bit maskdictionary and 2n pattern run length-coding method and provides a substantial improvement in the compression efficiency without introducing any additional decompression penalty. This method has been implemented using Mat lab and HDL Language to reduce test data volume and memory requirements. This method is applied on various benchmark test sets and compared the results with other existing methods. The proposed technique can achieve a compression ratio up to 86%.

Keywords: SoC, System-On-Chip, Bit Mask dictionary, test data compression

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6 Integrate Communication Modeling into the Design Modeling at Early Stages of the Design Flow Case Study: Unmanned Aerial Vehicle (UAV)

Authors: Ibrahim A. Aref, Tarek A. El-Mihoub

Abstract:

This paper shows how we can integrate communication modeling into the design modeling at early stages of the design flow. We consider effect of incorporating noise such as impulsive noise on system stability. We show that with change of the system model and investigate the system performance under the different communication effects. We modeled a unmanned aerial vehicle (UAV) as a demonstration using SystemC methodology. Moreover the system is modeled by joining the capabilities of UML and SystemC to operate at system level.

Keywords: Simulation, Modelling, UAV, SoC, systemC

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5 State of Charge Estimator Based On High-Gain Observer for Lithium-Ion Batteries

Authors: Won-Ho Kim, Moonjung Kim, Chang-Ho Hyun, Jaeho Han

Abstract:

This paper introduces a high-gain observer based state of charge(SOC) estimator for lithium-Ion batteries. The proposed SOC estimator has a high-gain observer(HGO) structure. The HGO scheme enhances the transient response speed and diminishes the effect of uncertainties. Furthermore, it guarantees that the output feedback controller recovers the performance of the state feedback controller when the observer gain is sufficiently high. In order to show the effectiveness of the proposed method, the linear RC battery model in ADVISOR is used. The performance of the proposed method is compared with that of the conventional linear observer(CLO) and some simulation result is given.

Keywords: SoC, robust, uncertainties, observer, high-gain

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4 System-Level Energy Estimation for SoC based on the Dynamic Behavior of Embedded Software

Authors: Yoshifumi Sakamoto, Kouichi Ono, Takeo Nakada, Yousuke Kubo, Hiroto Yasuura

Abstract:

This paper describes a system-level SoC energy consumption estimation method based on a dynamic behavior of embedded software in the early stages of the SoC development. A major problem of SOC development is development rework caused by unreliable energy consumption estimation at the early stages. The energy consumption of an SoC used in embedded systems is strongly affected by the dynamic behavior of the software. At the early stages of SoC development, modeling with a high level of abstraction is required for both the dynamic behavior of the software, and the behavior of the SoC. We estimate the energy consumption by a UML model-based simulation. The proposed method is applied for an actual embedded system in an MFP. The energy consumption estimation of the SoC is more accurate than conventional methods and this proposed method is promising to reduce the chance of development rework in the SoC development. ∈

Keywords: Modeling, Energy Consumption, UML, SoC, Dynamic Behavior, Embedded Sytem, Model-based simulation

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3 An Innovative Wireless Sensor Network Protocol Implementation using a Hybrid FPGA Technology

Authors: Tuan DANG, Danielle Reichel, Antoine Druilhe

Abstract:

Traditional development of wireless sensor network mote is generally based on SoC1 platform. Such method of development faces three main drawbacks: lack of flexibility in terms of development due to low resource and rigid architecture of SoC; low capability of evolution and portability versus performance if specific micro-controller architecture features are used; and the rapid obsolescence of micro-controller comparing to the long lifetime of power plants or any industrial installations. To overcome these drawbacks, we have explored a new approach of development of wireless sensor network mote using a hybrid FPGA technology. The application of such approach is illustrated through the implementation of an innovative wireless sensor network protocol called OCARI.

Keywords: Durability, Embedded system, Wireless Sensor Network, SoC, Flexibility, Hybrid FPGA, Mote, OCARI protocol

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2 Self Compensating ON Chip LDO Voltage Regulator in 180nm

Authors: SreehariRao Patri, K. S. R. KrishnaPrasad

Abstract:

An on chip low drop out voltage regulator that employs elegant compensation scheme is presented in this paper. The novelty in this design is that the device parasitic capacitances are exploited for compensation at different loads. The proposed LDO is designed to provide a constant voltage of 1.2V and is implemented in UMC 180 nano meter CMOS technology. The voltage regulator presented improves stability even at lighter loads and enhances line and load regulation.

Keywords: Analog, SoC, LDO

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1 A Generic and Extensible Spidergon NoC

Authors: Abdelkrim Zitouni, Mounir Zid, Sami Badrouchi, Rached Tourki

Abstract:

The Globally Asynchronous Locally Synchronous Network on Chip (GALS NoC) is the most efficient solution that provides low latency transfers and power efficient System on Chip (SoC) interconnect. This study presents a GALS and generic NoC architecture based on a configurable router. This router integrates a sophisticated dynamic arbiter, the wormhole routing technique and can be configured in a manner that allows it to be used in many possible NoC topologies such as Mesh 2-D, Tree and Polygon architectures. This makes it possible to improve the quality of service (QoS) required by the proposed NoC. A comparative performances study of the proposed NoC architecture, Tore architecture and of the most used Mesh 2D architecture is performed. This study shows that Spidergon architecture is characterised by the lower latency and the later saturation. It is also shown that no matter what the number of used links is raised; the Links×Diameter product permitted by the Spidergon architecture remains always the lower. The only limitation of this architecture comes from it-s over cost in term of silicon area.

Keywords: SoC, Dynamic arbiter, Generic router, Spidergon NoC

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