Search results for: tuning circuit

Authors: Md. Asif Jahangir Chowdhury, Md. Shahriar Rizwan, M. S. Islam

Abstract:

In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling. Recently, the power density has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. As a result static power consumption is becoming more dominant. This is a challenge for the circuit designers. However, the designers do have a few methods which they can use to reduce this static power consumption. But all of these methods have some drawbacks. In order to achieve lower static power consumption, one has to sacrifice design area and circuit performance. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using Variable Body Biasing technique without being penalized in area requirement and circuit performance.

Keywords: variable body biasing, state saving technique, stack effect, dual V-th, static power reduction.

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Authors: J. Mohan, S. Maheshwari

Abstract:

A new circuit topology realizing a first-order currentmode all-pass filter is proposed using two dual-output second generation current conveyor and two passive components. The circuit possesses low-input and high-output impedance, which makes it ideal for current-mode systems. The proposed circuit is verified through PSPICE simulation results.

Keywords: active filter, all-pass filter, current-mode, current conveyor.

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Authors: Chenguang Guo, Lei Chen, Yanlong Zhang

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This paper describes a novel optimized JTAG interface circuit between a JTAG controller and target IC. Being able to access JTAG using only one or two pins, this circuit does not change the original boundary scanning test frequency of target IC. Compared with the traditional JTAG interface which based on IEEE std. 1149.1, this reduced pin technology is more applicability in pin limited devices, and it is easier to control the scale of target IC for the designer.

Keywords: Boundary scan, JTAG interface, Test frequency, Reduced pin

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Authors: Hee-Guk Chae, Bo-Bae Song, Kyoung-Il Do, Jeong-Yun Seo, Yong-Seo Koo

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In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage.

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Authors: A. Suleng, T. Jelstad Olsen, J. Šindler, P. Bárta

Abstract:

A dead leg is a typical subsea production system component. CFD is required to model heat transfer within the dead leg. Unfortunately its solution is time demanding and thus not suitable for fast prediction or repeated simulations. Therefore there is a need to create a thermal FEA model, mimicking the heat flows and temperatures seen in CFD cool down simulations. This paper describes the conventional way of tuning and a new automated way using parametric model order reduction (PMOR) together with an optimization algorithm. The tuned FE analyses replicate the steady state CFD parameters within a maximum error in heat flow of 6 % and 3 % using manual and PMOR method respectively. During cool down, the relative error of the tuned FEA models with respect to temperature is below 5% comparing to the CFD. In addition, the PMOR method obtained the correct FEA setup five times faster than the manually tuned FEA.

Keywords: CFD, convective heat, FEA, model tuning, subseaproduction

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Authors: Yoonsuh Jung

Abstract:

As DNA microarray data contain relatively small sample size compared to the number of genes, high dimensional models are often employed. In high dimensional models, the selection of tuning parameter (or, penalty parameter) is often one of the crucial parts of the modeling. Cross-validation is one of the most common methods for the tuning parameter selection, which selects a parameter value with the smallest cross-validated score. However, selecting a single value as an ‘optimal’ value for the parameter can be very unstable due to the sampling variation since the sample sizes of microarray data are often small. Our approach is to choose multiple candidates of tuning parameter first, then average the candidates with different weights depending on their performance. The additional step of estimating the weights and averaging the candidates rarely increase the computational cost, while it can considerably improve the traditional cross-validation. We show that the selected value from the suggested methods often lead to stable parameter selection as well as improved detection of significant genetic variables compared to the tradition cross-validation via real data and simulated data sets.

Keywords: Cross Validation, Parameter Averaging, Parameter Selection, Regularization Parameter Search.

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Authors: Aakash Subramanian, Vansh Pal Singh Makh, Abhijit Mitra

Abstract:

A new digital transceiver circuit for asynchronous frame detection is proposed where both the transmitter and receiver contain all digital components, thereby avoiding possible use of conventional devices like monostable multivibrators with unstable external components such as resistances and capacitances. The proposed receiver circuit, in particular, uses a combinational logic block yielding an output which changes its state as soon as the start bit of a new frame is detected. This, in turn, helps in generating an efficient receiver sampling clock. A data latching circuit is also used in the receiver to latch the recovered data bits in any new frame. The proposed receiver structure is also extended from 4- bit information to any general n data bits within a frame with a common expression for the output of the combinational logic block. Performance of the proposed hardware design is evaluated in terms of time delay, reliability and robustness in comparison with the standard schemes using monostable multivibrators. It is observed from hardware implementation that the proposed circuit achieves almost 33 percent speed up over any conventional circuit.

Keywords: Asynchronous Communication, Digital Detector, Combinational logic output, Sampling clock generator, Hardwareimplementation.

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Authors: Agord M. Pinto Jr., Yuzo Iano, Leandro T. Manera, Raphael R. N. Souza

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This paper describes an optimization tool-based design strategy for a Current Mode Logic CML divide-by-2 circuit. Representing a building block for output frequency generation in a RFID protocol based-frequency synthesizer, the circuit was designed to minimize the power consumption for driving of multiple loads with unbalancing (at transceiver level). Implemented with XFAB XC08 180 nm technology, the circuit was optimized through MunEDA WiCkeD tool at Cadence Virtuoso Analog Design Environment ADE.

Keywords: Divide-by-2 circuit, CMOS technology, PLL phase locked-loop, optimization tool, CML current mode logic, RF transceiver.

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Authors: Fotios N. Vlachos, Anastasios D. Garetsos, Nikolaos K. Uzunoglu, Efstathios D. Gotsis

Abstract:

A four element prototype phased array surface probe has been designed and constructed to improve clinical human prostate spectroscopic data. The probe consists of two pairs of adjacent rectangular coils with an optimum overlap to reduce the mutual inductance. The two pairs are positioned on the anterior and the posterior pelvic region and two couples of varactors at the input of each coil undertake the procedures of tuning and matching. The probe switches off and on automatically during the consecutive phases of the MR experiment with the use of an analog switch that is triggered by a microcontroller. Experimental tests that were carried out resulted in high levels of tuning accuracy. Also, the switching mechanism functions properly for various applied loads and pulse sequence characteristics, producing only 10 μs of latency.

Keywords: Automatic tuning, prostate imaging, phased array, spectroscopy.

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Authors: Jin-Sung Kim, Jin-Hwan Kim, Ji-Mo Park, Sung-Man Park, Won-Yong Choe, Hoon Heo

Abstract:

An optimal control of Reverse Osmosis (RO) plant is studied in this paper utilizing the auto tuning concept in conjunction with PID controller. A control scheme composing an auto tuning stochastic technique based on an improved Genetic Algorithm (GA) is proposed. For better evaluation of the process in GA, objective function defined newly in sense of root mean square error has been used. Also in order to achieve better performance of GA, more pureness and longer period of random number generation in operation are sought. The main improvement is made by replacing the uniform distribution random number generator in conventional GA technique to newly designed hybrid random generator composed of Cauchy distribution and linear congruential generator, which provides independent and different random numbers at each individual steps in Genetic operation. The performance of newly proposed GA tuned controller is compared with those of conventional ones via simulation.

Keywords: Genetic Algorithm, Auto tuning, Hybrid random number generator, Reverse Osmosis, PID controller

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Authors: C. Kalamani, V. Abishek Karthick, S. Anitha, K. Kavin Kumar

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The fault tolerant system plays a crucial role in the critical applications which are being used in the present scenario. A fault may change the functionality of circuits. Aim of this paper is to design multiplier using fault tolerant hybrid full adder. Fault tolerant hybrid full adder is designed to check and repair any fault in the circuit using self-checking circuit and the self-repairing circuit. Further, the use of conventional logic circuits may result in more area, delay as well as power consumption. In order to reduce these parameters of the circuit, GDI (Gate Diffusion Input) techniques with less number of transistors are used compared to conventional full adder circuit. This reduces the area, delay and power consumption. The proposed method solves the major problems occurring in the most crucial and critical applications.

Keywords: Gate diffusion input, hybrid full adder, self-checking, fault tolerant.

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Authors: H. Mansor, S. B. Mohd Noor

Abstract:

This paper presents a design method of self-tuning Quantitative Feedback Theory (QFT) by using improved deadbeat control algorithm. QFT is a technique to achieve robust control with pre-defined specifications whereas deadbeat is an algorithm that could bring the output to steady state with minimum step size. Nevertheless, usually there are large peaks in the deadbeat response. By integrating QFT specifications into deadbeat algorithm, the large peaks could be tolerated. On the other hand, emerging QFT with adaptive element will produce a robust controller with wider coverage of uncertainty. By combining QFT-based deadbeat algorithm and adaptive element, superior controller that is called selftuning QFT-based deadbeat controller could be achieved. The output response that is fast, robust and adaptive is expected. Using a grain dryer plant model as a pilot case-study, the performance of the proposed method has been evaluated and analyzed. Grain drying process is very complex with highly nonlinear behaviour, long delay, affected by environmental changes and affected by disturbances. Performance comparisons have been performed between the proposed self-tuning QFT-based deadbeat, standard QFT and standard dead-beat controllers. The efficiency of the self-tuning QFTbased dead-beat controller has been proven from the tests results in terms of controller’s parameters are updated online, less percentage of overshoot and settling time especially when there are variations in the plant.

Keywords: Deadbeat control, quantitative feedback theory (QFT), robust control, self-tuning control.

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Authors: Guiheng Zhang, Wei Zhang, Jun Fu, Yudong Wang

Abstract:

A 900 MHz three-stage SiGe power amplifier (PA) with high power gain is presented in this paper. Volterra Series is applied to analyze nonlinearity sources of SiGe HBT device model clearly. Meanwhile, the influence of operating current to IMD3 is discussed. Then a β-helper current mirror bias circuit is applied to improve linearity, since the β-helper current mirror bias circuit can offer stable base biasing voltage. Meanwhile, it can also work as predistortion circuit when biasing voltages of three bias circuits are fine-tuned, by this way, the power gain and operating current of PA are optimized for best linearity. The three power stages which fabricated by 0.18 μm SiGe technology are bonded to the printed circuit board (PCB) to obtain impedances by Load-Pull system, then matching networks are done for best linearity with discrete passive components on PCB. The final measured three-stage PA exhibits 21.1 dBm of output power at 1 dB compression point (OP1dB) with power added efficiency (PAE) of 20.6% and 33 dB power gain under 3.3 V power supply voltage.

Keywords: High gain power amplifier, linearization bias circuit, SiGe HBT model, Volterra Series.

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Authors: A. Kojah, A. Nacaroğlu

Abstract:

Single phase transmission lines are used to transfer data or energy between two users. Transient conditions such as switching operations and short circuit faults cause the generation of the fluctuation on the waveform to be transmitted. Spatial voltage distribution on the single phase transmission line may change owing to the position and duration of the short circuit fault in the system. In this paper, the state space representation of the single phase transmission line for short circuit fault and for various types of terminations is given. Since the transmission line is modeled in time domain using distributed parametric elements, the mathematical representation of the event is given in state space (time domain) differential equation form. It also makes easy to solve the problem because of the time and space dependent characteristics of the voltage variations on the distributed parametrically modeled transmission line.

Keywords: Energy transmission, transient effects, transmission line, transient voltage, RLC short circuit, single phase.

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Authors: Yahya Naderi, Tohid Rahimi, Babak Yousefi, Seyed Hossein Hosseini

Abstract:

Today’s modern interconnected power system is highly complex in nature. In this, one of the most important requirements during the operation of the electric power system is the reliability and security. Power and frequency oscillation damping mechanism improve the reliability. Because of power system stabilizer (PSS) low speed response against of major fault such as three phase short circuit, FACTs devise that can control the network condition in very fast time, are becoming popular. But FACTs capability can be seen in a major fault present when nonlinear models of FACTs devise and power system equipment are applied. To realize this aim, the model of multi-machine power system with FACTs controller is developed in MATLAB/SIMULINK using Sim Power System (SPS) blockiest. Among the FACTs device, Static synchronous series compensator (SSSC) due to high speed changes its reactance characteristic inductive to capacitive, is effective power flow controller. Tuning process of controller parameter can be performed using different method. But Genetic Algorithm (GA) ability tends to use it in controller parameter tuning process. In this paper firstly POD controller is used to power oscillation damping. But in this station, frequency oscillation dos not has proper damping situation. So FOD controller that is tuned using GA is using that cause to damp out frequency oscillation properly and power oscillation damping has suitable situation.

Keywords: Power oscillation damping (POD), frequency oscillation damping (FOD), Static synchronous series compensator (SSSC), Genetic Algorithm (GA).

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Authors: Chih-Chiang Hua, Yi-Hsiung Fang, Yuan-Jhen Siao

Abstract:

A bridgeless boost (BLB) power factor correction (PFC) rectifier with hold-up time extension circuit is proposed in this paper. A full bridge rectifier is widely used in the front end of the ac/dc converter. Since the shortcomings of the full bridge rectifier, the bridgeless rectifier is developed. A BLB rectifier topology is utilized with the hold-up time extension circuit. Unlike the traditional hold-up time extension circuit, the proposed extension scheme uses fewer active switches to achieve a longer hold-up time. Simulation results are presented to verify the converter performance.

Keywords: Bridgeless boost, boost converter, power factor correction, hold-up time.

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Authors: Yukinari Minagi , Akinori Kanasugi

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This paper describes about dynamic reconfiguration to miniaturize arithmetic circuits in general-purpose processor. Dynamic reconfiguration is a technique to realize required functions by changing hardware construction during operation. The proposed arithmetic circuit performs floating-point arithmetic which is frequently used in science and technology. The data format is floating-point based on IEEE754. The proposed circuit is designed using VHDL, and verified the correct operation by simulations and experiments.

Keywords: dynamic reconfiguration, floating-point arithmetic, double precision, FPGA

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Authors: M. Massour El Aoud, M. Franceschi, M. Maher

Abstract:

The approach proposed here is oriented in the direction of fuzzy system for the analysis and the synthesis of intelligent climate controllers, the simulation of the internal climate of the greenhouse is achieved by a linear model whose coefficients are obtained by identification. The use of fuzzy logic controllers for the regulation of climate variables represents a powerful way to minimize the energy cost. Strategies of reduction and optimization are adopted to facilitate the tuning and to reduce the complexity of the controller.

Keywords: Greenhouse, fuzzy logic, optimization, gradient descent.

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Authors: Hossein Sahoolizadeh, Alishir Moradi Kordalivand, Zargham Heidari

Abstract:

In first stage of each microwave receiver there is Low Noise Amplifier (LNA) circuit, and this stage has important rule in quality factor of the receiver. The design of a LNA in Radio Frequency (RF) circuit requires the trade-off many importance characteristics such as gain, Noise Figure (NF), stability, power consumption and complexity. This situation Forces desingners to make choices in the desing of RF circuits. In this paper the aim is to design and simulate a single stage LNA circuit with high gain and low noise using MESFET for frequency range of 5 GHz to 6 GHz. The desing simulation process is down using Advance Design System (ADS). A single stage LNA has successfully designed with 15.83 dB forward gain and 1.26 dB noise figure in frequency of 5.3 GHz. Also the designed LNA should be working stably In a frequency range of 5 GHz to 6 GHz.

Keywords: Advance Design System, Low Noise Amplifier, Radio Frequency, Noise Figure.

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Authors: AL.AL, M. B. I. Reaz, S. M. A. Motakabber, Mohd Alauddin Mohd Ali

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Nowadays it is a trend for electronic circuit designers to integrate all system components on a single-chip. This paper proposed the design of a single-chip proportional to absolute temperature (PTAT) sensor including a voltage reference circuit using CEDEC 0.18m CMOS Technology. It is a challenge to design asingle-chip wide range linear response temperature sensor for many applications. The channel widths between the compensation transistor and the reference transistor are critical to design the PTAT temperature sensor circuit. The designed temperature sensor shows excellent linearity between -100°C to 200° and the sensitivity is about 0.05mV/°C. The chip is designed to operate with a single voltage source of 1.6V.

Keywords: PTAT, single-chip circuit, linear temperature sensor, CMOS technology.

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Authors: A. Ahadpour Shal, A. Ghadimi, A. Azadbar

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In this paper a new method for increasing the speed of SAGCM-APD is proposed. Utilizing carrier rate equations in different regions of the structure, a circuit model for the structure is obtained. In this research, in addition to frequency response, the effect of added new charge layer on some transient parameters like slew-rate, rising and falling times have been considered. Finally, by trading-off among some physical parameters such as different layers widths and droppings, a noticeable decrease in breakdown voltage has been achieved. The results of simulation, illustrate some features of proposed structure improvement in comparison with conventional SAGCM-APD structures.

Keywords: Optical communication systems (OCS), Circuit modeling, breakdown voltage, SAGCM APD

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Authors: Talib Hashim Hasan

Abstract:

This paper describes simple implementation of homotopy (also called continuation) algorithm for determining the proper resistance of the resistor to dissipate energy at a specified rate of an electric circuit. Homotopy algorithm can be considered as a developing of the classical methods in numerical computing such as Newton-Raphson and fixed point methods. In homoptopy methods, an embedding parameter is used to control the convergence. The method purposed in this work utilizes a special homotopy called Newton homotopy. Numerical example solved in MATLAB is given to show the effectiveness of the purposed method

Keywords: electrical circuit homotopy, methods, MATLAB, Newton homotopy

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Authors: Zdeňka Dostálová, David Matoušek, Bohumil Brtnik

Abstract:

As there are also graph methods of circuit analysis in addition to algebraic methods, it is, in theory, clearly possible to carry out an analysis of a whole switched circuit in two-phase switching exclusively by the graph method as well. This article deals with two methods of full-graph solving of switched circuits: by transformation graphs and by two-graphs. It deals with the circuit switched capacitors and the switched current, too. All methods are presented in an equally detailed steps to be able to compare.

Keywords: Switched capacitors of two phases, switched currents of two phases, transformation graph, two-graph, Mason's formula, voltage transfer, summary graph.

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Authors: Naga Brahmendra Yadav Gorla, Dr. Lakshmi Narasamma N

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This paper proposes an active soft-switching circuit for bridge converters aiming to improve the power conversion efficiency. The proposed circuit achieves loss-less switching for both main and auxiliary switches without increasing the main switch current/voltage rating. A winding coupled to the primary of power transformer ensures ZCS for the auxiliary switches during their turn-off. A 350 W, 100 kHz phase shifted full bridge (PSFB) converter is built to validate the analysis and design. Theoretical loss calculations for proposed circuit is presented. The proposed circuit is compared with passive soft switched PSFB in terms of efficiency and loss in duty cycle.

Keywords: soft switching, passive soft switching, ZVS, ZCS, PSFB.

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Authors: Zoheir Tir, Rachid Abdessemed

Abstract:

This paper presents a new control scheme to control a brushless doubly fed induction generator (BDFIG) using back-to-back PWM converters for wind power generation. The proposed control scheme is a New Self-Tuning Fuzzy Proportional-Derivative Controller (NSTFPDC). The goal of BDFIG control is to achieve a similar dynamic performance to the doubly fed induction generator (DFIG), exploiting the well-known induction machine vector control philosophy. The performance of NSTFPDC controller has been investigated and compared with the two controllers, called Proportional–Integral (PI) and PD-like Fuzzy Logic controller (PD-like FLC) based BDFIG. The simulation results demonstrate the effectiveness and the robustness of the NSTFPDC controller.

Keywords: Brushless Doubly Fed Induction Generator (BDFIG), PI controller, PD-like Fuzzy Logic controller, New Self-Tuning Fuzzy Proportional-Derivative Controller (NSTFPDC), Scaling factor, back-to-back PWM converters, wind energy system.

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Authors: Seyed Ali Sedigh Zyabari, A. Zarifkar

Abstract:

Single photon detectors have been fabricated NbN nano wire. These detectors are fabricated from high quality, ultra high vacuum sputtered NbN thin films on a sapphire substrate. In this work a typical schematic of the nanowire Single Photon Detector structure and then driving and measurement electronic circuit are shown. The response of superconducting nanowire single photon detectors during a photo detection event, is modeled by a special electrical circuits (two circuit). Finally, current through the wire is calculated by solving equations of models.

Keywords: NbN, nanowire meander, superconducting single photon detector, kinetic inductance.

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Authors: C. Chanapromma, T. Worachak, P. Silapan

Abstract:

This paper presents positive and negative full-wave rectifier. The proposed structure is based on OTA using commercially available ICs (LT1228). The features of the proposed circuit are that: it can rectify and amplify voltage signal with controllable output magnitude via input bias current: the output voltage is free from temperature variation. The circuit description merely consists of 1 single ended and 3 fully differential OTAs. The performance of the proposed circuit are investigated though PSpice. They show that the proposed circuit can function as positive/negative full-wave rectifier, where the voltage input wide-dynamic range from -5V to 5V. Furthermore, the output voltage is slightly dependent on the temperature variations.

Keywords: Full-wave rectifier, Positive/negative, OTA, Electronically controllable, Wide-dynamic range

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Authors: Bharatendra Rai

Abstract:

Sequences of words in text data have long-term dependencies and are known to suffer from vanishing gradient problem when developing deep learning models. Although recurrent networks such as long short-term memory networks help overcome this problem, achieving high text classification performance is a challenging problem. Convolutional recurrent networks that combine advantages of long short-term memory networks and convolutional neural networks, can be useful for text classification performance improvements. However, arriving at suitable hyperparameter values for convolutional recurrent networks is still a challenging task where fitting of a model requires significant computing resources. This paper illustrates the advantages of using convolutional recurrent networks for text classification with the help of statistically planned computer experiments for hyperparameter tuning. 

Keywords: Convolutional recurrent networks, hyperparameter tuning, long short-term memory networks, Tukey honest significant differences

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Authors: Koson Pitaksuttayaprot, Winai Jaikla

Abstract:

The realization of current-mode quadrature oscillators using current controlled current conveyor transconductance amplifiers (CCCCTAs) and grounded capacitors is presented. The proposed oscillators can provide 2 sinusoidal output currents with 90º phase difference. It is enabled non-interactive dual-current control for both the condition of oscillation and the frequency of oscillation. High output impedances of the configurations enable the circuit to be cascaded without additional current buffers. The use of only grounded capacitors is ideal for integration. The circuit performances are depicted through PSpice simulations, they show good agreement to theoretical anticipation.

Keywords: Current-mode, Oscillator, Integrated circuit, CCCCTA.

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Authors: Wirat Sonchan, Pratoom Moungmee, Anek Sootmongkol

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This study aimed to examine the effects of a circuit training program on muscle strength, agility, anaerobic performance and cardiovascular endurance. The study involved 24 freshmen (age 18.87+0.68 yr.) male students of the Faculty of Sport Science, Burapha University. They sample study were randomly divided into two groups: Circuit Training group (CT; n=12) and a Control group (C; n=12). Baseline data on height, weight, muscle strength (hand grip dynamometer and leg strength dynamometer), agility (agility T-Test), and anaerobic performance (Running-based Anaerobic Sprint Test) and cardiovascular endurance (20 m Endurance Shuttle Run Test) were collected. The circuit training program included one circuit of eight stations of 30/60 seconds of work/rest interval with two cycles in Week 1-4, and 60/90 seconds of work/rest interval with three cycles in Week 5-8, performed three times per week. Data were analyzed using paired t-tests and independent sample t-test. Statistically significance level was set at 0.05. The results show that after 8 weeks of a training program, muscle strength, agility, anaerobic capacity and cardiovascular endurance increased significantly in the CT Group (p < 0.05), while significant increase was not observed in the C Group (p < 0.05). The results of this study suggest that the circuit training program improved muscle strength, agility, anaerobic capacity and cardiovascular endurance of the study subjects. This program may be used as a guideline for selecting a set of exercise to improve physical fitness.

Keywords: Cardiovascular endurance, circuit training, physical fitness, anaerobic performance.

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