Search results for: static power consumption

Authors: Md. Asif Jahangir Chowdhury, Md. Shahriar Rizwan, M. S. Islam

Abstract:

In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling. Recently, the power density has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. As a result static power consumption is becoming more dominant. This is a challenge for the circuit designers. However, the designers do have a few methods which they can use to reduce this static power consumption. But all of these methods have some drawbacks. In order to achieve lower static power consumption, one has to sacrifice design area and circuit performance. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using Variable Body Biasing technique without being penalized in area requirement and circuit performance.

Keywords: variable body biasing, state saving technique, stack effect, dual V-th, static power reduction.

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Authors: Jörg Lenhardt, Wolfram Schiffmann, Jörg Keller

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While the feature sizes of recent Complementary Metal Oxid Semiconductor (CMOS) devices decrease the influence of static power prevails their energy consumption. Thus, power savings that benefit from Dynamic Frequency and Voltage Scaling (DVFS) are diminishing and temporal shutdown of cores or other microchip components become more worthwhile. A consequence of powering off unused parts of a chip is that the relative difference between idle and fully loaded power consumption is increased. That means, future chips and whole server systems gain more power saving potential through power-aware load balancing, whereas in former times this power saving approach had only limited effect, and thus, was not widely adopted. While powering off complete servers was used to save energy, it will be superfluous in many cases when cores can be powered down. An important advantage that comes with that is a largely reduced time to respond to increased computational demand. We include the above developments in a server power model and quantify the advantage. Our conclusion is that strategies from datacenters when to power off server systems might be used in the future on core level, while load balancing mechanisms previously used at core level might be used in the future at server level.

Keywords: Power efficiency, static power consumption, dynamic power consumption, CMOS.

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Authors: Hong Li, Linfeng Li, Jianping Hu

Abstract:

With rapid technology scaling, the proportion of the static power consumption catches up with dynamic power consumption gradually. To decrease leakage consumption is becoming more and more important in low-power design. This paper presents a power-gating scheme for P-DTGAL (p-type dual transmission gate adiabatic logic) circuits to reduce leakage power dissipations under deep submicron process. The energy dissipations of P-DTGAL circuits with power-gating scheme are investigated in different processes, frequencies and active ratios. BSIM4 model is adopted to reflect the characteristics of the leakage currents. HSPICE simulations show that the leakage loss is greatly reduced by using the P-DTGAL with power-gating techniques.

Keywords: Leakage reduction, low power, deep submicronCMOS circuits, P-type adiabatic circuits.

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Authors: M. Aleshams, A. Shahsavandi

Abstract:

This paper describes a CMOS four-quadrant multiplier intended for use in the front-end receiver by utilizing the square-law characteristic of the MOS transistor in the saturation region. The circuit is based on 0.35 um CMOS technology simulated using HSPICE software. The mixer has a third-order inter the power consumption is 271uW from a single 1.2V power supply. One of the features of the proposed design is using two MOS transistors limitation to reduce the supply voltage, which leads to reduce the power consumption. This technique provides a GHz bandwidth response and low power consumption.

Keywords: RF-Mixer, Multiplier, cut-off frequency, power consumption

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Authors: Mostafa Alinezhad, Mehrdad Ahmadi Kamarposhti

Abstract:

According to the increasing utilization in power system, the transmission lines and power plants often operate in stability boundary and system probably lose its stable condition by over loading or occurring disturbance. According to the reasons that are mentioned, the prediction and recognition of voltage instability in power system has particular importance and it makes the network security stronger.This paper, by considering of power system contingencies based on the effects of them on Mega Watt Margin (MWM) and maximum loading point is focused in order to analyse the static voltage stability using continuation power flow method. The study has been carried out on IEEE 14-Bus Test System using Matlab and Psat softwares and results are presented.

Keywords: Contingency, Continuation Power Flow, Static Voltage Stability, Voltage Collapse.

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Authors: Yavar Safaei Mehrabani, Mehdi Hosseinzadeh

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As embedded and portable systems were emerged power consumption of circuits had been major challenge. On the other hand latency as determines frequency of circuits is also vital task. Therefore, trade off between both of them will be desirable. Modulo 2n+1 adders are important part of the residue number system (RNS) based arithmetic units with the interesting moduli set (2n-1,2n, 2n+1). In this manuscript we have introduced novel binary representation to the design of modulo 2n+1 adder. VLSI realization of proposed architecture under 180 nm full static CMOS technology reveals its superiority in terms of area, power consumption and power-delay product (PDP) against several peer existing structures.

Keywords: Computer arithmetic, modulo 2n+1 adders, Residue Number System (RNS), VLSI.

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Authors: V. Eramo, E. Miucci, A. Cianfrani, A. Germoni, M. Listanti

Abstract:

The power consumption of an Optical Packet Switch equipped with SOA technology based Spanke switching fabric is evaluated. Sophisticated analytical models are introduced to evaluate the power consumption versus the offered traffic, the main switch parameters, and the used device characteristics. The impact of Amplifier Spontaneous Emission (ASE) noise generated by a transmission system on the power consumption is investigated. As a matter of example for 32×32 switches supporting 64 wavelengths and offered traffic equal to 0,8, the average energy consumption per bit is 5, 07 · 10-2 nJ/bit and increases if ASE noise introduced by the transmission systems is increased.

Keywords: Spanke, Amplifier Spontaneous Emission Noise, Power Consumption, Optical Packet Switch.

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Authors: S. Nazhan, Hassan K. Al-Musawi, Khalid A. Humood

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This paper reports on an experimental investigation into the influence of current modulation on the properties of a vertical-cavity surface-emitting laser (VCSEL) with a direct square wave modulation. The optical output power response, as a function of the pumping current, modulation frequency, and amplitude, is measured for an 850 nm VCSEL. We demonstrate that modulation frequency and amplitude play important roles in reducing the VCSEL’s power consumption for optical generation. Indeed, even when the biasing current is below the static threshold, the VCSEL emits optical power under the square wave modulation. The power consumed by the device to generate light is significantly reduced to > 50%, which is below the threshold current, in response to both the modulation frequency and amplitude. An operating VCSEL device at low power is very desirable for less thermal effects, which are essential for a high-speed modulation bandwidth.

Keywords: VCSELs, optical power generation, power consumption, square wave modulation.

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Authors: Ankit Mitra

Abstract:

An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.

Keywords: CMOS, TSPC, MTCMOS, ALU, Clock gating, power gating, pipelining.

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Authors: N.Karpagam, D.Devaraj

Abstract:

Static Var Compensator (SVC) is a shunt type FACTS device which is used in power system primarily for the purpose of voltage and reactive power control. In this paper, a fuzzy logic based supplementary controller for Static Var Compensator (SVC) is developed which is used for damping the rotor angle oscillations and to improve the transient stability of the power system. Generator speed and the electrical power are chosen as input signals for the Fuzzy Logic Controller (FLC). The effectiveness and feasibility of the proposed control is demonstrated with Single Machine Infinite Bus (SMIB) system and multimachine system (WSCC System) which show improvement over the use of a fixed parameter controller.

Keywords: FLC, SVC, Transient stability, SMIB, PIDcontroller.

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Authors: Joon-young Jung, Dong-oh Kang, Chang-seok Bae

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Power consumption is rapidly increased in data centers because the number of data center is increased and more the scale of data center become larger. Therefore, it is one of key research items to reduce power consumption in data center. The peak power of a typical server is around 250 watts. When a server is idle, it continues to use around 60% of the power consumed when in use, though vendors are putting effort into reducing this “idle" power load. Servers tend to work at only around a 5% to 20% utilization rate, partly because of response time concerns. An average of 10% of servers in their data centers was unused. In those reason, we propose dynamic power management system to reduce power consumption in green data center. Experiment result shows that about 55% power consumption is reduced at idle time.

Keywords: Data Center, Green IT, Management Server, Power Saving.

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Authors: Baghdasaryan Marinka

Abstract:

Monitoring the distribution of electric power consumption in the technological process of ore grinding is conducted. As a result, the impacts of the mill filling rate, the productivity of the ore supply, the volumetric density of the grinding balls, the specific density of the ground ore, and the relative speed of the mill rotation on the specific consumption of electric power have been studied. The power and technological factors affecting the reactive power generated by the synchronous motors, operating within the technological scheme are studied. A block diagram for evaluating the power consumption modes of the technological process is presented, which includes the analysis of the technological scheme, the determination of the place and volumetric density of the ore-grinding mill, the evaluation of the technological and power factors affecting the energy saving process, as well as the assessment of the electric power standards.

Keywords: Electric power standard, factor, ore grinding, power consumption, reactive power, technological.

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Authors: Amir Sepasi Zahmati, Bahman Abolhassani, Ali Asghar Beheshti Shirazi, Ali Shojaee Bakhtiari

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A wireless sensor network with a large number of tiny sensor nodes can be used as an effective tool for gathering data in various situations. One of the major issues in wireless sensor networks is developing an energy-efficient routing protocol which has a significant impact on the overall lifetime of the sensor network. In this paper, we propose a novel hierarchical with static clustering routing protocol called Energy-Efficient Protocol with Static Clustering (EEPSC). EEPSC, partitions the network into static clusters, eliminates the overhead of dynamic clustering and utilizes temporary-cluster-heads to distribute the energy load among high-power sensor nodes; thus extends network lifetime. We have conducted simulation-based evaluations to compare the performance of EEPSC against Low-Energy Adaptive Clustering Hierarchy (LEACH). Our experiment results show that EEPSC outperforms LEACH in terms of network lifetime and power consumption minimization.

Keywords: Clustering methods, energy efficiency, routingprotocol, wireless sensor networks.

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Authors: Mehrdad Ahmadi Kamarposhti, Mostafa Alinezhad

Abstract:

One of the major causes of voltage instability is the reactive power limit of the system. Improving the system's reactive power handling capacity via Flexible AC transmission System (FACTS) devices is a remedy for prevention of voltage instability and hence voltage collapse. In this paper, the effects of SVC and STATCOM in Static Voltage Stability Margin Enhancement will be studied. AC and DC representations of SVC and STATCOM are used in the continuation power flow process in static voltage stability study. The IEEE-14 bus system is simulated to test the increasing loadability. It is found that these controllers significantly increase the loadability margin of power systems.

Keywords: SVC, STATCOM, Voltage Collapse, Maximum Loading Point.

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Authors: M. Yousefi, N. Nasirzadeh

Abstract:

In this paper, dynamic comparator structure employing two methods for power consumption reduction with applications in low-power high-speed analog-to-digital converters have been presented. The proposed comparator has low consumption thanks to power reduction methods. They have the ability for offset adjustment. The comparator consumes 14.3 μW at 100 MHz which is equal to 11.8 fJ. The comparator has been designed and simulated in 180 nm CMOS. Layouts occupy 210 μm².

Keywords: Comparator, low, power, efficiency.

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Authors: Pardeep Singh, Sanjay Sharma, Parvinder S. Sandhu

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This work aims to reduce the read power consumption as well as to enhance the stability of the SRAM cell during the read operation. A new 10-transisor cell is proposed with a new read scheme to minimize the power consumption within the memory core. It has separate read and write ports, thus cell read stability is significantly improved. A 16Kb SRAM macro operating at 1V supply voltage is demonstrated in 65 nm CMOS process. Its read power consumption is reduced to 24% of the conventional design. The new cell also has lower leakage current due to its special bit-line pre-charge scheme. As a result, it is suitable for low-power mobile applications where power supply is restricted by the battery.

Keywords: A 16Kb 10T-SRAM, 4x Read-Power Reduction

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Authors: Vasundara Patel K. S., Harsha N. Bhushan, Kiran G. Gadag, Nischal Prasad B. N., Mohmmed Haroon

Abstract:

The most widely used semiconductor memory types are the Dynamic Random Access Memory (DRAM) and Static Random Access memory (SRAM). Competition among memory manufacturers drives the need to decrease power consumption and reduce the probability of read failure. A technology that is relatively new and has not been explored is the FinFET technology. In this paper, a single cell Schmitt Trigger Based Static RAM using FinFET technology is proposed and analyzed. The accuracy of the result is validated by means of HSPICE simulations with 32nm FinFET technology and the results are then compared with 6T SRAM using the same technology.

Keywords: Schmitt trigger based SRAM, FinFET, and Static Noise Margin.

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Authors: Tien-Shun Chan, Yung-Chung Chang, Cheng-Yu Chu, Wen-Hui Chen, Yuan-Lin Chen, Shun-Chong Wang, Chang-Chun Wang

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98% of the energy needed in Taiwan has been imported. The prices of petroleum and electricity have been increasing. In addition, facility capacity, amount of electricity generation, amount of electricity consumption and number of Taiwan Power Company customers have continued to increase. For these reasons energy conservation has become an important topic. In the past linear regression was used to establish the power consumption models for chillers. In this study, grey prediction is used to evaluate the power consumption of a chiller so as to lower the total power consumption at peak-load (so that the relevant power providers do not need to keep on increasing their power generation capacity and facility capacity). In grey prediction, only several numerical values (at least four numerical values) are needed to establish the power consumption models for chillers. If PLR, the temperatures of supply chilled-water and return chilled-water, and the temperatures of supply cooling-water and return cooling-water are taken into consideration, quite accurate results (with the accuracy close to 99% for short-term predictions) may be obtained. Through such methods, we can predict whether the power consumption at peak-load will exceed the contract power capacity signed by the corresponding entity and Taiwan Power Company. If the power consumption at peak-load exceeds the power demand, the temperature of the supply chilled-water may be adjusted so as to reduce the PLR and hence lower the power consumption.

Keywords: Gery system theory, grey prediction, chller.

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Authors: Shuen-Tai Wang, Chin-Hung Li, Ying-Chuan Chen

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In recent years there has been renewal of interest in the relation between Green IT and Cloud Computing. The growing use of computers in cloud platform has caused marked energy consumption, putting negative pressure on electricity cost of cloud data center. This paper proposes an effective mechanism to reduce energy utilization in cloud computing environments. We present initial work on the integration of resource and power management that aims at reducing power consumption. Our mechanism relies on recalling virtualization services dynamically according to user-s virtualization request and temporarily shutting down the physical machines after finish in order to conserve energy. Given the estimated energy consumption, this proposed effort has the potential to positively impact power consumption. The results from the experiment concluded that energy indeed can be saved by powering off the idling physical machines in cloud platforms.

Keywords: Green IT, Cloud Computing, virtualization, power consumption.

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Authors: Ali Reza Rajabi, Shahab Rashnoei, Mojtaba Hakimzadeh, Amir Habibi

Abstract:

At any point of time, a power system operating condition should be stable, meeting various operational criteria and it should also be secure in the event of any credible contingency. Present day power systems are being operated closer to their stability limits due to economic and environmental constraints. Maintaining a stable and secure operation of a power system is therefore a very important and challenging issue. Voltage instability has been given much attention by power system researchers and planners in recent years, and is being regarded as one of the major sources of power system insecurity. Voltage instability phenomena are the ones in which the receiving end voltage decreases well below its normal value and does not come back even after setting restoring mechanisms such as VAR compensators, or continues to oscillate for lack of damping against the disturbances. Reactive power limit of power system is one of the major causes of voltage instability. This paper investigates the effects of coordinated series capacitors (SC) with static VAR compensators (SVC) on steady-state voltage stability of a power system. Also, the influence of the presence of series capacitor on static VAR compensator controller parameters and ratings required to stabilize load voltages at certain values are highlighted.

Keywords: Static VAR Compensator (SVC), Series Capacitor (SC), voltage stability, reactive power.

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Authors: T. Vigneswaran, B. Mukundhan, P. Subbarami Reddy

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Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In addition to its main task, which is adding two numbers, it participates in many other useful operations such as subtraction, multiplication, division,, address calculation,..etc. In most of these systems the adder lies in the critical path that determines the overall speed of the system. So enhancing the performance of the 1-bit full adder cell (the building block of the adder) is a significant goal.Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a new low power adder cell by sacrificing the MOS Transistor count that reduces the serious threshold loss problem, considerably increases the speed and decreases the power when compared to the static energy recovery full (SERF) adder. So a new improved 14T CMOS l-bit full adder cell is presented in this paper. Results show 50% improvement in threshold loss problem, 45% improvement in speed and considerable power consumption over the SERF adder and other different types of adders with comparable performance.

Keywords: Arithmetic circuit, full adder, multiplier, low power, very Large-scale integration (VLSI).

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Authors: Deogratius Musiige, François Anton, Vital Yatskevich, Laulagnet Vincent, Darka Mioc, Nguyen Pierre

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This paper presents a methodology towards the emulation of the electrical power consumption of the RF device during the cellular phone/handset transmission mode using the LTE technology. The emulation methodology takes the physical environmental variables and the logical interface between the baseband and the RF system as inputs to compute the emulated power dissipation of the RF device. The emulated power, in between the measured points corresponding to the discrete values of the logical interface parameters is computed as a polynomial interpolation using polynomial basis functions. The evaluation of polynomial and spline curve fitting models showed a respective divergence (test error) of 8% and 0.02% from the physically measured power consumption. The precisions of the instruments used for the physical measurements have been modeled as intervals. We have been able to model the power consumption of the RF device operating at 5MHz using homotopy between 2 continuous power consumptions of the RF device operating at the bandwidths 3MHz and 10MHz.

Keywords: Radio frequency, high power amplifier, baseband, LTE, power, emulation, homotopy, interval analysis, Tx power, register-transfer level.

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Authors: Darshana Thomas, Edward Wilkie, James Irvine

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The Internet of things (IoT) is currently a highly researched topic, especially within the context of the smart home. These are small sensors that are capable of gathering data and transmitting it to a server. The majority of smart home products use protocols such as ZigBee or Bluetooth Low Energy (BLE). As these small sensors are increasing in number, the need to implement these with much more capable and ubiquitous transmission technology is necessary. The high power consumption is the reason that holds these small sensors back from using other protocols such as the most ubiquitous form of communication, WiFi. Comparing the power consumption of existing transmission technologies to one with WiFi inbuilt, would provide a better understanding for choosing between these technologies. We have developed a small IoT device with WiFi capability and proven that it is much more efficient than the first protocol, 433 MHz. We extend our work in this paper and compare WiFi power consumption with the other most widely used protocol BLE. The experimental results in this paper would conclude whether the developed prototype is capable in terms of power consumption to replace the existing protocol BLE with WiFi.

Keywords: Bluetooth, internet of things, power consumption, WiFi.

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Authors: N. Mahendran, R. Madhuranthi

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Wireless sensor networks (WSNs), are constantly in demand to process information more rapidly with less energy and area cost. Presently, processor based solutions have difficult to achieve high processing speed with low-power consumption. This paper presents a simple and accurate data processing scheme for low power wireless sensor node, based on reduced number of processing element (PE). The presented model provides a simple recursive structure (SRS) to process the sampled data in the wireless sensor environment and to reduce the power consumption in wireless sensor node. Based on this model, to process the incoming samples and produce a smaller amount of data sufficient to reconstruct the original signal. The ModelSim simulator used to simulate SRS structure. Functional simulation is carried out for the validation of the presented architecture. Xilinx Power Estimator (XPE) tool is used to measure the power consumption. The experimental results show the average power consumption of 91 mW; this is 42% improvement compared to the folded tree architecture.

Keywords: Power consumption, energy efficiency, low power WSN node, recursive structure, sleep/wake scheduling.

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Authors: M.Hosseinghadiry, H. Mohammadi, M.Nadisenejani

Abstract:

with increasing circuits- complexity and demand to use portable devices, power consumption is one of the most important parameters these days. Full adders are the basic block of many circuits. Therefore reducing power consumption in full adders is very important in low power circuits. One of the most powerconsuming modules in full adders is XOR/XNOR circuit. This paper presents two new full adders based on two new logic approaches. The proposed logic approaches use one XOR or XNOR gate to implement a full adder cell. Therefore, delay and power will be decreased. Using two new approaches and two XOR and XNOR gates, two new full adders have been implemented in this paper. Simulations are carried out by HSPICE in 0.18μm bulk technology with 1.8V supply voltage. The results show that the ten-transistors proposed full adder has 12% less power consumption and is 5% faster in comparison to MB12T full adder. 9T is more efficient in area and is 24% better than similar 10T full adder in term of power consumption. The main drawback of the proposed circuits is output threshold loss problem.

Keywords: Full adder, XNOR, Low power, High performance, Very Large Scale Integrated Circuit.

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Authors: M. Sedighizadeh, A. Rezazadeh

Abstract:

A method has been developed for preparing load models for power flow and stability. The load modeling (LOADMOD) computer software transforms data on load class mix, composition, and characteristics into the from required for commonly–used power flow and transient stability simulation programs. Typical default data have been developed for load composition and characteristics. This paper defines LOADMOD software and describes the dynamic and static load modeling techniques used in this software and results of initial testing for BAKHTAR power system.

Keywords: Load Modelling, Static, Power Flow.

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Authors: R. Kamalakannan, N. Ravi Kumar

Abstract:

The global energy consumption is increasing persistently and need for distributed power generation through renewable energy is essential. To meet the power requirements for consumers without any voltage fluctuations and losses, modeling and design of multilevel inverter with Flexible AC Transmission System (FACTS) capability is presented. The presented inverter is provided with 13-level cascaded H-bridge topology of Insulated Gate Bipolar Transistor (IGBTs) connected along with inbuilt Distributed Static Synchronous Compensators (DSTATCOM). The DSTATCOM device provides control of power factor stability at local feeder lines and the inverter eliminates Total Harmonic Distortion (THD). The 13-level inverter utilizes 52 switches of each H-bridge is fed with single DC sources separately and the Pulse Width Modulation (PWM) technique is used for switching IGBTs. The control strategy implemented for inverter transmits active power to grid as well as it maintains power factor to be stable with achievement of steady state power transmission. Significant outcome of this project is improvement of output voltage quality with steady state power transmission with low THD. Simulation of inverter with DSTATCOM is performed using MATLAB/Simulink environment. The scaled prototype model of proposed inverter is built and its results were validated with simulated results.

Keywords: FACTS devices, distributed-Static synchronous compensators, DSTATCOM, total harmonics elimination, modular multilevel converter.

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Authors: Ilya Kavalchuk, Hayrettin Arisoy, Alex Stojcevski, Aman Maun Than Oo

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Electric vehicles are one of the most complicated electric devices to simulate due to the significant number of different processes involved in electrical structure of it. There are concurrent processes of energy consumption and generation with different onboard systems, which make simulation tasks more complicated to perform. More accurate simulation on energy consumption can provide a better understanding of all energy management for electric transport. As a result of all those processes, electric transport can allow for a more sustainable future and become more convenient in relation to the distance range and recharging time. This paper discusses the problems of energy consumption simulations for electric vehicles using different software packages to provide ideas on how to make this process more precise, which can help engineers create better energy management strategies for electric vehicles.

Keywords: Electric Vehicles, EV, Power Consumption, Power Management, Simulation.

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Authors: S. Padma, Dr. R. Lakshmipathi, K. Ramash Kumar, P. Nandagopal

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The power system network is becoming more complex nowadays and it is very difficult to maintain the stability of the system. Today-s enhancement of technology makes it possible to include new energy storage devices in the electric power system. In addition, with the aid of power electronic devices, it is possible to independently exchange active and reactive power flow with the utility grid. The main purpose of this paper proposes a Proportional – Integral (PI) control based 48 – pulse Inverter based Static Synchronous Series Compensator (SSSC) with and without Superconducting Magnetic Energy Storage (SMES) used for enhancing the transient stability and regulating power flow in automatic mode. Using a test power system through the dynamic simulation in Matlab/Simulink platform validates the performance of the proposed SSSC with and without SMES system.

Keywords: Flexible AC transmission system (FACTS), PIControl, Superconducting Magnetic Energy Storage (SMES), Static Synchronous Series Compensator (SSSC).

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Authors: Tatyana Aleksandrovna Barbasova, Lev Sergeevich Kazarinov, Olga Valerevna Kolesnikova, Aleksandra Aleksandrovna Filimonova

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We regard forecasting of energy consumption by private production areas of a large industrial facility as well as by the facility itself. As for production areas, the forecast is made based on empirical dependencies of the specific energy consumption and the production output. As for the facility itself, implementation of the task to minimize the energy consumption forecasting error is based on adjustment of the facility’s actual energy consumption values evaluated with the metering device and the total design energy consumption of separate production areas of the facility. The suggested procedure of optimal energy consumption was tested based on the actual data of core product output and energy consumption by a group of workshops and power plants of the large iron and steel facility. Test results show that implementation of this procedure gives the mean accuracy of energy consumption forecasting for winter 2014 of 0.11% for the group of workshops and 0.137% for the power plants.

Keywords: Energy consumption, energy consumption forecasting error, energy efficiency, forecasting accuracy, forecasting.

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