Search results for: multicycle%20fatigue

2 Structure-Phase States of Al-Si Alloy after Electron-Beam Treatment and Multicycle Fatigue

Authors: Krestina V. Alsaraeva, Victor E. Gromov, Sergey V. Konovalov, Anna A. Atroshkina

Abstract:

Processing of Al-19.4Si alloy by high intensive electron beam has been carried out and multiple increases in fatigue life of the material have been revealed. Investigations of structure and surface modified layer destruction of Al-19.4Si alloy subjected to multicycle fatigue tests to fracture have been carried out by methods of scanning electron microscopy. The factors responsible for the increase of fatigue life of Al-19.4Si alloy have been revealed and analyzed.

Keywords: Al-19.4Si alloy, high intensive electron beam, multicycle fatigue, structure.

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1 A High Level Implementation of a High Performance Data Transfer Interface for NoC

Authors: Mansi Jhamb, R. K. Sharma, A. K. Gupta

Abstract:

The distribution of a single global clock across a chip has become the major design bottleneck for high performance VLSI systems owing to the power dissipation, process variability and multicycle cross-chip signaling. A Network-on-Chip (NoC) architecture partitioned into several synchronous blocks has become a promising approach for attaining fine-grain power management at the system level. In a NoC architecture the communication between the blocks is handled asynchronously. To interface these blocks on a chip operating at different frequencies, an asynchronous FIFO interface is inevitable. However, these asynchronous FIFOs are not required if adjacent blocks belong to the same clock domain. In this paper, we have designed and analyzed a 16-bit asynchronous micropipelined FIFO of depth four, with the awareness of place and route on an FPGA device. We have used a commercially available Spartan 3 device and designed a high speed implementation of the asynchronous 4-phase micropipeline. The asynchronous FIFO implemented on the FPGA device shows 76 Mb/s throughput and a handshake cycle of 109 ns for write and 101.3 ns for read at the simulation under the worst case operating conditions (voltage = 0.95V) on a working chip at the room temperature.

Keywords: Asynchronous, FIFO, FPGA, GALS, Network-on- Chip (NoC), VHDL.

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