Search results for: full digital simulation.

Authors: Bao Jinsong, Hu Xiaofeng, Wang Wei, Yu Dili, Jin Ye

Abstract:

The paper researched and presented a virtual simulation system based on a full-digital lunar terrain, integrated with kinematics and dynamics module as well as autonomous navigation simulation module. The system simulation models are established. Enabling technologies such as digital lunar surface module, kinematics and dynamics simulation, Autonomous navigation are investigated. A prototype system for lunar rover locomotion simulation is developed based on these technologies. Autonomous navigation is a key echnology in lunar rover system, but rarely involved in virtual simulation system. An autonomous navigation simulation module have been integrated in this prototype system, which was proved by the simulation results that the synthetic simulation and visualizing analysis system are established in the system, and the system can provide efficient support for research on the autonomous navigation of lunar rover.

Keywords: Lunar rover, virtual simulation, autonomous navigation, full-digital lunar terrain

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Authors: Ashly Joseph

Abstract:

In the era of digital transformation, full-stack observability has emerged as a crucial aspect of administering modern application stacks. This research paper presents the concept of full-stack observability, its significance in the context of contemporary application stacks, and the challenges posed by swiftly evolving digital environments. In addition, it describes how full-stack observability intends to provide complete visibility and actionable insights by correlating telemetry across multiple domains.

Keywords: Actionable insights, digital transformation, full-stack observability, performance metrics.

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Authors: Bin Wang, Hengyu Ji, Zhifeng Ye

Abstract:

Fuel Metering Unit (FMU) in fuel system of an aeroengine sometimes has direct influence on the engine performance, which is neglected for the sake of easy access to mathematical model of the engine in most cases. In order to verify the influence of FMU on an engine model, this paper presents a co-simulation of a stepping motor driven FMU (digital FMU) in a turboshaft aeroengine, using AMESim and MATLAB to obtain the steady and dynamic characteristics of the FMU. For this method, mechanical and hydraulic section of the unit is modeled through AMESim, while the stepping motor is mathematically modeled through MATLAB/Simulink. Combining these two sub-models yields an AMESim/MATLAB co-model of the FMU. A simplified component level model for the turboshaft engine is established and connected with the FMU model. Simulation results on the full model show that the engine model considering FMU characteristics describes the engine more precisely especially in its transition state. An FMU dynamics will cut down the rotation speed of the high pressure shaft and the inlet pressure of the combustor during the step response. The work in this paper reveals the impact of FMU on engine operation characteristics and provides a reference to an engine model for ground tests.

Keywords: Fuel metering unit, stepping motor, AMESim/MATLAB, full digital simulation.

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Authors: Benmabrouk. Zaineb, Ben Hamed. Mouna, Lassad. Sbita

Abstract:

This article deals to describe the simulation investigation of the digital phase locked loop implemented in software (SDPLL). SDPLL has been developed for speed drives of an induction motor in scalar strategy. A drive was implemented and simulation results are presented to verify the robustness against motor parameter variation and regulation speed.

Keywords: Induction motor, Software Digital Phase LockedLoop, Speed control, Simulation.

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Authors: Fasil Endalamaw

Abstract:

Digital magnitude comparators based on Gate Diffusion Input (GDI) implementation technique are high speed and area-efficient, and they consume less power as compared to other implementation techniques. However, they are less efficient for some logic gates and have no full voltage swing. In this paper, we made a performance comparison between the GDI implementation technique and other implementation methods, such as Static CMOS, Pass Transistor Logic (PTL), and Transmission Gate (TG) in 90 nm, 120 nm, and 180 nm CMOS technologies using BSIM4 MOS model. We proposed a methodology (hybrid implementation) of implementing digital magnitude comparators which significantly improved the power, speed, area, and voltage swing requirements. Simulation results revealed that the hybrid implementation of digital magnitude comparators show a 10.84% (power dissipation), 41.6% (propagation delay), 47.95% (power-delay product (PDP)) improvement compared to the usual GDI implementation method. We used Microwind & Dsch Version 3.5 as well as the Tanner EDA 16.0 tools for simulation purposes.

Keywords: Efficient, gate diffusion input, high speed, low power, CMOS.

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Authors: Iyad F. Jafar, Sandra J. Alrawashdeh, Ban K. Alhamayel

Abstract:

High level synthesis (HLS) is a process which generates register-transfer level design for digital systems from behavioral description. There are many HLS algorithms and commercial tools. However, most of these algorithms consider a behavioral description for the system when a single token is presented to the system. This approach does not exploit extra hardware efficiently, especially in the design of digital filters where common operations may exist between successive tokens. In this paper, we modify the behavioral description to process multiple tokens in parallel. However, this approach is unlike the full processing that requires full hardware replication. It exploits the presence of common operations between successive tokens. The performance of the proposed approach is better than sequential processing and approaches that of full parallel processing as the hardware resources are increased.

Keywords: Digital filters, High level synthesis, Sub-token forwarding

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Authors: Wenyu Song, Bingxi Li, Zhongbin Fu, Baocheng Jiang

Abstract:

Full - Scale Accelerated Loading System, one part of “the Eleventh - Five - Year National Grand Technology Infrastructure Program" is a facility to evaluate the performance and service life of different kinds of pavements subjected to traffic loading under full - controlled environment. While simulating the environments of frigid zone and permafrost zone, the accurate control of air temperature, road temperature and roadbed temperature are the key points and also aporias for the designment. In this paper, numerical simulations are used to determine the design parameters of the frozen soil simulation system. At first, a brief introduction of the Full - Scale Accelerate Loading System was given. Then, the temperature control method of frozen soil simulation system was proposed. Finally, by using finite element simulations, the optimal design of frozen soil simulation system was obtained. This proposed design, which was obtained by finite element simulations, provided significant referents to the ultimate design of the environment simulation system.

Keywords: China, finite element simulation, frozen soilsimulation system, preliminary design.

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Authors: J. Mbihi

Abstract:

This paper presents a dynamic architecture of digital duty-cycle modulation control drivers. Compared to most oversampling digital modulation schemes encountered in industrial electronics, its novelty is founded on a number of relevant merits including; embedded positive and negative feedback loops, internal modulation clock, structural simplicity, elementary building operators, no explicit need of samples of the nonlinear duty-cycle function when computing the switching modulated signal, and minimum number of design parameters. A prototyping digital control driver is synthesized and well tested within MATLAB/Simulink workspace. Then, the virtual simulation results and performance obtained under a sample of relevant instrumentation and control systems are presented, in order to show the feasibility, the reliability, and the versatility of target applications, of the proposed class of low cost and high quality digital control drivers in industrial electronics.

Keywords: Dynamic architecture, virtual simulation, duty-cycle modulation, digital control drivers, industrial electronics.

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Authors: Gang Li, Ghulam Mubashar Hassan, Arcady Dyskin, Cara MacNish

Abstract:

Digital image correlation (DIC) is a contactless fullfield displacement and strain reconstruction technique commonly used in the field of experimental mechanics. Comparing with physical measuring devices, such as strain gauges, which only provide very restricted coverage and are expensive to deploy widely, the DIC technique provides the result with full-field coverage and relative high accuracy using an inexpensive and simple experimental setup. It is very important to study the natural patterns effect on the DIC technique because the preparation of the artificial patterns is time consuming and hectic process. The objective of this research is to study the effect of using images having natural pattern on the performance of DIC. A systematical simulation method is used to build simulated deformed images used in DIC. A parameter (subset size) used in DIC can have an effect on the processing and accuracy of DIC and even cause DIC to failure. Regarding to the picture parameters (correlation coefficient), the higher similarity of two subset can lead the DIC process to fail and make the result more inaccurate. The pictures with good and bad quality for DIC methods have been presented and more importantly, it is a systematic way to evaluate the quality of the picture with natural patterns before they install the measurement devices.

Keywords: Digital image correlation (DIC), Deformation simulation, Natural pattern, Subset size.

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Authors: N. Webb, A. Buchanan

Abstract:

Digital and virtual heritage is often associated with the recreation of lost artefacts and architecture; however, we can also investigate works that were not completed, using digital tools and techniques. Here we explore physical evidence of a fourteenth-century Gothic vault located in the north transept of St Mary’s church in Nantwich, Cheshire, using existing springer stones that are built into the walls as a starting point. Digital surveying tools are used to document the architecture, followed by an analysis process to hypothesise and simulate possible design solutions, had the vault been completed. A number of options, both two-dimensionally and three-dimensionally, are discussed based on comparison with examples of other contemporary vaults, thus adding another specimen to the corpus of vault designs. Dissemination methods such as digital models and 3D prints are also explored as possible resources for demonstrating what the finished vault might have looked like for heritage interpretation and other purposes.

Keywords: Digital simulation, heritage interpretation, medieval vaults, virtual heritage, 3D scanning.

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Authors: Shashank Gautam

Abstract:

This paper proposes techniques like MT CMOS, POWER GATING, DUAL STACK, GALEOR and LECTOR to reduce the leakage power. A Full Adder has been designed using these techniques and power dissipation is calculated and is compared with general CMOS logic of Full Adder. Simulation results show the validity of the proposed techniques is effective to save power dissipation and to increase the speed of operation of the circuits to a large extent.

Keywords: Low Power, MT CMOS, Galeor, Lector, Power Gating, Dual Stack, Full Adder.

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Authors: Ankit Mitra

Abstract:

An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.

Keywords: CMOS, TSPC, MTCMOS, ALU, Clock gating, power gating, pipelining.

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Authors: Zainab M. Musa, Nordin M. A. Rahman, Julaily A. Jusoh

Abstract:

Digital reference service is when a traditional library reference service is provided electronically. In most cases users do not get full satisfaction from using digital reference service due to variety of reasons. This paper discusses the formal specification of web services applications for digital reference services (WSDRS). WSDRS is an informal model that claims to reduce the problems of digital reference services in libraries. It uses web services technology to provide efficient digital way of satisfying users’ need in the reference section of libraries. Informal model is in natural language which is inconsistent and ambiguous that may cause difficulties to the developers of the system. In order to solve this problem we decided to convert the informal specifications into formal specifications. This is supposed to reduce the overall development time and cost. We use Z language to develop the formal model and verify it with Z/EVES theorem prover tool.

Keywords: Formal, specifications, web services, digital reference services.

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Authors: A. Diet, M. Villegas, G. Baudoin

Abstract:

This work concerns the measurements of a Bulk Acoustic Waves (BAW) emission filter S parameters and compare with prototypes simulated types. Thanks to HP-ADS, a co-simulation of filters- characteristics in a digital radio-communication chain is performed. Four cases of modulation schemes are studied in order to illustrate the impact of the spectral occupation of the modulated signal. Results of simulations and co-simulation are given in terms of Error Vector Measurements to be useful for a general sensibility analysis of 4th/3rd Generation (G.) emitters (wideband QAM and OFDM signals)

Keywords: RF architectures, BAW filters.

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Authors: Riki Mukhaiyar

Abstract:

The integration between technology of remote sensing, information from the data of digital image, and modeling technology for the simulation of water quality will provide easiness during the observation on the quality of water changes on the river surface. For example, Ciliwung River which is contaminated with non-point source pollutant from household wastes, particularly on its downstream. This fact informed that the quality of water in this river is getting worse. The land use for settlements and housing ranges between 62.84% - 81.26% on the downstream of Ciliwung River, give a significant picture in seeing factors that affected the water quality of Ciliwung River.

Keywords: Digital Image, Digitize, Landuse, Non-Point SourcePollutant, Qual2e Simulation

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Authors: Driss Kettani

Abstract:

In this paper, we shed light on the “Digital Divide 2.0,” which we see as COVID-19’s version of the digital divide. We believe that “fighting” against digital divide 2.0 necessitates for a country to be seriously advanced in the global digital transformation that is, naturally, a complex, delicate, costly and long-term process. We build an argument supporting our assumption and, from there, we present the foundations of a computational framework to guide and streamline digital transformation at all levels.

Keywords: Digital divide 2.0, digital transformation, ICTs for development, computational outcomes assessment.

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Authors: S. Saisundar, Shan Jiang, Kevin T. C. Chai, David Nuttman, Minkyu Je

Abstract:

Keywords: Analog to digital converter, cyclic, gain-boosting, pipelined.

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Authors: P. Bárta

Abstract:

Increasing demand on the performance of Subsea Production Systems (SPS) suggests a need for more detailed investigation of fluid behavior taking place in subsea equipment. Complete CFD cool down analyses of subsea equipment are very time demanding. The objective of this paper is to investigate a Locked CFD approach, which enables significant reduction of the computational time and at the same time maintains sufficient accuracy during thermal cool down simulations. The result comparison of a dead leg simulation using the Full CFD and the three LCFD-methods confirms the validity of the locked flow field assumption for the selected case. For the tested case the LCFD simulation speed up by factor of 200 results in the absolute thermal error of 0.5 °C (3% relative error), speed up by factor of 10 keeps the LCFD results within 0.1 °C (0.5 % relative error) comparing to the Full CFD.

Keywords: CFD, Locked Flow Field, Speed up of CFD simulation time, Subsea

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Authors: Santanu Santra, Utpal Roy

Abstract:

The most important mathematical operation for any computing system is addition. An efficient adder can be of greater assistance in designing of any arithmetic circuits. Quantum-dot Cellular Automata (QCA) is a promising nanotechnology to create electronic circuits for computing devices and suitable candidate for next generation of computing systems. The article presents a modest approach to implement a novel XOR gate. The gate is simple in structure and powerful in terms of implementing digital circuits. By applying the XOR gate, the hardware requirement for a QCA circuit can be decrease and circuits can be simpler in level, clock phase and cell count. In order to verify the functionality of the proposed device some implementation of Half Adder (HA) and Full Adder (FA) is checked by means of computer simulations using QCA-Designer tool. Simulation results and physical relations confirm its usefulness in implementing every digital circuit.

Keywords: Clock, Computing system, Majority gate, QCA, QCA Designer.

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Authors: T. Vigneswaran, B. Mukundhan, P. Subbarami Reddy

Abstract:

Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In addition to its main task, which is adding two numbers, it participates in many other useful operations such as subtraction, multiplication, division,, address calculation,..etc. In most of these systems the adder lies in the critical path that determines the overall speed of the system. So enhancing the performance of the 1-bit full adder cell (the building block of the adder) is a significant goal.Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a new low power adder cell by sacrificing the MOS Transistor count that reduces the serious threshold loss problem, considerably increases the speed and decreases the power when compared to the static energy recovery full (SERF) adder. So a new improved 14T CMOS l-bit full adder cell is presented in this paper. Results show 50% improvement in threshold loss problem, 45% improvement in speed and considerable power consumption over the SERF adder and other different types of adders with comparable performance.

Keywords: Arithmetic circuit, full adder, multiplier, low power, very Large-scale integration (VLSI).

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Authors: Kyunghoon Kim, Sungjoon Shim, Jun Tae Kim, Jong Tae Kim

Abstract:

In a wireless communication system, a predistorter(PD) is often employed to alleviate nonlinear distortions due to operating a power amplifier near saturation, thereby improving the system performance and reducing the interference to adjacent channels. This paper presents a new adaptive polynomial digital predistorter(DPD). The proposed DPD uses Coordinate Rotation Digital Computing(CORDIC) processors and PD process by pipelined architecture. It is simpler and faster than conventional adaptive polynomial DPD. The performance of the proposed DPD is proved by MATLAB simulation.

Keywords: DPD, CORDIC.

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Authors: Shipra Upadhyay , R. K. Nagaria, R. A. Mishra

Abstract:

In this paper, we present the design and experimental evaluation of complementary energy path adiabatic logic (CEPAL) based 1 bit full adder circuit. A simulative investigation on the proposed full adder has been done using VIRTUOSO SPECTRE simulator of cadence in 0.18μm UMC technology and its performance has been compared with the conventional CMOS full adder circuit. The CEPAL based full adder circuit exhibits the energy saving of 70% to the conventional CMOS full adder circuit, at 100 MHz frequency and 1.8V operating voltage.

Keywords: Adiabatic, CEPAL, full adder, power clock

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Authors: Sattar B. Sadkhan, Najlae Falah Hameed

Abstract:

The Elliptic Curve Digital Signature Algorithm (ECDSA) is the elliptic curve analogue of DSA, where it is a digital signature scheme designed to provide a digital signature based on a secret number known only to the signer and also on the actual message being signed. These digital signatures are considered the digital counterparts to handwritten signatures, and are the basis for validating the authenticity of a connection. The security of these schemes results from the infeasibility to compute the signature without the private key. In this paper we introduce a proposed to development the original ECDSA with more complexity.

Keywords: Elliptic Curve Digital Signature Algorithm, DSA.

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Authors: Shubhajit Roy Chowdhury, Aritra Banerjee, Aniruddha Roy, Hiranmay Saha

Abstract:

The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been investigated using 0.15um and 0.35um technologies. Compared to the earlier designed 10 transistor full adder, the proposed adder shows a significant improvement in silicon area and power delay product. The whole simulation has been carried out using HSPICE.

Keywords: XOR gate, full adder, improvement in speed, area minimization, transistor count minimization.

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Authors: M.Hosseinghadiry, H. Mohammadi, M.Nadisenejani

Abstract:

with increasing circuits- complexity and demand to use portable devices, power consumption is one of the most important parameters these days. Full adders are the basic block of many circuits. Therefore reducing power consumption in full adders is very important in low power circuits. One of the most powerconsuming modules in full adders is XOR/XNOR circuit. This paper presents two new full adders based on two new logic approaches. The proposed logic approaches use one XOR or XNOR gate to implement a full adder cell. Therefore, delay and power will be decreased. Using two new approaches and two XOR and XNOR gates, two new full adders have been implemented in this paper. Simulations are carried out by HSPICE in 0.18μm bulk technology with 1.8V supply voltage. The results show that the ten-transistors proposed full adder has 12% less power consumption and is 5% faster in comparison to MB12T full adder. 9T is more efficient in area and is 24% better than similar 10T full adder in term of power consumption. The main drawback of the proposed circuits is output threshold loss problem.

Keywords: Full adder, XNOR, Low power, High performance, Very Large Scale Integrated Circuit.

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Authors: Anil Kumar Pandey

Abstract:

Power plane noise is the most significant source of signal integrity (SI) issues in a high-speed digital design. In this paper, power integrity (PI) analysis of multiple power planes in a power delivery system of a 12-layer high-speed FPGA board is presented. All 10 power planes of HSD board are analyzed separately by using 3D Electromagnetic based PI solver, then the transient simulation is performed on combined PI data of all planes along with voltage regulator modules (VRMs) and 70 current drawing chips to get the board level power noise coupling on different high-speed signals. De-coupling capacitors are placed between power planes and ground to reduce power noise coupling with signals.

Keywords: Channel simulation, electromagnetic simulation, power-aware signal integrity analysis, power integrity, PIPro.

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Authors: N. Popovich, P. Yan

Abstract:

In this paper a controller for the pitch angle of an aircraft regarding to the elevator deflection angle is designed. The way how the elevator angle affects pitching motion of the aircraft is pointed out, as well as, how a pitch controller can be applied for the aircraft to reach certain pitch angle. In this digital optimal system, the elevator deflection angle and pitching angle of the plane are considered to be input and output respectively. A single input single output (SISO) system is presented. A digital pitch aircraft control is demonstrated. A simulation for the whole system has been performed. The optimal control weighting vectors, Q and R have been determined.

Keywords: Aircraft, control, digital, optimal, Q and Rmatrices.

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Authors: Youngjae Jin, Daeshik Kim

Abstract:

This paper describes a cycle accurate simulation results of weight values learned by an auto-encoder behavior model in terms of pre-route simulation. Given the results we visualized the first layer representations with natural images. Many common deep learning threads have focused on learning high-level abstraction of unlabeled raw data by unsupervised feature learning. However, in the process of handling such a huge amount of data, the learning method’s computation complexity and time limited advanced research. These limitations came from the fact these algorithms were computed by using only single core CPUs. For this reason, parallel-based hardware, FPGAs, was seen as a possible solution to overcome these limitations. We adopted and simulated the ready-made auto-encoder to design a behavior model in VerilogHDL before designing hardware. With the auto-encoder behavior model pre-route simulation, we obtained the cycle accurate results of the parameter of each hidden layer by using MODELSIM. The cycle accurate results are very important factor in designing a parallel-based digital hardware. Finally this paper shows an appropriate operation of behavior model based pre-route simulation. Moreover, we visualized learning latent representations of the first hidden layer with Kyoto natural image dataset.

Keywords: Auto-encoder, Behavior model simulation, Digital hardware design, Pre-route simulation, Unsupervised feature learning.

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Authors: Ma Shidong, He Yuncheng, Wang Zhong, Yang Guoqing

Abstract:

In this paper, enhanced ground proximity warning simulation and validation system is designed and implemented. First, based on square grid and sub-grid structure, the global digital terrain database is designed and constructed. Terrain data searching is implemented through querying the latitude and longitude bands and separated zones of global terrain database with the current aircraft position. A combination of dynamic scheduling and hierarchical scheduling is adopted to schedule the terrain data, and the terrain data can be read and delete dynamically in the memory. Secondly, according to the scope, distance, approach speed information etc. to the dangerous terrain in front, and using security profiles calculating method, collision threat detection is executed in real-time, and provides caution and warning alarm. According to this scheme, the implementation of the enhanced ground proximity warning simulation system is realized. Simulations are carried out to verify a good real-time in terrain display and alarm trigger, and the results show simulation system is realized correctly, reasonably and stable.

Keywords: enhanced ground proximity warning system, digital terrain, look-ahead terrain alarm, terrain display, simulation and validation

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Authors: Amir Hossein Daei Sorkhabi, Bita Khazini

Abstract:

In this paper the intelligent control of full automatic car wash using a programmable logic controller (PLC) has been investigated and designed to do all steps of carwashing. The Intelligent control of full automatic carwash has the ability to identify and profile the geometrical dimensions of the vehicle chassis. Vehicle dimension identification is an important point in this control system to adjust the washing brushes position and time duration. The study also tries to design a control set for simulating and building the automatic carwash. The main purpose of the simulation is to develop criteria for designing and building this type of carwash in actual size to overcome challenges of automation. The results of this research indicate that the proposed method in process control not only increases productivity, speed, accuracy and safety but also reduce the time and cost of washing based on dynamic model of the vehicle. A laboratory prototype based on an advanced intelligent control has been built to study the validity of the design and simulation which it’s appropriate performance confirms the validity of this study.

Keywords: Automatic Carwash, Dimension, PLC.

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