Search results for: flip%20chip

Authors: Rohaya Abdul Wahab, Raja Mohd Fuad Tengku Aziz, Nazaliza Othman, Sharifah Saleh, Nabihah Razali, Rozaimah Baharim, Md Hanif Md Nasir

Abstract:

This paper will discuss flip chip methodology, in which I/O pads, standard cells, macros and bump cells array are placed in the floorplan, then routed using Astro place and route tool. Final DRC and LVS checking is done using Calibre verification tool. The design vehicle to run this methodology is an OpenRISC design targeted to Silterra 0.18 micrometer technology with 6 metal layers for routing. Astro has extensive support for flip chip placement and routing. Astro tool commands for flip chip are straightforward approach like the conventional standard wire bond packaging. However since we do not have flip chip commands in our Astro tool, no LEF file for bump cell and no LEF file for flip chip I/O pad, we create our own methodology to prepare for future flip chip tapeout. 

Keywords: Astro, bump cell, Calibre, flip chip, LEF, methodology, SCHEME, TCL.

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Authors: Masoud Jabbari, Mohammad Kazem Moravvej-Farshi, Rahim Ghayour, Abbas Zarifkar

Abstract:

In this paper, based on the coupled-mode and carrier rate equations, derivation of a dynamic model and numerically analysis of a MQW chirped DFB-SOA all-optical flip-flop is done precisely. We have analyzed the effects of strains of QW and MQW and cross phase modulation (XPM) on the dynamic response, and rise and fall times of the DFB-SOA all optical flip flop. We have shown that strained MQW active region in under an optimized condition into a DFB-SOA with chirped grating can improve the switching ON speed limitation in such a of the device, significantly while the fall time is increased. The values of the rise times for such an all optical flip-flop, are obtained in an optimized condition, areas tr=255ps.

Keywords: All-Optical Flip-Flop (AO-FF), Distributed feedback semiconductor optical amplifier (DFB-SOA), Optical Bistability, Multi quantum well (MQW)

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Authors: H. Kaatuzian, M. Sedghi, S. Khatami

Abstract:

In this paper, by exploiting a single semiconductor optical amplifier-Mach Zehnder Interferometer (SOA-MZI), an integratable all-optical flip-flop (AOFF) is proposed. It is composed of a SOA-MZI with a bidirectional coupler at the output. Output signals of both bar and crossbar of the SOA-MZI is fed back to SOAs located in the arms of the Mach-Zehnder Interferometer (MZI). The injected photon-rates to the SOAs are modulated by feedback signals in order to form optical flip-flop. According to numerical analysis, Gaussian optical pulses with the energy of 15.2 fJ and 20 ps duration with the full width at half-maximum criterion, can switch the states of the SR-AOFF. Also simulation results show that the SR-AOFF has the contrast ratio of 8.5 dB between two states with the transition time of nearly 20 ps.

Keywords: All Optical, Flip-Flop, Mach-Zehnder Interferometer (MZI), Semiconductor Optical Amplifier (SOA).

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Authors: Guo-Ming Sung, Naga Raju Naik R.

Abstract:

Paper presents a low power, high speed, sense-amplifier based flip-flop (SAFF). The flip-flop’s power con-sumption and delay are greatly reduced by employing a new conditionally precharge sense-amplifier stage and a single-ended latch stage. Glitch-free and contention-free latch operation is achieved by using a conditional cut-off strategy. The design uses fewer transistors, has a lower clock load, and has a simple structure, all of which contribute to a near-zero setup time. When compared to previous flip-flop structures proposed for similar input/output conditions, this design’s performance and overall PDP have improved. The post layout simulation of the circuit uses 2.91µW of power and has a delay of 65.82 ps. Overall, the power-delay product has seen some enhancements. Cadence Virtuoso Designing tool with CMOS 90nm technology are used for all designs.

Keywords: high-speed, low-power, flip-flop, sense-amplifier

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Authors: P. Nadimi, D. D. Caviglia, E. Di Zitti

Abstract:

We propose an all optical flip-flop circuit composedof two Silicon-on-insulator microring resonators coupled to straightwaveguides by exploiting the optical bistability behavior due to thenonlinear Kerr effect. We used the transfer matrix analysis toinvestigate continuous wave propagation through microrings, as wellwe considered the nonlinear switching characteristics of an opticaldevice using a double-coupler silicon ring resonator in presence ofthe Kerr nonlinearity, thus obtaining the bistability behavior of theoutput port, the drop port and also inside the silicon microringresonator. It is shown that the bistability behavior depends on thecontrol of the input wavelength.KeywordsAll optical flip-flops, Kerr effect, microringresonator, optical bistability.

Keywords: All optical flip-flops, Kerr effect, microring resonator, optical bistability.

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Authors: Zainudin Kornain, Azman Jalar, Rozaidi Rasid, Fong Chee Seng

Abstract:

Void formation in underfill is considered as failure in flip chip manufacturing process. Void formation possibly caused by several factors such as poor soldering and flux residue during die attach process, void entrapment due moisture contamination, dispense pattern process and setting up the curing process. This paper presents the comparison of single step and two steps curing profile towards the void and black dots formation in underfill for Hi-CTE Flip Chip Ceramic Ball Grid Array Package (FC-CBGA). Statistic analysis was conducted to analyze how different factors such as wafer lot, sawing technique, underfill fillet height and curing profile recipe were affected the formation of voids and black dots. A C-Mode Scanning Aqoustic Microscopy (C-SAM) was used to scan the total count of voids and black dots. It was shown that the 2 steps curing profile provided solution for void elimination and black dots in underfill after curing process.

Keywords: black dots formation, curing profile, FC-CBGA, underfill, void formation,

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Authors: R. Manjith, C. Muthukumari

Abstract:

In this paper, a novel Linear Feedback Shift Register (LFSR) with Look Ahead Clock Gating (LACG) technique is presented to reduce the power consumption in modern processors and System-on-Chip. Clock gating is a predominant technique used to reduce unwanted switching of clock signals. Several clock gating techniques to reduce the dynamic power have been developed, of which LACG is predominant. LACG computes the clock enabling signals of each flip-flop (FF) one cycle ahead of time, based on the present cycle data of the flip-flops on which it depends. It overcomes the timing problems in the existing clock gating methods like datadriven clock gating and Auto-Gated flip-flops (AGFF) by allotting a full clock cycle for the determination of the clock enabling signals. Further to reduce the power consumption in LACG technique, FFs can be grouped so that they share a common clock enabling signal. Simulation results show that the novel grouped LFSR with LACG achieves 15.03% power savings than conventional LFSR with LACG and 44.87% than data-driven clock gating.

Keywords: AGFF, data-driven, LACG, LFSR.

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Authors: Hema Sandhya Jagarlamudi, Mousumi Saha, Pavan Kumar Jagarlamudi

Abstract:

The use of Quantum dots is a promising emerging Technology for implementing digital system at the nano level. It is effecient for attractive features such as faster speed , smaller size and low power consumption than transistor technology. In this paper, various Combinational and sequential logical structures - HALF ADDER, SR Latch and Flip-Flop, D Flip-Flop preceding NAND, NOR, XOR,XNOR are discussed based on QCA design, with comparatively less number of cells and area. By applying these layouts, the hardware requirements for a QCA design can be reduced. These structures are designed and simulated using QCA Designer Tool. By taking full advantage of the unique features of this technology, we are able to create complete circuits on a single layer of QCA. Such Devices are expected to function with ultra low power Consumption and very high speeds.

Keywords: QCA, QCA Designer, Clock, Majority Gate

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Authors: L. Parisi, D. Hamili, N. Azlan

Abstract:

The aim of this study was to design and simulate a particular type of Asynchronous State Machine (ASM), namely a ‘traffic light controller’ (TLC), operated at a frequency of 0.5 Hz. The design task involved two main stages: firstly, designing a 4-bit binary counter using J-K flip flops as the timing signal and, subsequently, attaining the digital logic by deploying ASM design process. The TLC was designed such that it showed a sequence of three different colours, i.e. red, yellow and green, corresponding to set thresholds by deploying the least number of AND, OR and NOT gates possible. The software Multisim was deployed to design such circuit and simulate it for circuit troubleshooting in order for it to display the output sequence of the three different colours on the traffic light in the correct order. A clock signal, an asynchronous 4- bit binary counter that was designed through the use of J-K flip flops along with an ASM were used to complete this sequence, which was programmed to be repeated indefinitely. Eventually, the circuit was debugged and optimized, thus displaying the correct waveforms of the three outputs through the logic analyser. However, hazards occurred when the frequency was increased to 10 MHz. This was attributed to delays in the feedback being too high.

Keywords: Asynchronous State Machine, Traffic Light Controller, Circuit Design, Digital Electronics.

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Authors: Hamid Yasinian

Abstract:

Random epistemologies and hash tables have garnered minimal interest from both security experts and experts in the last several years. In fact, few information theorists would disagree with the evaluation of expert systems. In our research, we discover how flip-flop gates can be applied to the study of superpages. Though such a hypothesis at first glance seems perverse, it is derived from known results.

Keywords: Synthesis, Multi-Processors, Interactive Model, Moor’s Law.

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Authors: Chigbogu G. Ozoegwu, Sam N. Omenyi

Abstract:

The objective in this work is to generate and discuss the stability results of fully-immersed end-milling process with parameters; tool mass m=0.0431kg,tool natural frequency ω_n = 5700 rads^-1, damping factor ξ=0.002 and workpiece cutting coefficient C=3.5x10^7 Nm^-7/4. Different no of teeth is considered for the end-milling. Both 1-DOF and 2-DOF chatter models of the system are generated on the basis of non-linear force law. Chatter stability analysis is carried out using a modified form (generalized for both 1-DOF and 2-DOF models) of recently developed method called Full-discretization. The full-immersion three tooth end-milling together with higher toothed end-milling processes has secondary Hopf bifurcation lobes (SHBL’s) that exhibit one turning (minimum) point each. Each of such SHBL is demarcated by its minimum point into two portions; (i) the Lower Spindle Speed Portion (LSSP) in which bifurcations occur in the right half portion of the unit circle centred at the origin of the complex plane and (ii) the Higher Spindle Speed Portion (HSSP) in which bifurcations occur in the left half portion of the unit circle. Comments are made regarding why bifurcation lobes should generally get bigger and more visible with increase in spindle speed and why flip bifurcation lobes (FBL’s) could be invisible in the low-speed stability chart but visible in the high-speed stability chart of the fully-immersed three-tooth miller.

Keywords: Chatter, flip bifurcation, modified full-discretization map stability lobe, secondary Hopf bifurcation.

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Authors: Byung Hoon Seo, Hyun Gyu Kim, Tae Won Seo

Abstract:

Stair climbing is one of critical issues for field robots to widen applicable areas. This paper presents optimal design on kinematic parameters of a new robotic platform for stair climbing. The robotic platform climbs various stairs by body flip locomotion with caterpillar type main platform. Kinematic parameters such as platform length, platform height, and caterpillar rotation speed are optimized to maximize stair climbing stability. Three types of stairs are used to simulate typical user conditions. The optimal design process is conducted based on Taguchi methodology, and resulting parameters with optimized objective function are presented. In near future, a prototype is assembled for real environment testing.

Keywords: Stair climbing robot, Optimal design, Taguchi methodology, Caterpillar, Kinematic parameters.

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Authors: L. Lancaster, M. H. Lung, D. Sujan

Abstract:

The application of agro-industrial waste in Aluminum Metal Matrix Composites has been getting more attention as they can reinforce particles in metal matrix which enhance the strength properties of the composites. In addition, by applying these agroindustrial wastes in useful way not only save the manufacturing cost of products but also reduce the pollutions on environment. This paper represents a literature review on a range of industrial wastes and their utilization in metal matrix composites. The paper describes the synthesis methods of agro-industrial waste filled metal matrix composite materials and their mechanical, wear, corrosion, and physical properties. It also highlights the current application and future potential of agro-industrial waste reinforced composites in aerospace, automotive and other construction industries.

Keywords: Bond layer, Interfacial shear stress, Bi-layered assembly, Thermal mismatch, Flip Chip Ball Grid Array.

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Authors: Mayank Shakya, Soundra Pandian. K. K

Abstract:

A linear feedback shift register (LFSR) is proposed which targets to reduce the power consumption from within. It reduces the power consumption during testing of a Circuit Under Test (CUT) at two stages. At first stage, Control Logic (CL) makes the clocks of the switching units of the register inactive for a time period when output from them is going to be same as previous one and thus reducing unnecessary switching of the flip-flops. And at second stage, the LFSR reorders the test vectors by interchanging the bit with its next and closest neighbor bit. It keeps fault coverage capacity of the vectors unchanged but reduces the Total Hamming Distance (THD) so that there is reduction in power while shifting operation.

Keywords: Linear Feedback Shift Register, Total Hamming Distance, Fault Coverage, Control Logic

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Authors: Y. Li, Q. S. Zhang, H. Z. Huang, B. Y. Wu

Abstract:

The mechanism behind the electromigration and thermomigration failure in flip-chip solder joints with Cu-pillar bumps was investigated in this paper through using finite element method. Hot spot and the current crowding occurrs in the upper corner of copper column instead of solders of the common solder ball. The simulation results show that the change in thermal gradient is noticeable, which might greatly affect the reliability of solder joints with Cu-pillar bumps under current stressing. When the average applied current density is increased from 1×104 A/cm2 to 3×104 A/cm2 in solders, the thermal gradient would increase from 74 K/cm to 901 K/cm at an ambient temperature of 25°C. The force from thermal gradient of 901 K/cm can nearly induce thermomigration by itself. With the increase in applied current, the thermal gradient is growing. It is proposed that thermomigration likely causes a serious reliability issue for Cu column based interconnects.

Keywords: Simulation, Cu-pillar bumps, Electromigration, Thermomigration.

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Authors: P.K. Sharma, B. Bhargava, S. Akashe

Abstract:

Power dissipation due to leakage current in the digital circuits is a biggest factor which is considered specially while designing nanoscale circuits. This paper is exploring the ideas of reducing leakage current in static CMOS circuits by stacking the transistors in increasing numbers. Clearly it means that the stacking of OFF transistors in large numbers result a significant reduction in power dissipation. Increase in source voltage of NMOS transistor minimizes the leakage current. Thus stacking technique makes circuit with minimum power dissipation losses due to leakage current. Also some of digital circuits such as full adder, D flip flop and 6T SRAM have been simulated in this paper, with the application of reduction technique on ‘cadence virtuoso tool’ using specter at 45nm technology with supply voltage 0.7V.

Keywords: Stack, 6T SRAM cell, low power, threshold voltage

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Authors: Vishal Awasthi, Krishna Raj

Abstract:

Unwanted side effects because of spectral aliasing and spectral imaging during signal processing would be the major concern over the sampling rate alteration. Multirate-multistage implementation of digital filter could come about a large computational saving than single rate filter suitable for sample rate conversion. This implementation can further improve through high-level architectural transformation in circuit level. Reallocating registers and  relocating flip-flops across logic gates through retiming certainly a prominent sequential transformation technology, that optimize hardware circuits to achieve faster clocking speed without affecting the functionality. In this paper, we proposed an efficient compensated cascade Integrator comb (CIC) decimation filter structure that analyze the consequence of filter order variation which has a retimed FIR filter being compensator while using the cutset retiming technique and achieved an improvement in the passband droop by 14% to 39%, in computation time by 38.04%, 25.78%, 12.21%, 6.69% and 4.44% and reduction in path delay by 62.27%, 72%, 86.63%, 91.56% and 94.42% of 3, 6, 8, 12 and 24 order filter respectively than the non-retimed CIC compensation filter.

Keywords: Multirate Filtering, CIC decimation filter, Compensation theory, Retiming, Retiming algorithm, Filter order, Synchronous dataflow graph.

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Authors: Rajesh Mehra, Bharti Thakur

Abstract:

In this paper, an Infinite Impulse Response (IIR) filter has been designed and simulated on an Field Programmable Gate Arrays (FPGA). The implementation is based on Multiply Add and Accumulate (MAC) algorithm which uses multiply operations for design implementation. Parallel Pipelined structure is used to implement the proposed IIR Filter taking optimal advantage of the look up table of target device. The designed filter has been synthesized on Digital Signal Processor (DSP) slice based FPGA to perform multiplier function of MAC unit. The DSP slices are useful to enhance the speed performance. The proposed design is simulated with Matlab, synthesized with Xilinx Synthesis Tool, and implemented on FPGA devices. The Virtex 5 FPGA based design can operate at an estimated frequency of 81.5 MHz as compared to 40.5 MHz in case of Spartan 3 ADSP based design. The Virtex 5 based implementation also consumes less slices and slice flip flops of target FPGA in comparison to Spartan 3 ADSP based implementation to provide cost effective solution for signal processing applications.

Keywords: Butterworth, DSP, IIR, MAC, FPGA.

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Authors: Syed Javed Arif, Mohd Ayyub Khan, Saleem Anwar Khan

Abstract:

In this paper, a simple method is presented for measurement of power frequency deviations. A phase locked loop (PLL) is used to multiply the signal under test by a factor of 100. The number of pulses in this pulse train signal is counted over a stable known period, using decade driving assemblies (DDAs) and flip-flops. These signals are combined using logic gates and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded. These pulses are equally suitable for both control applications and display units. The experimental circuit developed gives a resolution of 1 Hz within the measurement period of 20 ms. The proposed circuit is also simulated in Verilog Hardware Description Language (VHDL) and implemented using Field Programing Gate Arrays (FPGAs). A Mixed signal Oscilloscope (MSO) is used to observe the results of FPGA implementation. These results are compared with the results of the proposed circuit of discrete components. The proposed system is useful for frequency deviation measurement and control in power systems.

Keywords: Frequency measurement, digital control, phase locked loop, encoding, Verilog HDL.

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Authors: K. Maria Agnes, J. Joshua Bapu

Abstract:

This paper impart the design and testing of Nanotechnology based sequential circuits using multiplexer conservative QCA (MX-CQCA) logic gates, which is easily testable using only two vectors. This method has great prospective in the design of sequential circuits based on reversible conservative logic gates and also smashes the sequential circuits implemented in traditional gates in terms of testability. Reversible circuits are similar to usual logic circuits except that they are built from reversible gates. Designs of multiplexer conservative QCA logic based two vectors testable double edge triggered (DET) sequential circuits in VHDL language are also accessible here; it will also diminish intricacy in testing side. Also other types of sequential circuits such as D, SR, JK latches are designed using this MX-CQCA logic gate. The objective behind the proposed design methodologies is to amalgamate arithmetic and logic functional units optimizing key metrics such as garbage outputs, delay, area and power. The projected MX-CQCA gate outshines other reversible gates in terms of the intricacy, delay.

Keywords: Conservative logic, Double edge triggered (DET) flip flop, majority voters, MX-CQCA gate, reversible logic, Quantum dot Cellular automata.

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Authors: Tharwat N. Hijjawi

Abstract:

Learning oral skills in an Arabic speaking environment is challenging. A blended course (material, activities, and individual/ group work tasks …) was implemented in a module of level B1 for undergraduate students of French as a foreign language in order to increase their opportunities to practice listening and speaking skills. This research investigates the influence of this modality on enhancing active learning and examines the effectiveness of provided strategies. Moreover, it aims at discovering how it allows teacher to flip the traditional classroom and create a learner-centered framework. Which approaches were integrated to motivate students and urge them to search, analyze, criticize, create and accomplish projects? What was the perception of students? This paper is based on the qualitative findings of a questionnaire and a focus group interview with learners. Despite the doubled time and effort both “teacher” and “student” needed, results revealed that the NTIC allowed a shift into a learning paradigm where learners were the “chiefs” of the process. Tasks and collaborative projects required higher intellectual capacities from them. Learners appreciated this experience and developed new life-long learning competencies at many levels: social, affective, ethical and cognitive. To conclude, they defined themselves as motivated young researchers, motivators and critical thinkers.

Keywords: Active learning, critical thinking, inverted classroom, learning paradigm, problem-based.

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Authors: Mohammed A. Alolfe, Abou-Bakr M. Youssef, Yasser M. Kadah

Abstract:

The proper design of RF pulses in magnetic resonance imaging (MRI) has a direct impact on the quality of acquired images, and is needed for many applications. Several techniques have been proposed to obtain the RF pulse envelope given the desired slice profile. Unfortunately, these techniques do not take into account the limitations of practical implementation such as limited amplitude resolution. Moreover, implementing constraints for special RF pulses on most techniques is not possible. In this work, we propose to develop an approach for designing optimal RF pulses under theoretically any constraints. The new technique will pose the RF pulse design problem as a combinatorial optimization problem and uses efficient techniques from this area such as genetic algorithms (GA) to solve this problem. In particular, an objective function will be proposed as the norm of the difference between the desired profile and the one obtained from solving the Bloch equations for the current RF pulse design values. The proposed approach will be verified using analytical solution based RF simulations and compared to previous methods such as Shinnar-Le Roux (SLR) method, and analysis, selected, and tested the options and parameters that control the Genetic Algorithm (GA) can significantly affect its performance to get the best improved results and compared to previous works in this field. The results show a significant improvement over conventional design techniques, select the best options and parameters for GA to get most improvement over the previous works, and suggest the practicality of using of the new technique for most important applications as slice selection for large flip angles, in the area of unconventional spatial encoding, and another clinical use.

Keywords: Selective excitation, magnetic resonance imaging, combinatorial optimization, pulse design.

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