Search results for: five topologies

Authors: C. Malça, P. Gonçalves, N. Alves, A. Mateus

Abstract:

Regardless of the manufacturing process used, subtractive or additive, material, purpose and application, produced components are conventionally solid mass with more or less complex shape depending on the production technology selected. Aspects such as reducing the weight of components, associated with the low volume of material required and the almost non-existent material waste, speed and flexibility of production and, primarily, a high mechanical strength combined with high structural performance, are competitive advantages in any industrial sector, from automotive, molds, aviation, aerospace, construction, pharmaceuticals, medicine and more recently in human tissue engineering. Such features, properties and functionalities are attained in metal components produced using the additive technique of Rapid Prototyping from metal powders commonly known as Selective Laser Melting (SLM), with optimized internal topologies and varying densities. In order to produce components with high strength and high structural and functional performance, regardless of the type of application, three different internal topologies were developed and analyzed using numerical computational tools. The developed topologies were numerically submitted to mechanical compression and four point bending testing. Finite Element Analysis results demonstrate how different internal topologies can contribute to improve mechanical properties, even with a high degree of porosity relatively to fully dense components. Results are very promising not only from the point of view of mechanical resistance, but especially through the achievement of considerable variation in density without loss of structural and functional high performance.

Keywords: Additive Manufacturing, Internal topologies, Porosity, Rapid Prototyping, Selective Laser Melting.

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Authors: Haniza N., Md Khambari, M. N, Shahrin S., Adib M.Monzer Habbal, Suhaidi Hassan

Abstract:

Wireless ad hoc nodes are freely and dynamically self-organize in communicating with others. Each node can act as host or router. However it actually depends on the capability of nodes in terms of its current power level, signal strength, number of hops, routing protocol, interference and others. In this research, a study was conducted to observe the effect of hops count over different network topologies that contribute to TCP Congestion Control performance degradation. To achieve this objective, a simulation using NS-2 with different topologies have been evaluated. The comparative analysis has been discussed based on standard observation metrics: throughput, delay and packet loss ratio. As a result, there is a relationship between types of topology and hops counts towards the performance of ad hoc network. In future, the extension study will be carried out to investigate the effect of different error rate and background traffic over same topologies.

Keywords: NS-2, network topology, network performance, multi-hops

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Authors: Ekkaluk Eksook, Chutima Prommak

Abstract:

This paper address the network reliability optimization problem in the optical access network design for the 3G cellular systems. We presents a novel 0-1 integer programming model for designing optical access network topologies comprised of multi-rings with common-edge in order to guarantee always-on services. The results show that the proposed model yields access network topologies with the optimal reliablity and satisfies both network cost limitations and traffic demand requirements.

Keywords: Network Reliability, Topological Network Design, 3G Cellular Networks.

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Authors: P. Kiruthika, K. Ramani

Abstract:

Multi-Level Inverter technology has been developed in the area of high-power medium-voltage energy scheme, because of their advantages such as devices of lower rating can be used thereby enabling the schemes to be used for high voltage applications. Reduced Total Harmonic Distortion (THD).Since the dv/dt is low; the Electromagnetic Interference from the scheme is low. To avoid the switching losses Lower switching frequencies can be used. In this paper present a survey of various topologies, control strategy and modulation techniques used by these inverters. Here the regenerative and superior topologies are also discussed.

Keywords: Cascaded H-bridge Multi-Level Inverter, Diode Clamped Multi-Level Inverter, Flying Capacitors Multi- Level Inverter, Multi-Level Inverter, Total Harmonic Distortion.

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Authors: P. Varalaxmi, A. Kirubakaran

Abstract:

This paper presents a thirteen-level asymmetrical cascaded H-bridge single phase inverter. In this configuration, the desired output voltage level is achieved by connecting the DC sources in different combinations by triggering the switches. The modes of operation are explained well for positive level generations. Moreover, a comparison is made with conventional topologies of diode clamped, flying capacitors and cascaded-H-bridge and some recently proposed topologies to show the significance of the proposed topology in terms of reduced part counts. The simulation work has been carried out in MATLAB/Simulink environment. The experimental work is also carried out for lower rating to verify the performance and feasibility of the proposed topology. Further the results are presented for different loading conditions.

Keywords: Multilevel inverter, pulse width modulation, total harmonic distortion, THD.

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Authors: Aimeng Wang, Dejun Ma, Hui Wang

Abstract:

The paper presents a detailed calculation of characteristic of five different topology permanent magnet machines for high performance traction including hybrid -electric vehicles using finite element analysis (FEA) method. These machines include V-shape single layer interior PM, W-shape single-layer interior PM, Segment interior PM and surface PM on the rotor and with distributed winding on the stator. The performance characteristics which include the back-emf voltage and its harmonic, magnet mass, iron loss and ripple torque are compared and analyzed. One of a 7.5kW IPM prototype was tested and verified finite-element analysis results. The aim of the paper is given some guidance and reference for machine designer which are interested in IPM machine selection for high performance traction application.

Keywords: Interior permanent magnet machine, finite-element analysis (FEA), five topologies, electric vehicle.

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Authors: Kuen-Long Leu, Yung-Yuan Chen, Chin-Long Wey, Jwu-E Chen, Chung-Hsien Hsu

Abstract:

The increasing importance of FlexRay systems in automotive domain inspires unceasingly relative researches. One primary issue among researches is to verify the reliability of FlexRay systems either from protocol aspect or from system design aspect. However, research rarely discusses the effect of network topology on the system reliability. In this paper, we will illustrate how to model the reliability of FlexRay systems with various network topologies by a well-known probabilistic reasoning technology, Bayesian Network. In this illustration, we especially investigate the effectiveness of error containment built in star topology and fault-tolerant midpoint synchronization algorithm adopted in FlexRay communication protocol. Through a FlexRay steer-by-wire case study, the influence of different topologies on the failure probability of the FlexRay steerby- wire system is demonstrated. The notable value of this research is to show that the Bayesian Network inference is a powerful and feasible method for the reliability assessment of FlexRay systems.

Keywords: Bayesian Network, FlexRay, fault tolerance, network topology, reliability.

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Authors: A. Hassoune, M. Khafallah, A. Mesbahi, T. Bouragba

Abstract:

This work presents an improved strategy of control for charging a lithium-ion battery in an electric vehicle charging station using two charger topologies i.e. single ended primary inductor converter (SEPIC) and forward converter. In terms of rapidity and accuracy, the power system consists of a topology/control diagram that would overcome the performance constraints, for instance the power instability, the battery overloading and how the energy conversion blocks would react efficiently to any kind of perturbations. Simulation results show the effectiveness of the proposed topologies operated with a power management algorithm based on voltage/peak current mode controls. In order to provide credible findings, a low power prototype is developed to test the control strategy via experimental evaluations of the converter topology and its controls.

Keywords: Battery charger, forward converter, lithium-ion, management algorithm, SEPIC.

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Authors: A. Pouhassani

Abstract:

The aim of this paper is to exhibit some properties of local topologies of an IVS. Also, we Introduce ISG structure as an interesting structure of semigroups in IVSs.

Keywords: IVS, ISG, Local topology, Lebesgue number, Lindelof theorem

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Authors: Mahmoud Elmezain, Ayoub Al-Hamadi, Jörg Appenrodt, Bernd Michaelis

Abstract:

Gesture recognition is a challenging task for extracting meaningful gesture from continuous hand motion. In this paper, we propose an automatic system that recognizes isolated gesture, in addition meaningful gesture from continuous hand motion for Arabic numbers from 0 to 9 in real-time based on Hidden Markov Models (HMM). In order to handle isolated gesture, HMM using Ergodic, Left-Right (LR) and Left-Right Banded (LRB) topologies is applied over the discrete vector feature that is extracted from stereo color image sequences. These topologies are considered to different number of states ranging from 3 to 10. A new system is developed to recognize the meaningful gesture based on zero-codeword detection with static velocity motion for continuous gesture. Therefore, the LRB topology in conjunction with Baum-Welch (BW) algorithm for training and forward algorithm with Viterbi path for testing presents the best performance. Experimental results show that the proposed system can successfully recognize isolated and meaningful gesture and achieve average rate recognition 98.6% and 94.29% respectively.

Keywords: Computer Vision & Image Processing, Gesture Recognition, Pattern Recognition, Application

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Authors: M. S. Sivagamasundari, P. Melba Mary

Abstract:

Multilevel inverter is a promising inverter topology for high voltage and high power applications. This inverter synthesizes several different levels of DC voltages to produce a stepped AC output that approaches the pure sine waveform. The three different topologies, diode-clamped inverter, capacitor-clamped inverter and cascaded h-bridge multilevel inverter are widely used in these multilevel inverters. Among the three topologies, cascaded h-bridge multilevel inverter is more suitable for photovoltaic applications since each PV array can act as a separate dc source for each h-bridge module. This research especially focus on photovoltaic power source as input to the system and shows the potential of a Single Phase Cascaded H-bridge Eleven level inverter governed by the fuzzy logic controller to improve the power quality by reducing the total harmonic distortion at the output voltage. Hence the efficiency of the system will be improved. Simulation using MATLAB/SIMULINK has been done to verify the performance of cascaded h-bridge eleven level inverter using sinusoidal pulse width modulation technique. The simulated output shows very favorable result.

Keywords: Multilevel inverter, Cascaded H-Bridge multilevel inverter, Total Harmonic Distortion, Photovoltaic cell, Sinusoidal pulse width modulation.

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Authors: Mohammad Ali Jabraeil Jamali, Ahmad Khademzadeh

Abstract:

The success of an electronic system in a System-on- Chip is highly dependent on the efficiency of its interconnection network, which is constructed from routers and channels (the routers move data across the channels between nodes). Since neither classical bus based nor point to point architectures can provide scalable solutions and satisfy the tight power and performance requirements of future applications, the Network-on-Chip (NoC) approach has recently been proposed as a promising solution. Indeed, in contrast to the traditional solutions, the NoC approach can provide large bandwidth with moderate area overhead. The selected topology of the components interconnects plays prime rule in the performance of NoC architecture as well as routing and switching techniques that can be used. In this paper, we present two generic NoC architectures that can be customized to the specific communication needs of an application in order to reduce the area with minimal degradation of the latency of the system. An experimental study is performed to compare these structures with basic NoC topologies represented by 2D mesh, Butterfly-Fat Tree (BFT) and SPIN. It is shown that Cluster mesh (CMesh) and MinRoot schemes achieves significant improvements in network latency and energy consumption with only negligible area overhead and complexity over existing architectures. In fact, in the case of basic NoC topologies, CMesh and MinRoot schemes provides substantial savings in area as well, because they requires fewer routers. The simulation results show that CMesh and MinRoot networks outperforms MESH, BFT and SPIN in main performance metrics.

Keywords: MinRoot, CMesh, NoC, Topology, Performance Evaluation

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Authors: Ahmet Z. Ozcelik, Serkan Narli

Abstract:

In this study, a minimal submaximal element of LIT(X) (the lattice of all intuitionistic topologies for X, ordered by inclusion) is determined. Afterwards, a new contractive property, intuitionistic mega-connectedness, is defined. We show that the submaximality and mega-connectedness are not complementary intuitionistic topological invariants by identifying those members of LIT(X) which are intuitionistic mega-connected.

Keywords: Intuitionistic set; intuitionistic topology;intuitionistic submaximality and mega-connectedness.

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Authors: Y. Kobori, L. Xing, H. Gao, N.Onozawa, S. Wu, S. N. Mohyar, Z. Nosker, H. Kobayashi, N. Takai, K. Niitsu

Abstract:

This paper proposes two types of non-isolated direct AC-DC converters. First, it shows a buck-boost converter with an H-bridge, which requires few components (three switches, two diodes, one inductor and one capacitor) to convert AC input to DC output directly. This circuit can handle a wide range of output voltage. Second, a direct AC-DC buck converter is proposed for lower output voltage applications. This circuit is analyzed with output voltage of 12V. We describe circuit topologies, operation principles and simulation results for both circuits.

Keywords: AC-DC converter, Buck-boost converter, Buck converter, PFC, BCM PFC circuit.

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Authors: Ranjan Kumar Dash, Chita Ranjan Tripathy

Abstract:

The evaluation of residual reliability of large sized parallel computer interconnection systems is not practicable with the existing methods. Under such conditions, one must go for approximation techniques which provide the upper bound and lower bound on this reliability. In this context, a new approximation method for providing bounds on residual reliability is proposed here. The proposed method is well supported by two algorithms for simulation purpose. The bounds on residual reliability of three different categories of interconnection topologies are efficiently found by using the proposed method

Keywords: Parallel computer network, reliability, probabilisticgraph, interconnection networks.

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Authors: Eduardo Romero, Marcelo Costamagna, Gabriela Peretti, Carlos Marqués

Abstract:

This work evaluates the ability of OBT for detecting parametric faults in continuous-time filters. To this end, we adopt two filters with quite different topologies as cases of study and a previously reported statistical fault model. In addition, we explore the behavior of the test schemes when a particular test condition is changed. The new data reported here, obtained from a fault simulation process, reveal a lower performance of OBT not observed in previous work using single-deviation faults, even under the change in the test condition.

Keywords: Testing, analog fault simulation, analog filter test, oscillation based test.

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Authors: A. Youseef

Abstract:

IEEE 802.16 (WiMAX) aims to present high speed wireless access to cover wide range coverage. The base station (BS) and the subscriber station (SS) are the main parts of WiMAX. WiMAX uses either Point-to-Multipoint (PMP) or mesh topologies. In the PMP mode, the SSs connect to the BS to gain access to the network. However, in the mesh mode, the SSs connect to each other to gain access to the BS. The main components of QoS management in the 802.16 standard are the admission control, buffer management and packet scheduling. In this paper, we use QualNet 5.0.2 to study the performance of different scheduling schemes, such as WFQ, SCFQ, RR and SP when the numbers of SSs increase. We find that when the number of SSs increases, the average jitter and average end-to-end delay is increased and the throughput is reduced.

Keywords: WiMAX, Scheduling Scheme, QoS, QualNet.

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Authors: A. Inba Rexy, R. Seyezhai

Abstract:

Through the fast growing technologies, design of power factor correction (PFC) circuit is facing several challenges. In this paper, a two-phase interleaved boost converter with ripple steering technique is proposed. Among the various topologies, Interleaved Boost converter (IBC) is considered as superior due to enriched performance, lower ripple content, compact weight and size. A thorough investigation is presented here for the proposed topology. Simulation study for the IBC has been carried out using MATLAB/SIMULINK. Theoretical analysis and hardware prototype has been performed to validate the results.

Keywords: Interleaved Boost Converter (IBC), Power Factor Correction (PFC), Ripple Steering Technique, Ripple, and Simulation.

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Authors: Yogesh Pahariya, Rakesh Saxena, Biswaroop Sarkar

Abstract:

The selection of control strategy depends on the converters of the drive including power, speed, performance and the possible system costs. A number of attempts were therefore made in recent times to develop novel power electronic converter structures for SRM drives, based on the utilization. Many of the converters with variable speed drives have no input power factor correction circuits. This results in harmonic pollution of the utility supply, which should be avoided. The effect of power factor variation in terms of harmonic content is also analyzed in this study. The proposed topologies were simulated using MATLAB / Simulink software package and the results are obtained.

Keywords: Harmonic Pollution, Power Electronic Converter, Power Quality, Simulation.

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Authors: M. Jagabar Sathik, K. Ramani

Abstract:

In this paper family of multilevel inverter topology with reduced number of power switches is presented. The proposed inverter can generate both even and odd level. The proposed topology is suitable for symmetric structure. The proposed symmetric inverter results in reduction of power switches, power diode and gate driver circuits and also it may further minimize the installation area and cost. To prove the superiority of proposed topology is compared with conventional topologies. The performance of this symmetric multilevel inverter has been tested by computer based simulation and prototype based experimental setup for nine-level inverter is developed and results are verified.

Keywords: Cascaded H- Bridge (CHB), Multilevel Inverter (MLI), Nearest Level Modulation (NLM), Total Harmonic Distortion (THD).

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Authors: Gurjinder Kaur, Yogesh Chaba, V. K. Jain

Abstract:

The aim of this paper is to explore the security issues that significantly affect the performance of Mobile Adhoc Networks (MANET)and limit the services provided to their intended users. The MANETs are more vulnerable to Distributed Denial of Service attacks (DDoS) because of their properties like shared medium, dynamic topologies etc. A DDoS attack is a coordinated attempt made by malicious users to flood the victim network with the large amount of data such that the resources of the victim network are exhausted resulting in the deterioration of the network performance. This paper highlights the effects of different types of DDoS attacks in MANETs and categorizes them according to their behavior.

Keywords: Distributed Denial, Mobile Adhoc Networks

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Authors: Neethu S., Shinoy K.S., A.S. Shajilal

Abstract:

This paper presents the optimal design and development of an axial flux motor for blood pump application. With the design objective of maximizing the motor efficiency and torque, different topologies of AFPM machine has been examined. Selection of optimal magnet fraction, Halbach arrangement of rotor magnets and the use of Soft Magnetic Composite (SMC) material for the stator core results in a novel motor with improved efficiency and torque profile. The results of the 3D Finite element analysis for the novel motor have been shown.

Keywords: Axial flux motor, Finite Element Methods, Halbach array, Left Ventricular Assist Device, Soft magnetic composite.

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Authors: Smko Zangana, Ergun Ercelebi

Abstract:

The alternating current is the main power in all industries and other aspects especially for the short and mid distances, but as far as long a distance which exceeds 500 KMs, using the alternating current technically will face many difficulties and more costs because it's difficult to control the current and also other restrictions. Therefore, recently those reasons led to building transmission lines HVDC to transmit power for long distances. This document presents technical comparison and assessments for power transmission system among distances either ways and studying the stability of the system regarding the proportion of losses in the actual power sent and received between both sides in different systems and also categorizing filters used in the HVDC system and its impact and effect on reducing Harmonic in the power transmission. MATLAB /Simulink simulation software is used to simulate both HVAC & HVDC power transmission system topologies.

Keywords: HVAC power system, HVDC power system, power system simulation (MATLAB), the alternating current, voltage stability.

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Authors: Abdelkrim Zitouni, Mounir Zid, Sami Badrouchi, Rached Tourki

Abstract:

The Globally Asynchronous Locally Synchronous Network on Chip (GALS NoC) is the most efficient solution that provides low latency transfers and power efficient System on Chip (SoC) interconnect. This study presents a GALS and generic NoC architecture based on a configurable router. This router integrates a sophisticated dynamic arbiter, the wormhole routing technique and can be configured in a manner that allows it to be used in many possible NoC topologies such as Mesh 2-D, Tree and Polygon architectures. This makes it possible to improve the quality of service (QoS) required by the proposed NoC. A comparative performances study of the proposed NoC architecture, Tore architecture and of the most used Mesh 2D architecture is performed. This study shows that Spidergon architecture is characterised by the lower latency and the later saturation. It is also shown that no matter what the number of used links is raised; the Links×Diameter product permitted by the Spidergon architecture remains always the lower. The only limitation of this architecture comes from it-s over cost in term of silicon area.

Keywords: Dynamic arbiter, Generic router, Spidergon NoC, SoC.

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Authors: Devin Atkin, Orly Yadid-Pecht

Abstract:

The continual demands for increasing resolution and dynamic range in complimentary metal-oxide semiconductor (CMOS) image sensors have resulted in exponential increases in the amount of data that need to be read out of an image sensor, and existing readouts cannot keep up with this demand. Interesting approaches such as sparse and burst readouts have been proposed and show promise, but at considerable trade-offs in other specifications. To this end, we have begun designing and evaluating various readout topologies centered around an attempt to parallelize the sensor readout. In this paper, we have designed, simulated, and started testing a light-controlled oscillator topology with dual column and row readouts. We expect the parallel readout structure to offer greater speed and alleviate the trade-off typical in this topology, where slow pixels present a major framerate bottleneck.

Keywords: CMOS image sensors, high-speed capture, wide dynamic range, light controlled oscillator.

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Authors: Antonis Constantinides, Christos Yiallouras, Christakis Damianou

Abstract:

The application of today's semiconductor transistors in high power UHF DVB-T linear amplifiers has evolved significantly by utilizing LDMOS technology. This fact provides engineers with the option to design a single transistor signal amplifier which enables output power and linearity that was unobtainable previously using bipolar junction transistors or later type first generation MOSFETS. The quiescent current stability in terms of thermal variations of the LDMOS guarantees a robust operation in any topology of DVB-T signal amplifiers. Otherwise, progressively uncontrolled heat dissipation enhancement on the LDMOS case can degrade the amplifier’s crucial parameters in regards to the gain, linearity and RF stability, resulting in dysfunctional operation or a total destruction of the unit. This paper presents one more sophisticated approach from the traditional biasing circuits used so far in LDMOS DVB-T amplifiers. It utilizes a microprocessor control technology, providing stability in topologies where IDQ must be perfectly accurate.

Keywords: Amplifier, DVB-T, LDMOS, MOSFETS.

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Authors: Vijay Gajanan Neve, Pallavi V. Pullawar, G. M. Dhole

Abstract:

Modern industrial processes are based on a large amount of electronic devices such as programmable logic controllers and adjustable speed drives. Unfortunately, electronic devices are sensitive to disturbances, and thus, industrial loads become less tolerant to power quality problems such as sags, swells, and harmonics. Voltage sags are an important power quality problem. In this paper proposed a new configuration of Static Var Compensator (SVC) considering three different conditions named as topologies and Booster transformer with fuzzy logic based controller, capable of compensating for power quality problems associated with voltage sags and maintaining a prescribed level of voltage profile. Fuzzy logic controller is designed to achieve the firing angles for SVC such that it maintains voltage profile. The online monitoring system for voltage sag mitigation in the laboratory using the hardware is used. The results are presented from the performance of each topology and Booster transformer considered in this paper.

Keywords: Booster Transformer, Fuzzy logic, Static Var Compensator, Voltage sag.

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Authors: Davide Pierattoni, Ivan Macor, Pier Luca Montessoro

Abstract:

In the recent years multimedia traffic and in particular VoIP services are growing dramatically. We present a new algorithm to control the resource utilization and to optimize the voice codec selection during SIP call setup on behalf of the traffic condition estimated on the network path. The most suitable methodologies and the tools that perform realtime evaluation of the available bandwidth on a network path have been integrated with our proposed algorithm: this selects the best codec for a VoIP call in function of the instantaneous available bandwidth on the path. The algorithm does not require any explicit feedback from the network, and this makes it easily deployable over the Internet. We have also performed intensive tests on real network scenarios with a software prototype, verifying the algorithm efficiency with different network topologies and traffic patterns between two SIP PBXs. The promising results obtained during the experimental validation of the algorithm are now the basis for the extension towards a larger set of multimedia services and the integration of our methodology with existing PBX appliances.

Keywords: Integrated voice-data communication, computernetwork performance, resource optimization.

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Authors: P.S. Prakash, S. Selvan

Abstract:

IP networks are evolving from data communication infrastructure into many real-time applications such as video conferencing, IP telephony and require stringent Quality of Service (QoS) requirements. A rudimentary issue in QoS routing is to find a path between a source-destination pair that satisfies two or more endto- end constraints and termed to be NP hard or complete. In this context, we present an algorithm Multi Constraint Path Problem Version 3 (MCPv3), where all constraints are approximated and return a feasible path in much quicker time. We present another algorithm namely Delay Coerced Multi Constrained Routing (DCMCR) where coerce one constraint and approximate the remaining constraints. Our algorithm returns a feasible path, if exists, in polynomial time between a source-destination pair whose first weight satisfied by the first constraint and every other weight is bounded by remaining constraints by a predefined approximation factor (a). We present our experimental results with different topologies and network conditions.

Keywords: Routing, Quality-of-Service (QoS), additive constraints, shortest path, delay coercion.

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Authors: Thomas Canhao Xu, Bo Yang, Alexander Wei Yin, Pasi Liljeberg, Hannu Tenhunen

Abstract:

With the increasing number of on-chip components and the critical requirement for processing power, Chip Multiprocessor (CMP) has gained wide acceptance in both academia and industry during the last decade. However, the conventional bus-based onchip communication schemes suffer from very high communication delay and low scalability in large scale systems. Network-on-Chip (NoC) has been proposed to solve the bottleneck of parallel onchip communications by applying different network topologies which separate the communication phase from the computation phase. Observing that the memory bandwidth of the communication between on-chip components and off-chip memory has become a critical problem even in NoC based systems, in this paper, we propose a novel 3D NoC with on-chip Dynamic Random Access Memory (DRAM) in which different layers are dedicated to different functionalities such as processors, cache or memory. Results show that, by using our proposed architecture, average link utilization has reduced by 10.25% for SPLASH-2 workloads. Our proposed design costs 1.12% less execution cycles than the traditional design on average.

Keywords: 3D integration, network-on-chip, memory-on-chip, DRAM, chip multiprocessor.

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