Search results for: bit interleaved parity
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 47

Search results for: bit interleaved parity

47 BIP-Based Alarm Declaration and Clearing in SONET Networks Employing Automatic Protection Switching

Authors: Vitalice K. Oduol, C. Ardil

Abstract:

The paper examines the performance of bit-interleaved parity (BIP) methods in error rate monitoring, and in declaration and clearing of alarms in those transport networks that employ automatic protection switching (APS). The BIP-based error rate monitoring is attractive for its simplicity and ease of implementation. The BIP-based results are compared with exact results and are found to declare the alarms too late, and to clear the alarms too early. It is concluded that the standards development and systems implementation should take into account the fact of early clearing and late declaration of alarms. The window parameters defining the detection and clearing thresholds should be set so as to build sufficient hysteresis into the system to ensure that BIP-based implementations yield acceptable performance results.

Keywords: Automatic protection switching, bit interleaved parity, excessive bit error rate

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46 Analysis and Simulation of Automotive Interleaved Buck Converter

Authors: Mohamed. A. Shrud, Ahmad H. Kharaz, Ahmed. S. Ashur, Ahmed Faris, Mustafa Benamar

Abstract:

This paper will focus on modeling, analysis and simulation of a 42V/14V dc/dc converter based architecture. This architecture is considered to be technically a viable solution for automotive dual-voltage power system for passenger car in the near further. An interleaved dc/dc converter system is chosen for the automotive converter topology due to its advantages regarding filter reduction, dynamic response, and power management. Presented herein, is a model based on one kilowatt interleaved six-phase buck converter designed to operate in a Discontinuous Conduction Mode (DCM). The control strategy of the converter is based on a voltagemode- controlled Pulse Width Modulation (PWM) with a Proportional-Integral-Derivative (PID). The effectiveness of the interleaved step-down converter is verified through simulation results using control-oriented simulator, MatLab/Simulink.

Keywords: Automotive, dc-to-dc power modules, design, interleaved, Matlab\Simulink and PID control.

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45 Analysis and Experimentation of Interleaved Boost Converter with Ripple Steering for Power Factor Correction

Authors: A. Inba Rexy, R. Seyezhai

Abstract:

Through the fast growing technologies, design of power factor correction (PFC) circuit is facing several challenges. In this paper, a two-phase interleaved boost converter with ripple steering technique is proposed. Among the various topologies, Interleaved Boost converter (IBC) is considered as superior due to enriched performance, lower ripple content, compact weight and size. A thorough investigation is presented here for the proposed topology. Simulation study for the IBC has been carried out using MATLAB/SIMULINK. Theoretical analysis and hardware prototype has been performed to validate the results.

Keywords: Interleaved Boost Converter (IBC), Power Factor Correction (PFC), Ripple Steering Technique, Ripple, and Simulation.

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44 Calibration of Time-Skew Error in a M-Channel Time-Interleaved Analog-to-Digital Converter

Authors: Yu-Sheng Lee, Qi An

Abstract:

Offset mismatch, gain mismatch, and time-skew error between time-interleaved channels limit the performance of time-interleaved analog-to-digital converters (TIADC). This paper focused on the time-skew error. A new technique for calibrating time-skew error in M-channels TIADC is described, and simulation results are also presented.

Keywords: Calibration, time-skew error, time-interleavedanalog-to-digital converters.

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43 Modeling and Simulation of Two-Phase Interleaved Boost Converter Using Open-Source Software Scilab/Xcos

Authors: Yin Yin Phyo, Tun Lin Naing

Abstract:

This paper investigated the simulation of two-phase interleaved boost converter (IBC) with free and open-source software Scilab/Xcos. By using interleaved method, it can reduce current stress on components, components size, input current ripple and output voltage ripple. The required mathematical model is obtained from the equivalent circuit of its different four modes of operation for simulation. The equivalent circuits are considered in continuous conduction mode (CCM). The average values of the system variables are derived from the state-space equation to find the equilibrium point. Scilab is now becoming more and more popular among students, engineers and scientists because it is open-source software and free of charge. It gives a great convenience because it has powerful computation and simulation function. The waveforms of output voltage, input current and inductors current are obtained by using Scilab/Xcos.

Keywords: Two-phase boost converter, continuous conduction mode, free and open-source, interleaved method, dynamic simulation.

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42 Implementation the Average Input Current Mode Control of Two-Phase Interleaved Boost Converter Using Low-Cost Microcontroller

Authors: Yin Yin Phyo, Tun Lin Naing

Abstract:

In this paper, the average input current mode control is proposed for two-phase interleaved boost converter with two separate input inductors operating in continuous conduction mode (CCM). The required mathematical model is obtained from the equivalent circuits of its different four modes of operation. The small ripple approximation is derived to find the transfer functions from dynamic model using switching function. In average input current mode control, the inner current loop and outer voltage loop are designed with PI controller using bode analysis. Anti-windup structure is applied for PI controllers in control system. Moreover, the simulation work is carried out by MATLAB/Simulink. And, the hardware prototype is implemented by using low-cost microcontroller Arduino Nano. Finally, the laboratory prototype, available from the local market, is constructed to validate the mathematical model. The results show that the output voltage response is the faster rise time and settling time with acceptable overshoot.

Keywords: Average input current mode control, interleaved boost converter, low-cost microcontroller, PI controller, switching function.

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41 Performance Evaluation of Low Density Parity Check Codes

Authors: Othman O. Khalifa, Sheroz khan, Mohamad Zaid, Muhamad Nawawi

Abstract:

This paper mainly about the study on one of the widely used error correcting codes that is Low parity check Codes (LDPC). In this paper, the Regular LDPC code has been discussed The LDPC codes explained in this paper is about the Regular Binary LDPC codes or the Gallager.

Keywords: LDPC, channel coding.

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40 Nonlinear and Asymmetric Adjustment to Purchasing Power Parity in East-Asian Countries

Authors: Wen-Chi Liu

Abstract:

This study applies a simple and powerful nonlinear unit root test to test the validity of long-run purchasing power parity (PPP)  in a sample of 10 East-Asian countries (i.e., China, Hong Kong,  Indonesia, Japan, Korea, Malaysia, Philippines, Singapore, Taiwan  and Thailand) over the period of March 1985 to September 2008. The empirical results indicate that PPP holds true for half of these 10  East-Asian countries under study, and the adjustment toward PPP is found to be nonlinear and in an asymmetric way. 

 

Keywords: Purchasing Power Parity, East-Asian Countries, Nonlinear Unit Root Test, Asymmetry.

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39 Design and Optimization of Parity Generator and Parity Checker Based On Quantum-dot Cellular Automata

Authors: Santanu Santra, Utpal Roy

Abstract:

Quantum-dot Cellular Automata (QCA) is one of the most substitute emerging nanotechnologies for electronic circuits, because of lower power consumption, higher speed and smaller size in comparison with CMOS technology. The basic devices, a Quantum-dot cell can be used to implement logic gates and wires. As it is the fundamental building block on nanotechnology circuits. By applying XOR gate the hardware requirements for a QCA circuit can be decrease and circuits can be simpler in terms of level, delay and cell count. This article present a modest approach for implementing novel optimized XOR gate, which can be applied to design many variants of complex QCA circuits. Proposed XOR gate is simple in structure and powerful in terms of implementing any digital circuits. In order to verify the functionality of the proposed design some complex implementation of parity generator and parity checker circuits are proposed and simulating by QCA Designer tool and compare with some most recent design. Simulation results and physical relations confirm its usefulness in implementing every digital circuit.

Keywords: Clock, CMOS technology, Logic gates, QCA Designer, Quantum-dot Cellular Automata (QCA).

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38 Design of Parity-Preserving Reversible Logic Signed Array Multipliers

Authors: Mojtaba Valinataj

Abstract:

Reversible logic as a new favorable design domain can be used for various fields especially creating quantum computers because of its speed and intangible power consumption. However, its susceptibility to a variety of environmental effects may lead to yield the incorrect results. In this paper, because of the importance of multiplication operation in various computing systems, some novel reversible logic array multipliers are proposed with error detection capability by incorporating the parity-preserving gates. The new designs are presented for two main parts of array multipliers, partial product generation and multi-operand addition, by exploiting the new arrangements of existing gates, which results in two signed parity-preserving array multipliers. The experimental results reveal that the best proposed 4×4 multiplier in this paper reaches 12%, 24%, and 26% enhancements in the number of constant inputs, number of required gates, and quantum cost, respectively, compared to previous design. Moreover, the best proposed design is generalized for n×n multipliers with general formulations to estimate the main reversible logic criteria as the functions of the multiplier size.

Keywords: Array multipliers, Baugh-Wooley method, error detection, parity-preserving gates, quantum computers, reversible logic.

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37 MMSE Based Beamforming for Chip Interleaved CDMA in Aeronautical Mobile Radio Channel

Authors: Sherif K. El Dyasti, Esam A. Hagras, Adel E. El-Hennawy

Abstract:

This paper addresses the performance of antenna array beamforming on Chip-Interleaved Code Division Multiple Access (CI_CDMA) system based on Minimum Mean Square Error (MMSE) detector in aeronautical mobile radio channel. Multipath fading, Doppler shifts caused by the speed of the aircraft, and Multiple Access Interference (MAI) are the most important reasons that affect and reduce the performance of aeronautical system. In this paper we suggested the CI-CDMA with antenna array to combat this fading and improve the bit error rate (BER) performance. We further evaluate the performance of the proposed system in the four standard scenarios in aeronautical mobile radio channel.

Keywords: Aeronautical Channel, CI-CDMA, Beamforming.

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36 Decoder Design for a New Single Error Correcting/Double Error Detecting Code

Authors: M. T. Anwar, P. K. Lala, P. Thenappan

Abstract:

This paper presents the decoder design for the single error correcting and double error detecting code proposed by the authors in an earlier paper. The speed of error detection and correction of a code is largely dependent upon the associated encoder and decoder circuits. The complexity and the speed of such circuits are determined by the number of 1?s in the parity check matrix (PCM). The number of 1?s in the parity check matrix for the code proposed by the authors are fewer than in any currently known single error correcting/double error detecting code. This results in simplified encoding and decoding circuitry for error detection and correction.

Keywords: Decoder, Hsiao code, Parity Check Matrix, Syndrome Pattern.

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35 DC-to-DC Converters for Low-Voltage High-Power Renewable Energy Systems

Authors: Abdar Ali, Rizwan Ullah, Zahid Ullah

Abstract:

This paper focuses on the study of DC-to-DC converters, which are suitable for low-voltage high-power applications. The output voltages generated by renewable energy sources such as photovoltaic arrays and fuel cell stacks are generally low and required to be increased to high voltage levels. Development of DC-to-DC converters, which provide high step-up voltage conversion ratios with high efficiencies and low voltage stresses, is one of the main issues in the development of renewable energy systems. A procedure for three converters−conventional DC-to-DC converter, interleaved boost converter, and isolated flyback based converter, is illustrated for a given set of specifications. The selection among the converters for the given application is based on the voltage conversion ratio, efficiency, and voltage stresses.

Keywords: Flyback converter, interleaved boost, photovoltaic array, fuel cell, switch stress, voltage conversion ratio, renewable energy.

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34 The Relationship between Sheep Management and Lamb Mortality

Authors: T. M. Mousa-Balabel

Abstract:

This study was carried out to investigate lamb mortalities relating to ewes' breed and some managemental factors on 250 pregnant ewes (190-Rahmani, 30-Ossimi and 30-Romanov) at Mehallet Mousa, Animal Production Research Station, Kafr El- Sheikh Province, Egypt. These animals divided into five groups according to the managemental factors used. The results revealed that the lamb mortality was higher in Ossimi breed and lower in Romanov one. In addition, the highest lamb mortality occurred among lambs for unsupplemented ewes, for those had body condition score two and for lambs which born outdoor. Moreover, the lamb survivability was increased by the parity of ewes. From this study it can be concluded that the lamb mortality depends on ewes' body condition score, parity, lambing system (indoor or outdoor), nutrition during pregnancy period and selected breed. In addition, the most important period for lamb survival is the first week of age.

Keywords: lamb mortality, sheep breeds, sheep management, sheep parity.

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33 Fully Parameterizable FPGA based Crypto-Accelerator

Authors: Iqbalur Rahman, Miftahur Rahman, Abul L Haque, Mostafizur Rahman,

Abstract:

In this paper, RSA encryption algorithm and its hardware implementation in Xilinx-s Virtex Field Programmable Gate Arrays (FPGA) is analyzed. The issues of scalability, flexible performance, and silicon efficiency for the hardware acceleration of public key crypto systems are being explored in the present work. Using techniques based on the interleaved math for exponentiation, the proposed RSA calculation architecture is compared to existing FPGA-based solutions for speed, FPGA utilization, and scalability. The paper covers the RSA encryption algorithm, interleaved multiplication, Miller Rabin algorithm for primality test, extended Euclidean math, basic FPGA technology, and the implementation details of the proposed RSA calculation architecture. Performance of several alternative hardware architectures is discussed and compared. Finally, conclusion is drawn, highlighting the advantages of a fully flexible & parameterized design.

Keywords: Crypto Accelerator, FPGA, Public Key Cryptography, RSA.

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32 Lowering Error Floors by Concatenation of Low-Density Parity-Check and Array Code

Authors: Cinna Soltanpur, Mohammad Ghamari, Behzad Momahed Heravi, Fatemeh Zare

Abstract:

Low-density parity-check (LDPC) codes have been shown to deliver capacity approaching performance; however, problematic graphical structures (e.g. trapping sets) in the Tanner graph of some LDPC codes can cause high error floors in bit-error-ratio (BER) performance under conventional sum-product algorithm (SPA). This paper presents a serial concatenation scheme to avoid the trapping sets and to lower the error floors of LDPC code. The outer code in the proposed concatenation is the LDPC, and the inner code is a high rate array code. This approach applies an interactive hybrid process between the BCJR decoding for the array code and the SPA for the LDPC code together with bit-pinning and bit-flipping techniques. Margulis code of size (2640, 1320) has been used for the simulation and it has been shown that the proposed concatenation and decoding scheme can considerably improve the error floor performance with minimal rate loss.

Keywords: Concatenated coding, low–density parity–check codes, array code, error floors.

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31 Low Energy Method for Data Delivery in Ubiquitous Network

Authors: Tae Kyung Kim, Hee Suk Seo

Abstract:

Recent advances in wireless sensor networks have led to many routing methods designed for energy-efficiency in wireless sensor networks. Despite that many routing methods have been proposed in USN, a single routing method cannot be energy-efficient if the environment of the ubiquitous sensor network varies. We present the controlling network access to various hosts and the services they offer, rather than on securing them one by one with a network security model. When ubiquitous sensor networks are deployed in hostile environments, an adversary may compromise some sensor nodes and use them to inject false sensing reports. False reports can lead to not only false alarms but also the depletion of limited energy resource in battery powered networks. The interleaved hop-by-hop authentication scheme detects such false reports through interleaved authentication. This paper presents a LMDD (Low energy method for data delivery) algorithm that provides energy-efficiency by dynamically changing protocols installed at the sensor nodes. The algorithm changes protocols based on the output of the fuzzy logic which is the fitness level of the protocols for the environment.

Keywords: Data delivery, routing, simulation.

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30 Image Transmission in Low-Power Networks in Mobile Communications Channel

Authors: M. A. M. El-Bendary, H. Kazimian, A. E. Abo-El-azm, N. A. El-Fishawy, F. El-Samie, F. Shawki

Abstract:

This paper studies a vital issue in wireless communications, which is the transmission of images over Wireless Personal Area Networks (WPANs) through the Bluetooth network. It presents a simple method to improve the efficiency of error control code of old Bluetooth versions over mobile WPANs through Interleaved Error Control Code (IECC) technique. The encoded packets are interleaved by simple block interleaver. Also, the paper presents a chaotic interleaving scheme as a tool against bursts of errors which depends on the chaotic Baker map. Also, the paper proposes using the chaotic interleaver instead of traditional block interleaver with Forward Error Control (FEC) scheme. A comparison study between the proposed and standard techniques for image transmission over a correlated fading channel is presented. Simulation results reveal the superiority of the proposed chaotic interleaving scheme to other schemes. Also, the superiority of FEC with proposed chaotic interleaver to the conventional interleavers with enhancing the security level with chaotic interleaving packetby- packet basis.

Keywords: Mobile Bluetooth terminals, WPANs, Jackes' model, Interleaving technique, chaotic interleaver

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29 An Efficient Architecture for Interleaved Modular Multiplication

Authors: Ahmad M. Abdel Fattah, Ayman M. Bahaa El-Din, Hossam M.A. Fahmy

Abstract:

Modular multiplication is the basic operation in most public key cryptosystems, such as RSA, DSA, ECC, and DH key exchange. Unfortunately, very large operands (in order of 1024 or 2048 bits) must be used to provide sufficient security strength. The use of such big numbers dramatically slows down the whole cipher system, especially when running on embedded processors. So far, customized hardware accelerators - developed on FPGAs or ASICs - were the best choice for accelerating modular multiplication in embedded environments. On the other hand, many algorithms have been developed to speed up such operations. Examples are the Montgomery modular multiplication and the interleaved modular multiplication algorithms. Combining both customized hardware with an efficient algorithm is expected to provide a much faster cipher system. This paper introduces an enhanced architecture for computing the modular multiplication of two large numbers X and Y modulo a given modulus M. The proposed design is compared with three previous architectures depending on carry save adders and look up tables. Look up tables should be loaded with a set of pre-computed values. Our proposed architecture uses the same carry save addition, but replaces both look up tables and pre-computations with an enhanced version of sign detection techniques. The proposed architecture supports higher frequencies than other architectures. It also has a better overall absolute time for a single operation.

Keywords: Montgomery multiplication, modular multiplication, efficient architecture, FPGA, RSA

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28 Performance Comparison and Analysis of Serial Concatenated Convolutional Codes

Authors: Dongwon Lee, Eon Kyeong Joo

Abstract:

In this paper, the performance of three types of serial concatenated convolutional codes (SCCC) is compared and analyzed in additive white Gaussian noise (AWGN) channel. In Type I, only the parity bits of outer encoder are passed to inner encoder. In Type II and Type III, both the information bits and the parity bits of outer encoder are transferred to inner encoder. As results of simulation, Type I shows the best bit error rate (BER) performance at low signal-to-noise ratio (SNR). On the other hand, Type III shows the best BER performance at high SNR in AWGN channel. The simulation results are analyzed using the distance spectrum.

Keywords: Distance spectrum, MAP algorithm, SCCC.

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27 Optimization of Quantization in Higher Order Modulations for LDPC-Coded Systems

Authors: M.Sushanth Babu, P.Krishna, U.Venu, M.Ranjith

Abstract:

In this paper, we evaluate the choice of suitable quantization characteristics for both the decoder messages and the received samples in Low Density Parity Check (LDPC) coded systems using M-QAM (Quadrature Amplitude Modulation) schemes. The analysis involves the demapper block that provides initial likelihood values for the decoder, by relating its quantization strategy of the decoder. A mapping strategy refers to the grouping of bits within a codeword, where each m-bit group is used to select a 2m-ary signal in accordance with the signal labels. Further we evaluate the system with mapping strategies like Consecutive-Bit (CB) and Bit-Reliability (BR). A new demapper version, based on approximate expressions, is also presented to yield a low complexity hardware implementation.

Keywords: Low Density parity Check, Mapping, Demapping, Quantization, Quadrature Amplitude Modulation

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26 Enhancing the Error-Correcting Performance of LDPC Codes through an Efficient Use of Decoding Iterations

Authors: Insah Bhurtah, P. Clarel Catherine, K. M. Sunjiv Soyjaudah

Abstract:

The decoding of Low-Density Parity-Check (LDPC) codes is operated over a redundant structure known as the bipartite graph, meaning that the full set of bit nodes is not absolutely necessary for decoder convergence. In 2008, Soyjaudah and Catherine designed a recovery algorithm for LDPC codes based on this assumption and showed that the error-correcting performance of their codes outperformed conventional LDPC Codes. In this work, the use of the recovery algorithm is further explored to test the performance of LDPC codes while the number of iterations is progressively increased. For experiments conducted with small blocklengths of up to 800 bits and number of iterations of up to 2000, the results interestingly demonstrate that contrary to conventional wisdom, the error-correcting performance keeps increasing with increasing number of iterations.

Keywords: Error-correcting codes, information theory, low-density parity-check codes, sum-product algorithm.

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25 Error Detection and Correction for Onboard Satellite Computers Using Hamming Code

Authors: Rafsan Al Mamun, Md. Motaharul Islam, Rabana Tajrin, Nabiha Noor, Shafinaz Qader

Abstract:

In an attempt to enrich the lives of billions of people by providing proper information, security and a way of communicating with others, the need for efficient and improved satellites is constantly growing. Thus, there is an increasing demand for better error detection and correction (EDAC) schemes, which are capable of protecting the data onboard the satellites. The paper is aimed towards detecting and correcting such errors using a special algorithm called the Hamming Code, which uses the concept of parity and parity bits to prevent single-bit errors onboard a satellite in Low Earth Orbit. This paper focuses on the study of Low Earth Orbit satellites and the process of generating the Hamming Code matrix to be used for EDAC using computer programs. The most effective version of Hamming Code generated was the Hamming (16, 11, 4) version using MATLAB, and the paper compares this particular scheme with other EDAC mechanisms, including other versions of Hamming Codes and Cyclic Redundancy Check (CRC), and the limitations of this scheme. This particular version of the Hamming Code guarantees single-bit error corrections as well as double-bit error detections. Furthermore, this version of Hamming Code has proved to be fast with a checking time of 5.669 nanoseconds, that has a relatively higher code rate and lower bit overhead compared to the other versions and can detect a greater percentage of errors per length of code than other EDAC schemes with similar capabilities. In conclusion, with the proper implementation of the system, it is quite possible to ensure a relatively uncorrupted satellite storage system.

Keywords: Bit-flips, Hamming code, low earth orbit, parity bits, satellite, single error upset.

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24 Pure Scalar Equilibria for Normal-Form Games

Authors: H. W. Corley

Abstract:

A scalar equilibrium (SE) is an alternative type of equilibrium in pure strategies for an n-person normal-form game G. It is defined using optimization techniques to obtain a pure strategy for each player of G by maximizing an appropriate utility function over the acceptable joint actions. The players’ actions are determined by the choice of the utility function. Such a utility function could be agreed upon by the players or chosen by an arbitrator. An SE is an equilibrium since no players of G can increase the value of this utility function by changing their strategies. SEs are formally defined, and examples are given. In a greedy SE, the goal is to assign actions to the players giving them the largest individual payoffs jointly possible. In a weighted SE, each player is assigned weights modeling the degree to which he helps every player, including himself, achieve as large a payoff as jointly possible. In a compromise SE, each player wants a fair payoff for a reasonable interpretation of fairness. In a parity SE, the players want their payoffs to be as nearly equal as jointly possible. Finally, a satisficing SE achieves a personal target payoff value for each player. The vector payoffs associated with each of these SEs are shown to be Pareto optimal among all such acceptable vectors, as well as computationally tractable.

Keywords: Compromise equilibrium, greedy equilibrium, normal-form game, parity equilibrium, pure strategies, satisficing equilibrium, scalar equilibria, utility function, weighted equilibrium.

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23 Comparison between Separable and Irreducible Goppa Code in McEliece Cryptosystem

Authors: Thuraya M. Qaradaghi, Newroz N. Abdulrazaq

Abstract:

The McEliece cryptosystem is an asymmetric type of cryptography based on error correction code. The classical McEliece used irreducible binary Goppa code which considered unbreakable until now especially with parameter [1024, 524, and 101], but it is suffering from large public key matrix which leads to be difficult to be used practically. In this work Irreducible and Separable Goppa codes have been introduced. The Irreducible and Separable Goppa codes used are with flexible parameters and dynamic error vectors. A Comparison between Separable and Irreducible Goppa code in McEliece Cryptosystem has been done. For encryption stage, to get better result for comparison, two types of testing have been chosen; in the first one the random message is constant while the parameters of Goppa code have been changed. But for the second test, the parameters of Goppa code are constant (m=8 and t=10) while the random message have been changed. The results show that the time needed to calculate parity check matrix in separable are higher than the one for irreducible McEliece cryptosystem, which is considered expected results due to calculate extra parity check matrix in decryption process for g2(z) in separable type, and the time needed to execute error locator in decryption stage in separable type is better than the time needed to calculate it in irreducible type. The proposed implementation has been done by Visual studio C#.

Keywords: McEliece cryptosystem, Goppa code, separable, irreducible.

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22 Influence of κ-Casein Genotype on Milk Productivity of Latvia Local Dairy Breeds

Authors: S. Petrovska, D. Jonkus, D. Smiltiņa

Abstract:

κ-casein is one of milk proteins which are very important for milk processing. Genotypes of κ-casein affect milk yield, fat, and protein content. The main factors which affect local Latvian dairy breed milk yield and composition are analyzed in research. Data were collected from 88 Latvian brown and 82 Latvian blue cows in 2015. AA genotype was 0.557 in Latvian brown and 0.232 in Latvian blue breed. BB genotype was 0.034 in Latvian brown and 0.207 in Latvian blue breed. Highest milk yield was observed in Latvian brown (5131.2 ± 172.01 kg), significantly high fat content and fat yield also was in Latvian brown (p < 0.05). Significant differences between κ-casein genotypes were not found in Latvian brown, but highest milk yield (5057 ± 130.23 kg), protein content (3.42 ± 0.03%), and protein yield (171.9 ± 4.34 kg) were with AB genotype. Significantly high fat content was observed in Latvian blue breed with BB genotype (4.29 ± 0.17%) compared with AA genotypes (3.42 ± 0.19). Similar tendency was found in protein content – 3.27 ± 0.16% with BB genotype and 2.59 ± 0.16% with AA genotype (p < 0.05). Milk yield increases by increasing parity. We did not obtain major tendency of changes of milk fat and protein content according parity.

Keywords: κ-casein, polymorphism, dairy cows, milk productivity.

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21 A Novel Digital Calibration Technique for Gain and Offset Mismatch in TIΣΔ ADCs

Authors: Ali Beydoun, Van-Tam Nguyen, Patrick Loumeau

Abstract:

Time interleaved sigma-delta (TIΣΔ) architecture is a potential candidate for high bandwidth analog to digital converters (ADC) which remains a bottleneck for software and cognitive radio receivers. However, the performance of the TIΣΔ architecture is limited by the unavoidable gain and offset mismatches resulting from the manufacturing process. This paper presents a novel digital calibration method to compensate the gain and offset mismatch effect. The proposed method takes advantage of the reconstruction digital signal processing on each channel and requires only few logic components for implementation. The run time calibration is estimated to 10 and 15 clock cycles for offset cancellation and gain mismatch calibration respectively.

Keywords: sigma-delta, calibration, gain and offset mismatches, analog-to-digital conversion, time-interleaving.

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20 Assessment of Predictive Confounders for the Prevalence of Breast Cancer among Iraqi Population: A Retrospective Study from Baghdad, Iraq

Authors: Nadia H. Mohammed, Anmar Al-Taie, Fadia H. Al-Sultany

Abstract:

Although breast cancer prevalence continues to increase, mortality has been decreasing as a result of early detection and improvement in adjuvant systemic therapy. Nevertheless, this disease required further efforts to understand and identify the associated potential risk factors that could play a role in the prevalence of this malignancy among Iraqi women. The objective of this study was to assess the perception of certain predictive risk factors on the prevalence of breast cancer types among a sample of Iraqi women diagnosed with breast cancer. This was a retrospective observational study carried out at National Cancer Research Center in College of Medicine, Baghdad University from November 2017 to January 2018. Data of 100 patients with breast cancer whose biopsies examined in the National Cancer Research Center were included in this study. Data were collected to structure a detailed assessment regarding the patients’ demographic, medical and cancer records. The majority of study participants (94%) suffered from ductal breast cancer with mean age 49.57 years. Among those women, 48.9% were obese with body mass index (BMI) 35 kg/m2. 68.1% of them had positive family history of breast cancer and 66% had low parity. 40.4% had stage II ductal breast cancer followed by 25.5% with stage III. It was found that 59.6% and 68.1% had positive oestrogen receptor sensitivity and positive human epidermal growth factor (HER2/neu) receptor sensitivity respectively. In regard to the impact of prediction of certain variables on the incidence of ductal breast cancer, positive family history of breast cancer (P < 0.0001), low parity (P< 0.0001), stage I and II breast cancer (P = 0.02) and positive HER2/neu status (P < 0.0001) were significant predictive factors among the study participants. The results from this study provide relevant evidence for a significant positive and potential association between certain risk factors and the prevalence of breast cancer among Iraqi women.

Keywords: Ductal breast cancer, hormone sensitivity, Iraq, risk factors.

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19 Performance Analysis of HSDPA Systems using Low-Density Parity-Check (LDPC)Coding as Compared to Turbo Coding

Authors: K. Anitha Sheela, J. Tarun Kumar

Abstract:

HSDPA is a new feature which is introduced in Release-5 specifications of the 3GPP WCDMA/UTRA standard to realize higher speed data rate together with lower round-trip times. Moreover, the HSDPA concept offers outstanding improvement of packet throughput and also significantly reduces the packet call transfer delay as compared to Release -99 DSCH. Till now the HSDPA system uses turbo coding which is the best coding technique to achieve the Shannon limit. However, the main drawbacks of turbo coding are high decoding complexity and high latency which makes it unsuitable for some applications like satellite communications, since the transmission distance itself introduces latency due to limited speed of light. Hence in this paper it is proposed to use LDPC coding in place of Turbo coding for HSDPA system which decreases the latency and decoding complexity. But LDPC coding increases the Encoding complexity. Though the complexity of transmitter increases at NodeB, the End user is at an advantage in terms of receiver complexity and Bit- error rate. In this paper LDPC Encoder is implemented using “sparse parity check matrix" H to generate a codeword at Encoder and “Belief Propagation algorithm "for LDPC decoding .Simulation results shows that in LDPC coding the BER suddenly drops as the number of iterations increase with a small increase in Eb/No. Which is not possible in Turbo coding. Also same BER was achieved using less number of iterations and hence the latency and receiver complexity has decreased for LDPC coding. HSDPA increases the downlink data rate within a cell to a theoretical maximum of 14Mbps, with 2Mbps on the uplink. The changes that HSDPA enables includes better quality, more reliable and more robust data services. In other words, while realistic data rates are only a few Mbps, the actual quality and number of users achieved will improve significantly.

Keywords: AMC, HSDPA, LDPC, WCDMA, 3GPP.

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18 Parallel Vector Processing Using Multi Level Orbital DATA

Authors: Nagi Mekhiel

Abstract:

Many applications use vector operations by applying single instruction to multiple data that map to different locations in conventional memory. Transferring data from memory is limited by access latency and bandwidth affecting the performance gain of vector processing. We present a memory system that makes all of its content available to processors in time so that processors need not to access the memory, we force each location to be available to all processors at a specific time. The data move in different orbits to become available to other processors in higher orbits at different time. We use this memory to apply parallel vector operations to data streams at first orbit level. Data processed in the first level move to upper orbit one data element at a time, allowing a processor in that orbit to apply another vector operation to deal with serial code limitations inherited in all parallel applications and interleaved it with lower level vector operations.

Keywords: Memory organization, parallel processors, serial code, vector processing.

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