Search results for: Stack cache

Authors: Abdulrahman K. Alshegaifi, Chun-Hsi Huang

Abstract:

Treating data based on its location in memory has received much attention in recent years due to its different properties, which offer important aspects for cache utilization. Stack data and non-stack data may interfere with each other’s locality in the data cache. One of the important aspects of stack data is that it has high spatial and temporal locality. In this work, we simulate non-unified cache design that split data cache into stack and non-stack caches in order to maintain stack data and non-stack data separate in different caches. We observe that the overall hit rate of non-unified cache design is sensitive to the size of non-stack cache. Then, we investigate the appropriate size and associativity for stack cache to achieve high hit ratio especially when over 99% of accesses are directed to stack cache. The result shows that on average more than 99% of stack cache accuracy is achieved by using 2KB of capacity and 1-way associativity. Further, we analyze the improvement in hit rate when adding small, fixed, size of stack cache at level1 to unified cache architecture. The result shows that the overall hit rate of unified cache design with adding 1KB of stack cache is improved by approximately, on average, 3.9% for Rijndael benchmark. The stack cache is simulated by using SimpleScalar toolset.

Keywords: Hit rate, Locality of program, Stack cache, and Stack data.

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Authors: Hassan Ghasemzadeh, Sepideh Mazrouee, Hassan Goldani Moghaddam, Hamid Shojaei, Mohammad Reza Kakoee

Abstract:

Block replacement algorithms to increase hit ratio have been extensively used in cache memory management. Among basic replacement schemes, LRU and FIFO have been shown to be effective replacement algorithms in terms of hit rates. In this paper, we introduce a flexible stack-based circuit which can be employed in hardware implementation of both LRU and FIFO policies. We propose a simple and efficient architecture such that stack-based replacement algorithms can be implemented without the drawbacks of the traditional architectures. The stack is modular and hence, a set of stack rows can be cascaded depending on the number of blocks in each cache set. Our circuit can be implemented in conjunction with the cache controller and static/dynamic memories to form a cache system. Experimental results exhibit that our proposed circuit provides an average value of 26% improvement in storage bits and its maximum operating frequency is increased by a factor of two

Keywords: Cache Memory, Replacement Algorithms, LeastRecently Used Algorithm, First In First Out Algorithm.

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Authors: Guowei Hou, Lixin Yu, Wei Zhuang, Hui Qin, Xue Yang

Abstract:

Formal verification is proposed to ensure the correctness of the design and make functional verification more efficient. As cache plays a vital role in the design of System on Chip (SoC), and cache with Memory Management Unit (MMU) and cache memory unit makes the state space too large for simulation to verify, then a formal verification is presented for such system design. In the paper, a formal model checking verification flow is suggested and a new cache memory model which is called “exhaustive search model” is proposed. Instead of using large size ram to denote the whole cache memory, exhaustive search model employs just two cache blocks. For cache system contains data cache (Dcache) and instruction cache (Icache), Dcache memory model and Icache memory model are established separately using the same mechanism. At last, the novel model is employed to the verification of a cache which is module of a custom-built SoC system that has been applied in practical, and the result shows that the cache system is verified correctly using the exhaustive search model, and it makes the verification much more manageable and flexible.

Keywords: Cache system, formal verification, novel model, System on Chip (SoC).

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Authors: Jasim. A. Ghaeb

Abstract:

A high performance computer includes a fast processor and millions bytes of memory. During the data processing, huge amount of information are shuffled between the memory and processor. Because of its small size and its effectiveness speed, cache has become a common feature of high performance computers. Enhancing cache performance proved to be essential in the speed up of cache-based computers. Most enhancement approaches can be classified as either software based or hardware controlled. The performance of the cache is quantified in terms of hit ratio or miss ratio. In this paper, we are optimizing the cache performance based on enhancing the cache hit ratio. The optimum cache performance is obtained by focusing on the cache hardware modification in the way to make a quick rejection to the missed line's tags from the hit-or miss comparison stage, and thus a low hit time for the wanted line in the cache is achieved. In the proposed technique which we called Even- Odd Tabulation (EOT), the cache lines come from the main memory into cache are classified in two types; even line's tags and odd line's tags depending on their Least Significant Bit (LSB). This division is exploited by EOT technique to reject the miss match line's tags in very low time compared to the time spent by the main comparator in the cache, giving an optimum hitting time for the wanted cache line. The high performance of EOT technique against the familiar mapping technique FAM is shown in the simulated results.

Keywords: Caches, Cache performance, Hit time, Cache hit ratio, Cache mapping, Cache memory.

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Authors: Aline Zeitunlian, Ramzi A. Haraty

Abstract:

Caching was suggested as a solution for reducing bandwidth utilization and minimizing query latency in mobile environments. Over the years, different caching approaches have been proposed, some relying on the server to broadcast reports periodically informing of the updated data while others allowed the clients to request for the data whenever needed. Until recently a hybrid cache consistency scheme Scalable Asynchronous Cache Consistency Scheme SACCS was proposed, which combined the two different approaches benefits- and is proved to be more efficient and scalable. Nevertheless, caching has its limitations too, due to the limited cache size and the limited bandwidth, which makes the implementation of cache replacement strategy an important aspect for improving the cache consistency algorithms. In this thesis, we proposed a new cache replacement strategy, the Least Unified Value strategy (LUV) to replace the Least Recently Used (LRU) that SACCS was based on. This paper studies the advantages and the drawbacks of the new proposed strategy, comparing it with different categories of cache replacement strategies.

Keywords: Cache consistency, hybrid algorithm, and mobileenvironments

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Authors: Sajjad Rostami-Sani, Mojtaba Valinataj, Amir-Hossein Khojir-Angasi

Abstract:

The cache has an important role in the reduction of access delay between a processor and memory in high-performance embedded systems. In these systems, the energy consumption is one of the most important concerns, and it will become more important with smaller processor feature sizes and higher frequencies. Meanwhile, the cache system dissipates a significant portion of energy compared to the other components of a processor. There are some elements that can affect the energy consumption of the cache such as replacement policy and degree of associativity. Due to these points, it can be inferred that selecting an appropriate configuration for the cache is a crucial part of designing a system. In this paper, we investigate the effect of different cache replacement policies on both cache’s performance and energy consumption. Furthermore, the impact of different Instruction Set Architectures (ISAs) on cache’s performance and energy consumption has been investigated.

Keywords: L1-cache, energy consumption, replacement policy, Instruction set architecture, multicore processor.

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Authors: Sami I. Serhan, Hamed M. Abdel-Haq

Abstract:

In this paper, an efficient technique is proposed to manage the cache memory. The proposed technique introduces some modifications on the well-known set associative mapping technique. This modification requires a little alteration in the structure of the cache memory and on the way by which it can be referenced. The proposed alteration leads to increase the set size virtually and consequently to improve the performance and the utilization of the cache memory. The current mapping techniques have accomplished good results. In fact, there are still different cases in which cache memory lines are left empty and not used, whereas two or more processes overwrite the lines of each other, instead of using those empty lines. The proposed algorithm aims at finding an efficient way to deal with such problem.

Keywords: Modified Set Associative Mapping, Locality of Reference, Miss Ratio, Hit Ratio, Cache Memory, Clustered Behavior, Index Address, Tag Field, Status Field, and Complement of Index Address.

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Authors: Nastaran Moosavi, Mohammad Mokhtari

Abstract:

Seismic inversion is a technique which has been in use for years and its main goal is to estimate and to model physical characteristics of rocks and fluids. Generally, it is a combination of seismic and well-log data. Seismic inversion can be carried out through different methods; we have conducted and compared post-stack and pre- stack seismic inversion methods on real data in one of the fields in the Persian Gulf. Pre-stack seismic inversion can transform seismic data to rock physics such as P-impedance, S-impedance and density. While post- stack seismic inversion can just estimate P-impedance. Then these parameters can be used in reservoir identification. Based on the results of inverting seismic data, a gas reservoir was detected in one of Hydrocarbon oil fields in south of Iran (Persian Gulf). By comparing post stack and pre-stack seismic inversion it can be concluded that the pre-stack seismic inversion provides a more reliable and detailed information for identification and prediction of hydrocarbon reservoirs.

Keywords: Density, P-impedance, S-impedance, post-stack seismic inversion, pre-stack seismic inversion.

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Authors: Md. Ataullah, Naveen Chauhan

Abstract:

The Address Resolution Protocol (ARP) is used by computers to map logical addresses (IP) to physical addresses (MAC). However ARP is an all trusting protocol and is stateless which makes it vulnerable to many ARP cache poisoning attacks such as Man-in-the-Middle (MITM) and Denial of service (DoS) attacks. These flaws result in security breaches thus weakening the appeal of the computer for exchange of sensitive data. In this paper we describe ARP, outline several possible ARP cache poisoning attacks and give the detailed of some attack scenarios in network having both wired and wireless hosts. We have analyzed each of proposed solutions, identify their strengths and limitations. Finally get that no solution offers a feasible solution. Hence, this paper presents an efficient and secure version of ARP that is able to cope up with all these types of attacks and is also a feasible solution. It is a stateful protocol, by storing the information of the Request frame in the ARP cache, to reduce the chances of various types of attacks in ARP. It is more efficient and secure by broadcasting ARP Reply frame in the network and storing related entries in the ARP cache each time when communication take place.

Keywords: ARP cache poisoning, MITM, DoS

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Authors: Ashly Joseph

Abstract:

In the era of digital transformation, full-stack observability has emerged as a crucial aspect of administering modern application stacks. This research paper presents the concept of full-stack observability, its significance in the context of contemporary application stacks, and the challenges posed by swiftly evolving digital environments. In addition, it describes how full-stack observability intends to provide complete visibility and actionable insights by correlating telemetry across multiple domains.

Keywords: Actionable insights, digital transformation, full-stack observability, performance metrics.

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Authors: Na Li, Samuel Simon Araya, Søren Knudsen Kær

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This study investigates the effects of operating parameters of different current density, temperature and pressure on the performance of a proton exchange membrane (PEM) water electrolysis stack. A 7-cell PEM water electrolysis stack was assembled and tested under different operation modules. The voltage change and polarization curves under different test conditions, namely current density, temperature and pressure, were recorded. Results show that higher temperature has positive effect on overall stack performance, where temperature of 80 ℃ improved the cell performance greatly. However, the cathode pressure and current density has little effect on stack performance.

Keywords: PEM electrolysis stack, current density, temperature, pressure.

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Authors: Patcharin Saechan, Isares Dhuchakallaya

Abstract:

Thermoacoustic refrigerator is a cooling device which uses the acoustic waves to produce the cooling effect. The aim of this paper is to explore the experimental and numerical feasibility of a standing-wave thermoacoustic refrigerator. The effects of the stack length, position of stack and operating frequency on the cooling performance are carried out. The circular pore stacks are tested under the atmospheric pressure. A low-cost loudspeaker is used as an acoustic driver. The results show that the location of stack installed in resonator tube has a greater effect on the cooling performance, than the stack length and operating frequency, respectively. The temperature difference across the ends of stack can be generated up to 13.7°C, and the temperature of cold-end is dropped down by 5.3°C from the ambient temperature.

Keywords: Cooling performance, Refrigerator, Standing-wave, Thermoacoustics.

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Authors: Narottam Chand

Abstract:

Wireless sensor networks (WSNs) consist of number of tiny, low cost and low power sensor nodes to monitor some physical phenomenon. The major limitation in these networks is the use of non-rechargeable battery having limited power supply. The main cause of energy consumption in such networks is communication subsystem. This paper presents an energy efficient Cluster Cooperative Caching at Sensor (C3S) based upon grid type clustering. Sensor nodes belonging to the same cluster/grid form a cooperative cache system for the node since the cost for communication with them is low both in terms of energy consumption and message exchanges. The proposed scheme uses cache admission control and utility based data replacement policy to ensure that more useful data is retained in the local cache of a node. Simulation results demonstrate that C3S scheme performs better in various performance metrics than NICoCa which is existing cooperative caching protocol for WSNs.

Keywords: Cooperative caching, cache replacement, admission control, WSN, clustering.

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Authors: Lai Xuejiang, Huang Li, Yang Yi

Abstract:

To study the potential hazards of the sudden emergency relief of flare stack, the thermal radiation and noise calculation of flare stack is carried out by using Flaresim program 2.0. Thermal radiation and noise analysis should be considered as the sudden emergency relief takes place. According to the Flaresim software simulation results, the thermal radiation and noise meet the requirement.

Keywords: Flare stack, thermal radiation, noise, safety assessment.

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Authors: Hee-Guk Chae, Bo-Bae Song, Kyoung-Il Do, Jeong-Yun Seo, Yong-Seo Koo

Abstract:

In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage.

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Authors: Sofien Chtourou, Mohamed Chtourou, Omar Hammami

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Embedded systems need to respect stringent real time constraints. Various hardware components included in such systems such as cache memories exhibit variability and therefore affect execution time. Indeed, a cache memory access from an embedded microprocessor might result in a cache hit where the data is available or a cache miss and the data need to be fetched with an additional delay from an external memory. It is therefore highly desirable to predict future memory accesses during execution in order to appropriately prefetch data without incurring delays. In this paper, we evaluate the potential of several artificial neural networks for the prediction of instruction memory addresses. Neural network have the potential to tackle the nonlinear behavior observed in memory accesses during program execution and their demonstrated numerous hardware implementation emphasize this choice over traditional forecasting techniques for their inclusion in embedded systems. However, embedded applications execute millions of instructions and therefore millions of addresses to be predicted. This very challenging problem of neural network based prediction of large time series is approached in this paper by evaluating various neural network architectures based on the recurrent neural network paradigm with pre-processing based on the Self Organizing Map (SOM) classification technique.

Keywords: Address, data set, memory, prediction, recurrentneural network.

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Authors: Tao Chen, ShiHua Liu, JiWei Zhang

Abstract:

Assembly of the proton exchange membrane fuel cells (PEMFC) has a very important influence on its performance and efficiency. The various components of PEMFC stack are usually locked and fixed by bolts. Locking bolt will cause the deformation of the bipolar plate and the other components, which will affect directly the deformation degree of the integral parts of the PEMFC as well as the performance of PEMFC. This paper focuses on the object of three-cell stack of PEMFC. Finite element simulation is used to investigate the deformation of bipolar plate caused by quantity and layout of bolts, bolt locking pressure, and bolt locking sequence, etc. Finally, we made a conclusion that the optimal combination packaging scheme was adopted to assemble the fuel cell stack. The scheme was in use of 3.8 MPa locking pressure imposed on the fuel cell stack, type Ⅱ of four locking bolts and longitudinal locking method. The scheme was obtained by comparatively analyzing the overall displacement contour of PEMFC stack, absolute displacement curve of bipolar plate along the given three paths in the Z direction and the polarization curve of fuel cell. The research results are helpful for the fuel cell stack assembly.

Keywords: Bipolar plate, deformation, finite element simulation, fuel cell, locking bolt.

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Authors: Karina Natali, Wei-Hwa Chiang

Abstract:

This study examines the stack ventilation performance of an office building located in Taipei, Taiwan. Atriums in this building act as stacks that facilitate buoyancy-driven ventilation. Computational Fluid Dynamic (CFD) simulations are used to identify interior airflow patterns, and then used these patterns to assess the building’s heat expulsion efficiency. Ambient temperatures of 20°C were adopted as the typical seasonal spring temperature range in Taipei. Further, “zero-wind” conditions are established to ensure simulation results reflected only the buoyancy effect. After checking results against neutral pressure level (NPL) level, airflow, air velocity, and indoor temperature stratification, the lower stack is modified to reduce the NPL in order to remove heat accumulated on the top floor.

Keywords: Natural ventilation, side outlet, stack effect, thermal comfort.

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Authors: P. Kaladevi, N. Giridharan

Abstract:

The system for analyzing and eliciting public grievances serves its main purpose to receive and process all sorts of complaints from the public and respond to users. Due to the more number of complaint data becomes big data which is difficult to store and process. The proposed system uses HDFS to store the big data and uses MapReduce to process the big data. The concept of cache was applied in the system to provide immediate response and timely action using big data analytics. Cache enabled big data increases the response time of the system. The unstructured data provided by the users are efficiently handled through map reduce algorithm. The processing of complaints takes place in the order of the hierarchy of the authority. The drawbacks of the traditional database system used in the existing system are set forth by our system by using Cache enabled Hadoop Distributed File System. MapReduce framework codes have the possible to leak the sensitive data through computation process. We propose a system that add noise to the output of the reduce phase to avoid signaling the presence of sensitive data. If the complaints are not processed in the ample time, then automatically it is forwarded to the higher authority. Hence it ensures assurance in processing. A copy of the filed complaint is sent as a digitally signed PDF document to the user mail id which serves as a proof. The system report serves to be an essential data while making important decisions based on legislation.

Keywords: Big Data, Hadoop, HDFS, Caching, MapReduce, web personalization, e-governance.

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Authors: Shih-Bin Wang, Ping Yuan, Syu-Fang Liu, Ming-Jun Kuo

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By the application of an improved back-propagation neural network (BPNN), a model of current densities for a solid oxide fuel cell (SOFC) with 10 layers is established in this study. To build the learning data of BPNN, Taguchi orthogonal array is applied to arrange the conditions of operating parameters, which totally 7 factors act as the inputs of BPNN. Also, the average current densities achieved by numerical method acts as the outputs of BPNN. Comparing with the direct solution, the learning errors for all learning data are smaller than 0.117%, and the predicting errors for 27 forecasting cases are less than 0.231%. The results show that the presented model effectively builds a mathematical algorithm to predict performance of a SOFC stack immediately in real time. Also, the calculating algorithms are applied to proceed with the optimization of the average current density for a SOFC stack. The operating performance window of a SOFC stack is found to be between 41137.11 and 53907.89. Furthermore, an inverse predicting model of operating parameters of a SOFC stack is developed here by the calculating algorithms of the improved BPNN, which is proved to effectively predict operating parameters to achieve a desired performance output of a SOFC stack.

Keywords: a SOFC stack, BPNN, inverse predicting model of operating parameters, optimization of the average current density

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Authors: Shobha.K.R., K. Rajanikanth

Abstract:

An on-demand routing protocol for wireless ad hoc networks is one that searches for and attempts to discover a route to some destination node only when a sending node originates a data packet addressed to that node. In order to avoid the need for such a route discovery to be performed before each data packet is sent, such routing protocols must cache routes previously discovered. This paper presents an analysis of the effect of intelligent caching in a non clustered network, using on-demand routing protocols in wireless ad hoc networks. The analysis carried out is based on the Dynamic Source Routing protocol (DSR), which operates entirely on-demand. DSR uses the cache in every node to save the paths that are learnt during route discovery procedure. In this implementation, caching these paths only at intermediate nodes and using the paths from these caches when required is tried. This technique helps in storing more number of routes that are learnt without erasing the entries in the cache, to store a new route that is learnt. The simulation results on DSR have shown that this technique drastically increases the available memory for caching the routes discovered without affecting the performance of the DSR routing protocol in any way, except for a small increase in end to end delay.

Keywords: Caching, DSR, on demand routing, MANET.

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Authors: Hyun-Young Kim, Chung-Kwang Lee, Han-Hee Cho, Sang-Woon Cho, Yong-Seo Koo

Abstract:

In this paper, we proposed a novel SCR (Silicon Controlled Rectifier) - based ESD (Electrostatic Discharge) protection device for I/O and power clamp. The proposed device has a higher holding voltage characteristic than conventional SCR. These characteristics enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. The proposed device was analyzed to figure out electrical characteristics and tolerance robustness in term of individual design parameters (D1, D2, D3). They are investigated by using the Synopsys TCAD simulator. As a result of simulation, holding voltage increased with different design parameters. The holding voltage of the proposed device changes from 3.3V to 7.9V. Also, N-Stack structure ESD device with the high holding voltage is proposed. In the simulation results, 2-stack has holding voltage of 6.8V and 3-stack has holding voltage of 10.5V. The simulation results show that holding voltage of stacking structure can be larger than the operation voltage of high-voltage application.

Keywords: ESD, SCR, holding voltage, stack, power clamp.

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Authors: Lei Shi, Zhibin Yu, Artur J. Jaworski, Abdulrahman S. Abduljalil

Abstract:

This paper investigates vortex shedding processes occurring at the end of a stack of parallel plates, due to an oscillating flow induced by an acoustic standing wave within an acoustic resonator. Here, Particle Image Velocimetry (PIV) is used to quantify the vortex shedding processes within an acoustic cycle phase-by-phase, in particular during the “ejection" of the fluid out of the stack. Standard hot-wire anemometry measurement is also applied to detect the velocity fluctuations near the end of the stack. Combination of these two measurement techniques allowed a detailed analysis of the vortex shedding phenomena. The results obtained show that, as the Reynolds number varies (by varying the plate thickness and drive ratio), different flow patterns of vortex shedding are observed by the PIV measurement. On the other hand, the time-dependent hot-wire measurements allow obtaining detailed frequency spectra of the velocity signal, used for calculating characteristic Strouhal numbers. The impact of the plate thickness and the Reynolds number on the vortex shedding pattern has been discussed. Furthermore, a detailed map of the relationship between the Strouhal number and Reynolds number has been obtained and discussed.

Keywords: Oscillatory flow, Parallel-plate thermoacoustic stack, Strouhal numbers, Vortex shedding.

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Authors: Zulkiflee M., Robiah Y., Nur Azman Abu, Shahrin S.

Abstract:

Malware is software which was invented and meant for doing harms on computers. Malware is becoming a significant threat in computer network nowadays. Malware attack is not just only involving financial lost but it can also cause fatal errors which may cost lives in some cases. As new Internet Protocol version 6 (IPv6) emerged, many people believe this protocol could solve most malware propagation issues due to its broader addressing scheme. As IPv6 is still new compares to native IPv4, some transition mechanisms have been introduced to promote smoother migration. Unfortunately, these transition mechanisms allow some malwares to propagate its attack from IPv4 to IPv6 network environment. In this paper, a proof of concept shall be presented in order to show that some existing IPv4 malware detection technique need to be improvised in order to detect malware attack in dual-stack network more efficiently. A testbed of dual-stack network environment has been deployed and some genuine malware have been released to observe their behaviors. The results between these different scenarios will be analyzed and discussed further in term of their behaviors and propagation methods. The results show that malware behave differently on IPv6 from the IPv4 network protocol on the dual-stack network environment. A new detection technique is called for in order to cater this problem in the near future.

Keywords: Dual-Stack, Malware, Worm, IPv6;IDS

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Authors: Sung Ho Ahn, Jintae Hong, Chang Young Joung, Tae Ho Yang, Sung Ho Heo, Seo Yun Jang

Abstract:

The performances of nuclear fuels and materials are qualified at an irradiation system in research reactors operating under the commercial nuclear power plant conditions. Fuel centerline temperature, coolant temperature, neutron flux, deformations of fuel stack and swelling are important parameters needed to analyze the nuclear fuel performances. The dimensional stability of nuclear fuels is a key parameter measuring the fuel densification and swelling. In this study, the fuel stack elongation is measured using a LVDT. A mockup LVDT instrumented fuel rod is developed. The performances of mockup LVDT instrumented fuel rod is evaluated by experiments.

Keywords: Axial deformation, elongation measurement, in-pile instrumentation, LVDT.

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Authors: Ching M. Hsu, Rong F. Huang, Michael E. Loretero

Abstract:

Shear-layer instabilities of a pulsed stack-issued transverse jet were studied experimentally in a wind tunnel. Jet pulsations were induced by means of acoustic excitation. Streak pictures of the smoke-flow patterns illuminated by the laser-light sheet in the median plane were recorded with a high-speed digital camera. Instantaneous velocities of the shear-layer instabilities in the flow were digitized by a hot-wire anemometer. By analyzing the streak pictures of the smoke-flow visualization, three characteristic flow modes, synchronized flapping jet, transition, and synchronized shear-layer vortices, are identified in the shear layer of the pulsed stack-issued transverse jet at various excitation Strouhal numbers. The shear-layer instabilities of the pulsed stack-issued transverse jet are synchronized by acoustic excitation except for transition mode. In transition flow mode, the shear-layer vortices would exhibit a frequency that would be twice as great as the acoustic excitation frequency.

Keywords: Acoustic excitation, jet in crossflow, shear-layer instability.

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Authors: Narottam Chand

Abstract:

Wireless sensor networks (WSNs) have gained tremendous attention in recent years due to their numerous applications. Due to the limited energy resource, energy efficient operation of sensor nodes is a key issue in wireless sensor networks. Cooperative caching which ensures sharing of data among various nodes reduces the number of communications over the wireless channels and thus enhances the overall lifetime of a wireless sensor network. In this paper, we propose a cooperative caching scheme called ZCS (Zone Cooperation at Sensors) for wireless sensor networks. In ZCS scheme, one-hop neighbors of a sensor node form a cooperative cache zone and share the cached data with each other. Simulation experiments show that the ZCS caching scheme achieves significant improvements in byte hit ratio and average query latency in comparison with other caching strategies.

Keywords: Admission control, cache replacement, cooperative caching, WSN, zone cooperation

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Authors: Zhibin Yu, Artur J. Jaworski, Abdulrahman S. Abduljalil

Abstract:

A stack with a small critical temperature gradient is desirable for a standing wave thermoacoustic engine to obtain a low onset temperature difference (the minimum temperature difference to start engine-s self-oscillation). The viscous and heat relaxation loss in the stack determines the critical temperature gradient. In this work, a dimensionless critical temperature gradient factor is obtained based on the linear thermoacoustic theory. It is indicated that the impedance determines the proportion between the viscous loss, heat relaxation losses and the power production from the heat energy. It reveals the effects of the channel dimensions, geometrical configuration and the local acoustic impedance on the critical temperature gradient in stacks. The numerical analysis shows that there exists a possible optimum combination of these parameters which leads to the lowest critical temperature gradient. Furthermore, several different geometries have been tested and compared numerically.

Keywords: Critical temperature gradient, heat relaxation, stack, viscous effect.

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Authors: Arian Bahrami, Mojtaba Tafaoli-Masoule, Mansour Nikkhah Bahrami

Abstract:

This paper demonstrates the potential of applying PD-like fuzzy logic controller for active vibration control of piezoelectric Stewart platforms. Through simulation, the control authority of the piezo stack actuators for effectively damping the Stewart platform vibration can be evaluated for further implementation of the system. Each leg of the piezoelectric Stewart platform consists of a linear piezo stack actuator, a collocated velocity sensor, a collocated displacement sensor and flexible tips for the connections with the two end plates. The piezoelectric stack is modeled as a bar element and the electro-mechanical coupling property is simulated using Matlab/Simulink software. Then, the open loop and closed loop dynamic responses are performed for the system to characterize the effect of the control on the vibration of the piezoelectric Stewart platform. A significant improvement in the damping of the structure can be observed by using the PD-like fuzzy controller.

Keywords: Active vibration control, Fuzzy controller, Piezoelectric stewart platform.

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Authors: Shashank Gautam

Abstract:

This paper proposes techniques like MT CMOS, POWER GATING, DUAL STACK, GALEOR and LECTOR to reduce the leakage power. A Full Adder has been designed using these techniques and power dissipation is calculated and is compared with general CMOS logic of Full Adder. Simulation results show the validity of the proposed techniques is effective to save power dissipation and to increase the speed of operation of the circuits to a large extent.

Keywords: Low Power, MT CMOS, Galeor, Lector, Power Gating, Dual Stack, Full Adder.

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