Search results for: Shipra Asija
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 2

Search results for: Shipra Asija

2 Old Age Home Organizer

Authors: Vicky Suri, Monika Suri Grover, Raghav Gupta, Shipra Asija, Sulabh Arya, Sushant Jain

Abstract:

With today's fast lifestyles and busy schedule, nuclear families are becoming popular. Thus, the elderly members of these families are often neglected. This has lead to the popularity of the concept of Community living for the aged. The elders reside at a centre, which is controlled by the MANAGER. The manager takes responsibility of the functioning of the centre which includes taking care of 'residents' at the centre along with managing the daily chores of the centre, which he accomplishes with the help of a number of staff members and volunteers Often the Manager is not an employee but a volunteer. In such cases especially, time is an important constraint. A system, which provides an easy and efficient manner of managing the working of an old age home in detail, will prove to be of great benefit. We have developed a P.C. based organizer used to monitor the various activities of an old age home. It is an effective and easy-to-use system which will enable the manager to keep an account of all the residents, their accounts, staff members, volunteers, the centre-s logistic requirements etc. It is thus, a comprehensive 'Organizer' for Old Age Homes.

Keywords: Old Age Home Organizer, HelpAge India.

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1 Complementary Energy Path Adiabatic Logic based Full Adder Circuit

Authors: Shipra Upadhyay , R. K. Nagaria, R. A. Mishra

Abstract:

In this paper, we present the design and experimental evaluation of complementary energy path adiabatic logic (CEPAL) based 1 bit full adder circuit. A simulative investigation on the proposed full adder has been done using VIRTUOSO SPECTRE simulator of cadence in 0.18μm UMC technology and its performance has been compared with the conventional CMOS full adder circuit. The CEPAL based full adder circuit exhibits the energy saving of 70% to the conventional CMOS full adder circuit, at 100 MHz frequency and 1.8V operating voltage.

Keywords: Adiabatic, CEPAL, full adder, power clock

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