Search results for: N. Shenbaga Vinayaga Moorthi
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 3

Search results for: N. Shenbaga Vinayaga Moorthi

3 Dimethyl Ether as an Ignition Improver for Hydrous Methanol Fuelled Homogeneous Charge Compression Ignition (HCCI) Engine

Authors: M. Venkatesan, N. Shenbaga Vinayaga Moorthi, R. Karthikeyan, A. Manivannan

Abstract:

Homogeneous Charge Compression (HCCI) Ignition technology has been around for a long time, but has recently received renewed attention and enthusiasm. This paper deals with experimental investigations of HCCI engine using hydrous methanol as a primary fuel and Dimethyl Ether (DME) as an ignition improver. A regular diesel engine has been modified to work as HCCI engine for this investigation. The hydrous methanol is inducted and DME is injected into a single cylinder engine. Hence, hydrous methanol is used with 15% water content in HCCI engine and its performance and emission behavior is documented. The auto-ignition of Methanol is enabled by DME. The quantity of DME varies with respect to the load. In this study, the experiments are conducted independently and the effect of the hydrous methanol on the engine operating limit, heat release rate and exhaust emissions at different load conditions are investigated. The investigation also proves that the Hydrous Methanol with DME operation reduces the oxides of Nitrogen and smoke to an extreme low level which is not possible by the direct injection CI engine. Therefore, it is beneficial to use hydrous methanol-DME HCCI mode while using hydrous methanol in internal Combustion Engines.

Keywords: Hydrous Methanol, Dimethyl ether, Performance, Emission and Combustion.

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2 Tree Based Data Aggregation to Resolve Funneling Effect in Wireless Sensor Network

Authors: G. Rajesh, B. Vinayaga Sundaram, C. Aarthi

Abstract:

In wireless sensor network, sensor node transmits the sensed data to the sink node in multi-hop communication periodically. This high traffic induces congestion at the node which is present one-hop distance to the sink node. The packet transmission and reception rate of these nodes should be very high, when compared to other sensor nodes in the network. Therefore, the energy consumption of that node is very high and this effect is known as the “funneling effect”. The tree based-data aggregation technique (TBDA) is used to reduce the energy consumption of the node. The throughput of the overall performance shows a considerable decrease in the number of packet transmissions to the sink node. The proposed scheme, TBDA, avoids the funneling effect and extends the lifetime of the wireless sensor network. The average case time complexity for inserting the node in the tree is O(n log n) and for the worst case time complexity is O(n2).

Keywords: Data Aggregation, Funneling Effect, Traffic Congestion, Wireless Sensor Network.

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1 Low Jitter ADPLL based Clock Generator for High Speed SoC Applications

Authors: Moorthi S., Meganathan D., Janarthanan D., Praveen Kumar P., J. Raja paul perinbam

Abstract:

An efficient architecture for low jitter All Digital Phase Locked Loop (ADPLL) suitable for high speed SoC applications is presented in this paper. The ADPLL is designed using standard cells and described by Hardware Description Language (HDL). The ADPLL implemented in a 90 nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. The simulation result shows that PLL has cycle to cycle jitter of 164 ps and period jitter of 100 ps at 100MHz. Since the digitally controlled oscillator (DCO) can achieve both high resolution and wide frequency range, it can meet the demands of system-level integration. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for System-on-Chip (SoC) applications.

Keywords: All Digital Phase Locked Loop (ADPLL), Systemon-Chip (SoC), Phase Locked Loop (PLL), Very High speedIntegrated Circuit (VHSIC) Hardware Description Language(VHDL), Digitally Controlled Oscillator (DCO), Phase frequencydetector (PFD) and Voltage Controlled Oscillator (VCO).

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