Search results for: MOS-C realization

Authors: Padmanabhan Balasubramanian, C. Ardil

Abstract:

In this paper, we consider the problem of logic simplification for a special class of logic functions, namely complementary Boolean functions (CBF), targeting low power implementation using static CMOS logic style. The functions are uniquely characterized by the presence of terms, where for a canonical binary 2-tuple, D(mj) ∪ D(mk) = { } and therefore, we have | D(mj) ∪ D(mk) | = 0 [19]. Similarly, D(Mj) ∪ D(Mk) = { } and hence | D(Mj) ∪ D(Mk) | = 0. Here, 'mk' and 'Mk' represent a minterm and maxterm respectively. We compare the circuits minimized with our proposed method with those corresponding to factored Reed-Muller (f-RM) form, factored Pseudo Kronecker Reed-Muller (f-PKRM) form, and factored Generalized Reed-Muller (f-GRM) form. We have opted for algebraic factorization of the Reed-Muller (RM) form and its different variants, using the factorization rules of [1], as it is simple and requires much less CPU execution time compared to Boolean factorization operations. This technique has enabled us to greatly reduce the literal count as well as the gate count needed for such RM realizations, which are generally prone to consuming more cells and subsequently more power consumption. However, this leads to a drawback in terms of the design-for-test attribute associated with the various RM forms. Though we still preserve the definition of those forms viz. realizing such functionality with only select types of logic gates (AND gate and XOR gate), the structural integrity of the logic levels is not preserved. This would consequently alter the testability properties of such circuits i.e. it may increase/decrease/maintain the same number of test input vectors needed for their exhaustive testability, subsequently affecting their generalized test vector computation. We do not consider the issue of design-for-testability here, but, instead focus on the power consumption of the final logic implementation, after realization with a conventional CMOS process technology (0.35 micron TSMC process). The quality of the resulting circuits evaluated on the basis of an established cost metric viz., power consumption, demonstrate average savings by 26.79% for the samples considered in this work, besides reduction in number of gates and input literals by 39.66% and 12.98% respectively, in comparison with other factored RM forms.

Keywords: Reed-Muller forms, Logic function, Hammingdistance, Algebraic factorization, Low power design.

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Authors: Oleksandr Krykunov

Abstract:

The source voltage of high-power fuel cell shows strong load dependence at comparatively low voltage levels. In order to provide the voltage of 750V on the DC-link for feeding electrical energy into the mains via a three phase inverter a step-up converter with a large step-up ratio is required. The output voltage of this DC/DC-converter must be stabile during variations of the load current and the voltage of the fuel cell. This paper presents the methods and results of the calculation of the efficiency and the expense for the realization for the circuits of the DC/DC-converter that meet these requirements.

Keywords: DC/DC-converter, calculation, efficiency, fuel cell.

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Authors: E. Al Daoud

Abstract:

In many cases, theoretical treatments are available for models for which there is no perfect physical realization. In this situation, the only possible test for an approximate theoretical solution is to compare with data generated from a computer simulation. In this paper, Monte Carlo tools are used to study and compare the elementary particles models. All the experiments are implemented using 10000 events, and the simulated energy is 13 TeV. The mean and the curves of several variables are calculated for each model using MadAnalysis 5. Anomalies in the results can be seen in the muons masses of the minimal supersymmetric standard model and the two Higgs doublet model.

Keywords: Feynman rules, hadrons, Lagrangian, Monte Carlo, simulation.

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Authors: A. Bulatbayeva, A. Kusainov

Abstract:

In this article has been analyzed Kazakhstani experience in organizing the system after the institute of higher education, legislative-regulative assurance of master preparation, and statistic data in the republic. Have been the features of projecting the master programs, a condition of realization of studying credit system, have been analyzed the technologies of research teaching masters. In conclusion have been given some recommendation on creating personal-oriented environment of research teaching masters.

Keywords: Personal-oriented Environment, Research Teaching, Research Activity, the Technologies of Research Teaching

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Authors: S. Benhamed, S. Hocine, D. Benhamamouch

Abstract:

We try to give a solution of version control for documents in web service, that-s why we propose a new approach used specially for the XML documents. The new approach is applied in a centralized repository, this repository coexist with other repositories in a decentralized system. To achieve the activities of this approach in a standard model we use the ECA active rules. We also show how the Event-Condition-Action rules (ECA rules) have been incorporated as a mechanism for the version control of documents. The need to integrate ECA rules is that it provides a clear declarative semantics and induces an immediate operational realization in the system without the need for human intervention.

Keywords: ECA Rule, Web service, version control system, propagation.

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Authors: Nicolay Zarutskiy, Roman Bulkin

Abstract:

The paper deals with the existing methods of force-torque sensor calibration with a number of components from one to six, analyzed their advantages and disadvantages, the necessity of introduction of a calibration method. Calibration method and its constructive realization are also described here. A calibration method allows performing automated force-torque sensor calibration both with selected components of the main vector of forces and moments and with complex loading. Thus, two main advantages of the proposed calibration method are achieved: the automation of the calibration process and universality.

Keywords: Automation, calibration, calibration device, calibration method, force-torque sensors.

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Authors: Rizwan Asghar, Dake Liu

Abstract:

The direct implementation of interleaver functions in WiMAX is not hardware efficient due to presence of complex functions. Also the conventional method i.e. using memories for storing the permutation tables is silicon consuming. This work presents a 2-D transformation for WiMAX channel interleaver functions which reduces the overall hardware complexity to compute the interleaver addresses on the fly. A fully reconfigurable architecture for address generation in WiMAX channel interleaver is presented, which consume 1.1 k-gates in total. It can be configured for any block size and any modulation scheme in WiMAX. The presented architecture can run at a frequency of 200 MHz, thus fully supporting high bandwidth requirements for WiMAX.

Keywords: Interleaver, deinterleaver, WiMAX, 802.16e.

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Authors: Kar Foo Chong, Pradeep K. Gopalakrishnan, T. Hui Teo

Abstract:

There are multiple ways to implement a decimator filter. This paper addresses usage of CIC (cascaded-integrator-comb) filter and HB (half band) filter as the decimator filter to reduce the frequency sample rate by factor of 64 and detail of the implementation step to realize this design in hardware. Low power design approach for CIC filter and half band filter will be discussed. The filter design is implemented through MATLAB system modeling, ASIC (application specific integrated circuit) design flow and verified using a FPGA (field programmable gate array) board and MATLAB analysis.

Keywords: CIC filter, decimation filter, half-band filter, lowpower.

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Authors: Yi-Fan Zhu, Wei Zhang, Xuan Zhou, Qun Li, Yong-Lin Lei

Abstract:

The quick training algorithms and accurate solution procedure for incremental learning aim at improving the efficiency of training of SVR, whereas there are some disadvantages for them, i.e. the nonconvergence of the formers for changeable training set and the inefficiency of the latter for a massive dataset. In order to handle the problems, a new training algorithm for a changeable training set, named Approximation Incremental Training Algorithm (AITA), was proposed. This paper explored the reason of nonconvergence theoretically and discussed the realization of AITA, and finally demonstrated the benefits of AITA both on precision and efficiency.

Keywords: support vector regression, incremental learning, changeable training set, quick training algorithm, accurate solutionprocedure

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Authors: A. Bocevska, G. Todorov, T. Neshkov

Abstract:

New developed approach for Functional Cost Analysis (FCA) based on virtual prototyping (VP) models in CAD/CAE environment, applicable and necessary in developing new products is presented. It is instrument for improving the value of the product while maintaining costs and/or reducing the costs of the product without reducing value. Five broad classes of VP methods are identified. Efficient use of prototypes in FCA is a vital activity that can make the difference between successful and unsuccessful entry of new products into the competitive word market. Successful realization of this approach is illustrated for a specific example using press joint power tool.

Keywords: CAD/CAE environment, Functional Cost Analysis (FCA), Virtual prototyping (VP) models.

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Authors: Khalid Al-Tahat, Khaled Zuhair Mahmoud, Ahmad Al-Mughrabi

Abstract:

This paper proposes a novel methodology for enabling debugging and tracing of production web applications without affecting its normal flow and functionality. This method of debugging enables developers and maintenance engineers to replace a set of existing resources such as images, server side scripts, cascading style sheets with another set of resources per web session. The new resources will only be active in the debug session and other sessions will not be affected. This methodology will help developers in tracing defects, especially those that appear only in production environments and in exploring the behaviour of the system. A realization of the proposed methodology has been implemented in Java.

Keywords: Live debugging, web application, web resources, inconsistent bugs, tracing.

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Authors: N. Praveen Kumar, Abhijit Mitra, C. Ardil

Abstract:

Decision feedback equalizers are commonly employed to reduce the error caused by intersymbol interference. Here, an adaptive decision feedback equalizer is presented with a new adaptation algorithm. The algorithm follows a block-based approach of normalized least mean square (NLMS) algorithm with set-membership filtering and achieves a significantly less computational complexity over its conventional NLMS counterpart with set-membership filtering. It is shown in the results that the proposed algorithm yields similar type of bit error rate performance over a reasonable signal to noise ratio in comparison with the latter one.

Keywords: Decision feedback equalizer, Adaptive algorithm, Block based computation, Set membership filtering.

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Authors: Yuichi Miyamoto

Abstract:

In regards to the energy sector in the modern period, two points were raised. First is a vast and growing energy demand, and second is an environmental impact associated with it. The enormous consumption of fossil fuel to the mobile unit is leading to its rapid depletion. Nuclear power is not the only problem. A modal shift that utilizes personal transporters and independent power, in order to realize a sustainable society, is very effective. The author proposes that the world will continue to work on this. Energy of the future society, innovation in battery technology and the use of natural energy is a big key. And it is also necessary in order to save on energy consumption.

Keywords: Natural energy, Modal shift, Personal transporter, Battery.

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Authors: Abhijit Mitra, Harpreet Singh Dhillon

Abstract:

We present a novel scheme to evaluate sinusoidal functions with low complexity and high precision using cubic spline interpolation. To this end, two different approaches are proposed to find the interpolating polynomial of sin(x) within the range [- π , π]. The first one deals with only a single data point while the other with two to keep the realization cost as low as possible. An approximation error optimization technique for cubic spline interpolation is introduced next and is shown to increase the interpolator accuracy without increasing complexity of the associated hardware. The architectures for the proposed approaches are also developed, which exhibit flexibility of implementation with low power requirement.

Keywords: Arithmetic, spline interpolator, hardware design, erroranalysis, optimization methods.

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Authors: P. Silapan, C. Chanapromma, T. Worachak

Abstract:

This article proposes a current-mode square-rooting circuit using current follower transconductance amplifier (CTFA). The amplitude of the output current can be electronically controlled via input bias current with wide input dynamic range. The proposed circuit consists of only single CFTA. Without any matching conditions and external passive elements, the circuit is then appropriate for an IC architecture. The magnitude of the output signal is temperature-insensitive. The PSpice simulation results are depicted, and the given results agree well with the theoretical anticipation. The power consumption is approximately 1.96mW at ±1.5V supply voltages.

Keywords: CFTA, Current-mode, Square-rooting Circuit

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Authors: Koson Pitaksuttayaprot, Winai Jaikla

Abstract:

The realization of current-mode quadrature oscillators using current controlled current conveyor transconductance amplifiers (CCCCTAs) and grounded capacitors is presented. The proposed oscillators can provide 2 sinusoidal output currents with 90º phase difference. It is enabled non-interactive dual-current control for both the condition of oscillation and the frequency of oscillation. High output impedances of the configurations enable the circuit to be cascaded without additional current buffers. The use of only grounded capacitors is ideal for integration. The circuit performances are depicted through PSpice simulations, they show good agreement to theoretical anticipation.

Keywords: Current-mode, Oscillator, Integrated circuit, CCCCTA.

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Authors: Todor Penchev, Dimitar Karastojanov, Ivan Altaparmakov

Abstract:

For briquetting of metal chips are used hydraulic and mechanical presses. The density of the briquettes in this case is about 60% - 70 % on the density of solid metal. In this work are presented the results of experimental studies for briquetting of metal chips, by using a new technology for impact briquetting. The used chips are by Armco iron, steel, cast iron, copper, aluminum and brass. It has been found that: (i) in a controlled impact the density of the briquettes can be increases up to 30%; (ii) at the same specific impact energy Es (J/sm3) the density of the briquettes increases with increasing of the impact velocity; (iii), realization of the repeated impact leads to decrease of chips density, which can be explained by distribution of elastic waves in the briquette.

Keywords: Briquetting, chips briquetting, impact briquetting.

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Authors: Mehdi Hosseinzadeh, Amir Sabbagh Molahosseini, Keivan Navi

Abstract:

The residue number system (RNS) is popular in high performance computation applications because of its carry-free nature. The challenges of RNS systems design lie in the moduli set selection and in the reverse conversion from residue representation to weighted representation. In this paper, we proposed a fully parallel reverse conversion algorithm for the moduli set {rn - 2, rn - 1, rn}, based on simple mathematical relationships. Also an efficient hardware realization of this algorithm is presented. Our proposed converter is very faster and results to hardware savings, compared to the other reverse converters.

Keywords: Reverse converter, residue to weighted converter, residue number system, multiple-valued logic, computer arithmetic.

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Authors: K. J. Kachiashvili

Abstract:

The Comparison analysis of the Wald-s and Bayestype sequential methods for testing hypotheses is offered. The merits of the new sequential test are: universality which consists in optimality (with given criteria) and uniformity of decision-making regions for any number of hypotheses; simplicity, convenience and uniformity of the algorithms of their realization; reliability of the obtained results and an opportunity of providing the errors probabilities of desirable values. There are given the Computation results of concrete examples which confirm the above-stated characteristics of the new method and characterize the considered methods in regard to each other.

Keywords: Errors of types I and II, likelihood ratio, the Bayes Type Sequential test, the Wald's sequential test, averaged number of observations.

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Authors: M.F. Zaeh, G. Reinhart, U. Lindemann, F. Karl, W. Biedermann

Abstract:

Due to today-s turbulent environment, manufacturing resources, particularly in assembly, must be reconfigured frequently. These reconfigurations are caused by various, partly cyclic, influencing factors. Hence, it is important to evaluate the innovation ability - the capability of resources to implement innovations quickly and efficiently without large expense - of manufacturing resources. For this purpose, a new methodology is presented in this article. Within the methodology, design structure matrices and graph theory are used. The results of the methodology include different indices to evaluate the innovation ability of the manufacturing resources. Due to the cyclicity of the influencing factors, the methodology can be used to synchronize the realization of adaptations.

Keywords: Changeability, Cycle Management, Design StructureMatrices, Graph Theory, Manufacturing Resource Planning, Production Management

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Authors: Fayez Mostafa Alhamoui, Adnan Hadi Mahdi Al- Helali

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The main issue in designing a wireless sensor network (WSN) is the finding of a proper routing protocol that complies with the several requirements of high reliability, short latency, scalability, low power consumption, and many others. This paper proposes a novel routing algorithm that complies with these design requirements. The new routing protocol divides the WSN into several subnetworks and each sub-network is divided into several clusters. This division is designed to reduce the number of radio transmission and hence decreases the power consumption. The network division may be changed dynamically to adapt with the network changes and allows the realization of the design requirements.

Keywords: Wireless sensor networks, routing protocols, ad hoc topology, cluster, sub-network, WSN design requirements.

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Authors: Xin-Yu Shih, Yue-Qu Liu, Hong-Ru Chou

Abstract:

This paper presents a low-area and fully-reconfigurable Fast Fourier Transform (FFT) hardware design for 3GPP-LTE communication standard. It can fully support 32 different FFT sizes, up to 2048 FFT points. Besides, a special processing element is developed for making reconfigurable computing characteristics possible, while first-in first-out (FIFO) scheduling scheme design technique is proposed for hardware-friendly FIFO resource arranging. In a synthesis chip realization via TSMC 40 nm CMOS technology, the hardware circuit only occupies core area of 0.2325 mm² and dissipates 233.5 mW at maximal operating frequency of 250 MHz.

Keywords: Reconfigurable, fast Fourier transform, single-path delay feedback, 3GPP-LTE.

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Authors: Prungsak Uttaphut

Abstract:

An implementation of current-mode multiphase sinusoidal oscillators is presented. Using CFTA-based lossy integrators, odd and odd/even phase systems can be realized with following advantages. The condition of oscillation and frequency of oscillation can be orthogonally tuned. The high output impedances facilitate easy driving an external load without additional current buffers. The proposed MSOs provide odd or even phase signals that are equally spaced in phase and equal amplitude. The circuit requires one CFTA, one resistor and one grounded capacitor per phase without additional current amplifier. The results of PSPICE simulations using CMOS CFTA are included to verify theory.

Keywords: multiphase sinusoidal oscillator, current-mode, CFTA, lossy integrator

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Authors: Marco Hemmerling

Abstract:

The paper outlines the relevance of computational geometry within the design and production process of architecture. Based on two case studies, the digital chain - from the initial formfinding to the final realization of spatial concepts - is discussed in relation to geometric principles. The association with the fascinating complexity that can be found in nature and its underlying geometry was the starting point for both projects presented in the paper. The translation of abstract geometric principles into a three-dimensional digital design model – realized in Rhinoceros – was followed by a process of transformation and optimization of the initial shape that integrated aesthetic, spatial and structural qualities as well as aspects of material properties and conditions of production.

Keywords: Architecture, Computer Aided Architectural Design, 3D-Modeling, Rapid Prototyping, CAD/CAM.

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Authors: S. Ntalampiras, I. Potamitis, N. Fakotakis, S. Kouzoupis

Abstract:

The present work faces the problem of automatic enumeration and recognition of an unknown and time-varying number of environmental sound sources while using a single microphone. The assumption that is made is that the sound recorded is a realization of sound sources belonging to a group of audio classes which is known a-priori. We describe two variations of the same principle which is to calculate the distance between the current unknown audio frame and all possible combinations of the classes that are assumed to span the soundscene. We concentrate on categorizing environmental sound sources, such as birds, insects etc. in the task of monitoring the biodiversity of a specific habitat.

Keywords: automatic recognition of multiple sound sources, enumeration of sound sources, computational ecology.

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Authors: Yavar Safaei Mehrabani, Mehdi Hosseinzadeh

Abstract:

As embedded and portable systems were emerged power consumption of circuits had been major challenge. On the other hand latency as determines frequency of circuits is also vital task. Therefore, trade off between both of them will be desirable. Modulo 2n+1 adders are important part of the residue number system (RNS) based arithmetic units with the interesting moduli set (2n-1,2n, 2n+1). In this manuscript we have introduced novel binary representation to the design of modulo 2n+1 adder. VLSI realization of proposed architecture under 180 nm full static CMOS technology reveals its superiority in terms of area, power consumption and power-delay product (PDP) against several peer existing structures.

Keywords: Computer arithmetic, modulo 2n+1 adders, Residue Number System (RNS), VLSI.

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Authors: C. R. Ríos-Soberanis, V. M. Moo-Huchin, R. J. Estrada-Leon, E. Perez-Pacheco

Abstract:

Polymers from renewable resources have attracted an increasing amount of attention over the last two decades, predominantly due to two major reasons: firstly environmental concerns, and secondly the realization that our petroleum resources are finite. Finding new uses for agricultural commodities is also an important area of research. Therefore, it is crucial to get new sources of natural materials that can be used in different applications. Ramon tree (Brosimum alicastrum) is a tropical plant that grows freely in Yucatan countryside. This paper focuses on the seeds recollection, processing and starch extraction and characterization in order to find out about its suitability as biomaterial. Results demonstrated that it has a high content of qualities to be used not only as comestible but also as an important component in polymeric blends.

Keywords: Biomaterials, biopolymer, starch, characterization techniques.

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Authors: Anatoly D. Pluzhnikov, Elena N. Pribludova, Alexander G. Ryndyk

Abstract:

In conjunction with the problem of the target selection on a clutter background, the analysis of the scanning rate influence on the spatial-temporal signal structure, the generalized multivariate correlation function and the quality of the resolution with the increase pulse repetition frequency is made. The possibility of the object space-distance resolution, which is conditioned by the range-to-angle conversion with an increased scanning rate, is substantiated. The calculations for the real cylindrical array at high scanning rate are presented. The high scanning rate let to get the signal to noise improvement of the order of 10 dB for the space-time signal processing.

Keywords: Antenna pattern, array, signal processing, spatial resolution.

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Authors: Shengqi Yu, Jinwei Zhao

Abstract:

This paper presents a kind of analog circuit based temperature control system, which is mainly composed by threshold control signal circuit, synchronization signal circuit and trigger pulse circuit. Firstly, the temperature feedback signal function is realized by temperature sensor TS503F3950E. Secondly, the main control circuit forms the cycle controlled pulse signal to control the thyristor switching model. Finally two reverse paralleled thyristors regulate the output power by their switching state. In the consequence, this is a modernized and energy-saving domestic electric heating system.

Keywords: Time base circuit, automatic control, zero-crossing trigger, temperature control.

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Authors: J. Novak-Marcincin, J. Barna, M. Janak

Abstract:

Augmented Reality (AR) shows great promises for its usage as a tool for simulation and verification of design proposal of new technological systems. Main advantage of augmented reality application usage is possibility of creation and simulation of new technological unit before its realization. This may contribute to increasing of safety and ergonomics and decreasing of economical aspects of new proposed unit. Virtual model of proposed workcell could reveal hidden errors which elimination in later stage of new workcell creation should cause great difficulties. Paper describes process of such virtual model creation and possibilities of its simulation and verification by augmented reality tools.

Keywords: Augmented reality, simulation, workcell design.

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