Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 137

Search results for: Low power

107 Designing of Full Adder Using Low Power Techniques

Authors: Shashank Gautam

Abstract:

This paper proposes techniques like MT CMOS, POWER GATING, DUAL STACK, GALEOR and LECTOR to reduce the leakage power. A Full Adder has been designed using these techniques and power dissipation is calculated and is compared with general CMOS logic of Full Adder. Simulation results show the validity of the proposed techniques is effective to save power dissipation and to increase the speed of operation of the circuits to a large extent.

Keywords: Low Power, MT CMOS, Galeor, Lector, Power Gating, Dual Stack, Full Adder.

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106 Highly Optimized Novel High Speed Low Power Barrel Shifter at 22nm Hi K Metal Gate Strained Si Technology Node

Authors: Shobha Sharma, Amita Dev

Abstract:

This research paper presents highly optimized barrel shifter at 22nm Hi K metal gate strained Si technology node. This barrel shifter is having a unique combination of static and dynamic body bias which gives lowest power delay product. This power delay product is compared with the same circuit at same technology node with static forward biasing at ‘supply/2’ and also with normal reverse substrate biasing and still found to be the lowest. The power delay product of this barrel sifter is .39362X10-17J and is lowered by approximately 78% to reference proposed barrel shifter at 32nm bulk CMOS technology. Power delay product of barrel shifter at 22nm Hi K Metal gate technology with normal reverse substrate bias is 2.97186933X10-17J and can be compared with this design’s PDP of .39362X10-17J. This design uses both static and dynamic substrate biasing and also has approximately 96% lower power delay product compared to only forward body biased at half of supply voltage. The NMOS model used are predictive technology models of Arizona state university and the simulations to be carried out using HSPICE simulator.

Keywords: Dynamic body biasing, highly optimized barrel shifter, PDP, Static body biasing.

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105 Transient Enhanced LDO Voltage Regulator with Improved Feed Forward Path Compensation

Authors: Suresh Alapati, Sreehari Rao Patri, K. S. R. Krishna Prasad

Abstract:

Anultra-low power capacitor less low-dropout voltage regulator with improved transient response using gain enhanced feed forward path compensation is presented in this paper. It is based on a cascade of a voltage amplifier and a transconductor stage in the feed forward path with regular error amplifier to form a composite gainenhanced feed forward stage. It broadens the gain bandwidth and thus improves the transient response without substantial increase in power consumption. The proposed LDO, designed for a maximum output current of 100 mA in UMC 180 nm, requires a quiescent current of 69 )A. An undershot of 153.79mV for a load current changes from 0mA to 100mA and an overshoot of 196.24mV for current change of 100mA to 0mA. The settling time is approximately 1.1 )s for the output voltage undershooting case. The load regulation is of 2.77 )V/mA at load current of 100mA. Reference voltage is generated by using an accurate band gap reference circuit of 0.8V.The costly features of SOC such as total chip area and power consumption is drastically reduced by the use of only a total compensation capacitance of 6pF while consuming power consumption of 0.096 mW.

Keywords: Capacitor-less LDO, frequency compensation, Transient response, latch, self-biased differential amplifier.

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104 Transient Analysis & Performance Estimation of Gate Inside Junctionless Transistor (GI-JLT)

Authors: Sangeeta Singh, Pankaj Kumar, P. N. Kondekar

Abstract:

In this paper, the transient device performance analysis of n-type Gate Inside JunctionLess Transistor (GI-JLT) has been evaluated. 3-D Bohm Quantum Potential (BQP) transport device simulation has been used to evaluate the delay and power dissipation performance. GI-JLT has a number of desirable device parameters such as reduced propagation delay, dynamic power dissipation, power and delay product, intrinsic gate delay and energy delay product as compared to Gate-all-around transistors GAA-JLT. In addition to this, various other device performance parameters namely, on/off current ratio, short channel effects (SCE), transconductance Generation Factor (TGF) and unity gain cut-off frequency (fT ) and subthreshold slope (SS) of the GI-JLT and GAA-JLT have been analyzed and compared. GI-JLT shows better device performance characteristics than GAA-JLT for low power and high frequency applications, because of its larger gate electrostatic control on the device operation.

Keywords: Gate-inside junctionless transistor GI-JLT, Gate-all-around junctionless transistor GAA-JLT, propagation delay, power delay product.

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103 Low Power CNFET SRAM Design

Authors: Pejman Hosseiniun, Rose Shayeghi, Iman Rahbari, Mohamad Reza Kalhor

Abstract:

CNFET has emerged as an alternative material to silicon for high performance, high stability and low power SRAM design in recent years. SRAM functions as cache memory in computers and many portable devices. In this paper, a new SRAM cell design based on CNFET technology is proposed. The proposed SRAM cell design for CNFET is compared with SRAM cell designs implemented with the conventional CMOS and FinFET in terms of speed, power consumption, stability, and leakage current. The HSPICE simulation and analysis show that the dynamic power consumption of the proposed 8T CNFET SRAM cell’s is reduced about 48% and the SNM is widened up to 56% compared to the conventional CMOS SRAM structure at the expense of 2% leakage power and 3% write delay increase.

Keywords: SRAM cell, CNFET, low power, HSPICE.

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102 Development of a New Piezoelectrically Actuated Micropump for Liquid and Gas

Authors: Chiang-Ho Cheng, An-Shik Yang, Chih-Jer Lin, Chun-Ying Lee

Abstract:

This paper aims to present the design, fabrication and test of a novel piezoelectric actuated, check-valves embedded micropump having the advantages of miniature size, light weight and low power consumption. This device is designed to pump gases and liquids with the capability of performing the self-priming and bubble-tolerant work mode by maximizing the stroke volume of the membrane as well as the compression ratio via minimization of the dead volume of the micropump chamber and channel. By experiment apparatus setup, we can get the real-time values of the flow rate of micropump, the displacement of the piezoelectric actuator and the deformation of the check valve, simultaneously. The micropump with check valve 0.4 mm in thickness obtained higher output performance under the sinusoidal waveform of 120 Vpp. The micropump achieved the maximum pumping rates of 42.2 ml/min and back pressure of 14.0 kPa at the corresponding frequency of 28 and 20 Hz. The presented micropump is able to pump gases with a pumping rate of 196 ml/min at operating frequencies of 280 Hz under the sinusoidal waveform of 120 Vpp.

Keywords: Actuator, Check-valve, Micropump, Piezoelectric.

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101 Optical Properties of WO3-NiO Complementary Electrochromic Devices

Authors: Chih-Ming Wang, Chih-Yu Wen, Ying-Chung Chen, Chun-Chieh Wang, Chien-Chung Hsu, Jui-Yang Chang, Jyun-Min Lin

Abstract:

In this study, we developed a complementary electrochromic device consisting of WO3 and NiO films fabricated by rf-magnetron sputtered. The electrochromic properties of WO3 and NiO films were investigated using cyclic voltammograms (CV), performed on WO3 and NiO films immersed in an electrolyte of 1 M LiClO4 in propylene carbonate (PC). Optical and electrochemical of the films, as a function of coloration–bleaching cycle, were characterized using an UV-Vis-NIR spectrophotometer and cyclic voltammetry (CV). After investigating the properties of WO3 film, NiO film, and complementary electrochromic devices, we concluded that this device provides good reversibility, low power consumption of -2.5 V in color state, high variation of transmittance of 58.96%, changes in optical density of 0.81 and good memory effect under open-circuit conditions. In addition, electrochromic component penetration rate can be retained below 20% within 24h, showing preferred memory features; however, component coloring and bleaching response time are about 33s.

Keywords: Complementary electrochromic device, Rf-magnetron sputtered, Transmittance, Memory effect, Optical density change

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100 Design and Analysis of an 8T Read Decoupled Dual Port SRAM Cell for Low Power High Speed Applications

Authors: Ankit Mitra

Abstract:

Speed, power consumption and area, are some of the most important factors of concern in modern day memory design. As we move towards Deep Sub-Micron Technologies, the problems of leakage current, noise and cell stability due to physical parameter variation becomes more pronounced. In this paper we have designed an 8T Read Decoupled Dual Port SRAM Cell with Dual Threshold Voltage and characterized it in terms of read and write delay, read and write noise margins, Data Retention Voltage and Leakage Current. Read Decoupling improves the Read Noise Margin and static power dissipation is reduced by using Dual-Vt transistors. The results obtained are compared with existing 6T, 8T, 9T SRAM Cells, which shows the superiority of the proposed design. The Cell is designed and simulated in TSPICE using 90nm CMOS process.

Keywords: CMOS, Dual-Port, Data Retention Voltage, 8T SRAM, Leakage Current, Noise Margin, Loop-cutting, Single-ended.

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99 Performance Study of ZigBee-Based Wireless Sensor Networks

Authors: Afif Saleh Abugharsa

Abstract:

The IEEE 802.15.4 standard is designed for low-rate wireless personal area networks (LR-WPAN) with focus on enabling wireless sensor networks. It aims to give a low data rate, low power consumption, and low cost wireless networking on the device-level communication. The objective of this study is to investigate the performance of IEEE 802.15.4 based networks using simulation tool. In this project the network simulator 2 NS2 was used to several performance measures of wireless sensor networks. Three scenarios were considered, multi hop network with a single coordinator, star topology, and an ad hoc on demand distance vector AODV. Results such as packet delivery ratio, hop delay, and number of collisions are obtained from these scenarios.

Keywords: ZigBee, wireless sensor networks, IEEE 802.15.4, low power, low data rate

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98 Design and Analysis of a Low Power High Speed 1 Bit Full Adder Cell Based On TSPC Logic with Multi-Threshold CMOS

Authors: Ankit Mitra

Abstract:

An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.

Keywords: CMOS, TSPC, MTCMOS, ALU, Clock gating, power gating, pipelining.

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97 Design of CMOS CFOA Based on Pseudo Operational Transconductance Amplifier

Authors: Hassan Jassim Motlak

Abstract:

A novel design technique employing CMOS Current Feedback Operational Amplifier (CFOA) is presented. The feature of consumption very low power in designing pseudo-OTA is used to decreasing the total power consumption of the proposed CFOA. This design approach applies pseudo-OTA as input stage cascaded with buffer stage. Moreover, the DC input offset voltage and harmonic distortion (HD) of the proposed CFOA are very low values compared with the conventional CMOS CFOA due to the symmetrical input stage. P-Spice simulation results are obtained using 0.18μm MIETEC CMOS process parameters and supply voltage of ±1.2V, 50μA biasing current. The p-spice simulation shows excellent improvement of the proposed CFOA over existing CMOS CFOA. Some of these performance parameters, for example, are DC gain of 62. dB, openloop gain bandwidth product of 108 MHz, slew rate (SR+) of +71.2V/μS, THD of -63dB and DC consumption power (PC) of 2mW.

Keywords: Pseudo-OTA used CMOS CFOA, low power CFOA, high-performance CFOA, novel CFOA.

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96 Microgrid: Low Power Network Topology and Control

Authors: Amit Sachan

Abstract:

The network designing and data modeling developments which are the two significant research tasks in direction to tolerate power control of Microgrid concluded using IEC 61850 data models and facilities. The current casing areas of IEC 61580 include infrastructures in substation automation systems, among substations and to DERs. So, for LV microgrid power control, previously using the IEC 61850 amenities to control the smart electrical devices, we have to model those devices as IEC 61850 data models and design a network topology to maintenance all-in-one communiqué amid those devices. In adding, though IEC 61850 assists modeling a portion by open-handed several object models for common functions similar measurement, metering, monitoring…etc., there are motionless certain missing smithereens for building a multiplicity of functions for household appliances like tuning the temperature of an electric heater or refrigerator.

Keywords: IEC 61850, RCMC, HCMC, DER Unit Controller.

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95 Robust & Energy Efficient Universal Gates for High Performance Computer Networks at 22nm Process Technology

Authors: M. Geetha Priya, K. Baskaran, S. Srinivasan

Abstract:

Digital systems are said to be constructed using basic logic gates. These gates are the NOR, NAND, AND, OR, EXOR & EXNOR gates. This paper presents a robust three transistors (3T) based NAND and NOR gates with precise output logic levels, yet maintaining equivalent performance than the existing logic structures. This new set of 3T logic gates are based on CMOS inverter and Pass Transistor Logic (PTL). The new universal logic gates are characterized by better speed and lower power dissipation which can be straightforwardly fabricated as memory ICs for high performance computer networks. The simulation tests were performed using standard BPTM 22nm process technology using SYNOPSYS HSPICE. The 3T NAND gate is evaluated using C17 benchmark circuit and 3T NOR is gate evaluated using a D-Latch. According to HSPICE simulation in 22 nm CMOS BPTM process technology under given conditions and at room temperature, the proposed 3T gates shows an improvement of 88% less power consumption on an average over conventional CMOS logic gates. The devices designed with 3T gates will make longer battery life by ensuring extremely low power consumption.

Keywords: Low power, CMOS, pass-transistor, flash memory, logic gates.

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94 Design and Implementation of a 10-bit SAR ADC

Authors: Hasmayadi Abdul Majid, Rohana Musa

Abstract:

This paper presents the development of a 38.5 kS/s 10-bit low power SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and SAR digital logic to create 10 effective bits while consuming less than 7.8 mW with a 3.3 V power supply.

Keywords: Successive Approximation Register Analog-to- Digital Converter, SAR ADC, Resistive DAC.

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93 Novel Intrinsic Conducting Polymer Current Limiting Device (CLD) for Surge Protection

Authors: Noor H Jabarullah

Abstract:

In the past many uneconomic solutions for limitation and interruption of short-circuit currents in low power applications have been introduced, especially polymer switch based on the positive temperature coefficient of resistance (PCTR) concept. However there are many limitations in the active material, which consists of conductive fillers. This paper presents a significantly improved and simplified approach that replaces the existing current limiters with faster switching elements. Its elegance lies in the remarkable simplicity and low-cost processes of producing the device using polyaniline (PANI) doped with methane-sulfonic acid (MSA). Samples characterized as lying in the metallic and critical regimes of metal insulator transition have been studied by means of electrical performance in the voltage range from 1V to 5 V under different environmental conditions. Moisture presence is shown to increase the resistivity and also improved its current limiting performance. Additionally, the device has also been studied for electrical resistivity in the temperature range 77 K-300 K. The temperature dependence of the electrical conductivity gives evidence for a transport mechanism based on variable range hopping in three dimensions.

Keywords: Conducting polymer, current limiter, intrinsic, moisture dependence, polyaniline, resettable, surge protection.

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92 Low Power Capacitance-to-Voltage Converter for Magnetometer Interface IC

Authors: Dipankar Nag, Choe Andrew Kunil, Kevin Chai Tshun Chuan, Minkyu Je

Abstract:

This paper presents the design and implementation of a fully integrated Capacitance-to-Voltage Converter (CVC) as the analog front-end for magnetometer interface IC. The application demands very low power solution operating in the frequency of around 20 KHz. The design adapts low power architecture to create low noise electronic interface for Capacitive Micro-machined Lorentz force magnetometer sensor. Using a 0.18-μm CMOS process, simulation results of this interface IC show that the proposed CVC can provide 33 dB closed loop gain, 20 nV/√Hz input referred noise at 20 KHz, while consuming 65 μA current from 1.8-V supply. 

Keywords: Analog front end, Capacitance-to-Voltage Converter, Magnetometer, MEMS, Recycling Folded Cascode.

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91 Investigation of Constant Transconductance Circuit for Low Power Low-Noise Amplifier

Authors: Wei Yi Lim, M. Annamalai Arasu, M. Kumarasamy Raja, Minkyu Je

Abstract:

In this paper, the design of wide-swing constant transconductance (gm) bias circuit that generates bias voltage for low-noise amplifier (LNA) circuit design by using an off-chip resistor is demonstrated. The overall transconductance (Gm) generated by the constant gm bias circuit is important to maintain the overall gain and noise figure of the LNA circuit. Therefore, investigation is performed to study the variation in Gm with process, temperature and supply voltage (PVT).  Temperature and supply voltage are swept from -10 °C to 85 °C and 1.425 V to 1.575 V respectively, while the process conditions are also varied to the extreme and the gm variation is eventually concluded at between -3 % to 7 %. With the slight variation in the gm value, through simulation, at worst condition of state SS, we are able to attain a conversion gain (S21) variation of -3.10 % and a noise figure (NF) variation of 18.71 %. The whole constant gm circuit draws approximately 100 µA from a 1.5V supply and is designed based on 0.13 µm CMOS process. 

Keywords: Transconductance, LNA, temperature, process.

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90 Subthreshold Circuit Performance Investigation under Temperature Variations

Authors: Mohd. Hasan, Ajmal Kafeel, S. D. Pable

Abstract:

Ultra-low-power (ULP) circuits have received widespread attention due to the rapid growth of biomedical applications and Battery-less Electronics. Subthreshold region of transistor operation is used in ULP circuits. Major research challenge in the subthreshold operating region is to extract the ULP benefits with minimal degradation in speed and robustness. Process, Voltage and Temperature (PVT) variations significantly affect the performance of subthreshold circuits. Designed performance parameters of ULP circuits may vary largely due to temperature variations. Hence, this paper investigates the effect of temperature variation on device and circuit performance parameters at different biasing voltages in the subthreshold region. Simulation results clearly demonstrate that in deep subthreshold and near threshold voltage regions, performance parameters are significantly affected whereas in moderate subthreshold region, subthreshold circuits are more immune to temperature variations. This establishes that moderate subthreshold region is ideal for temperature immune circuits.

Keywords: Subthreshold, temperature variations, ultralow power.

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89 Investigating the Effect of Using Capacitors in the Pumping Station on the Harmonic Contents (Case Study: Kafr El - Shikh Governorate, Egypt)

Authors: Khaled M. Fetyan

Abstract:

Power Factor (PF) is one of the most important parameters in the electrical systems, especially in the water pumping station. The low power factor value of the water pumping stations causes penalty for the electrical bill. There are many methods use for power factor improvement. Each one of them uses a capacitor on the electrical power network. The position of the capacitors is varied depends on many factors such as; voltage level and capacitors rating. Adding capacitors on the motor terminals increase the supply power factor from 0.8 to more than 0.9 but these capacitors cause some problems for the electrical grid network, such as increasing the harmonic contents of the grid line voltage. In this paper the effects of using capacitors in the water pumping stations to improve the power factor value on the harmonic contents of the electrical grid network are studied. One of large water pumping stations in Kafr El-Shikh Governorate in Egypt was used, as a case study. The effect of capacitors on the line voltage harmonic contents is measured. The station uses capacitors to improve the PF values at the 1 lkv grid network. The power supply harmonics values are measured by a power quality analyzer at different loading conditions. The results showed that; the capacitors improved the power factor value of the feeder and its value increased than 0.9. But the THD values are increased by adding these capacitors. The harmonic analysis showed that; the 13th, 17th, and 19th harmonics orders are increased also by adding the capacitors.

Keywords: Water pumping stations, power factor improvement, total harmonic distortions (THD), power quality.

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88 Energy Efficient Clustering and Data Aggregation in Wireless Sensor Networks

Authors: Surender Kumar Soni

Abstract:

Wireless Sensor Networks (WSNs) are wireless networks consisting of number of tiny, low cost and low power sensor nodes to monitor various physical phenomena like temperature, pressure, vibration, landslide detection, presence of any object, etc. The major limitation in these networks is the use of nonrechargeable battery having limited power supply. The main cause of energy consumption WSN is communication subsystem. This paper presents an efficient grid formation/clustering strategy known as Grid based level Clustering and Aggregation of Data (GCAD). The proposed clustering strategy is simple and scalable that uses low duty cycle approach to keep non-CH nodes into sleep mode thus reducing energy consumption. Simulation results demonstrate that our proposed GCAD protocol performs better in various performance metrics.

Keywords: Ad hoc network, Cluster, Grid base clustering, Wireless sensor network.

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87 Energy Efficient Cooperative Caching in WSN

Authors: Narottam Chand

Abstract:

Wireless sensor networks (WSNs) consist of number of tiny, low cost and low power sensor nodes to monitor some physical phenomenon. The major limitation in these networks is the use of non-rechargeable battery having limited power supply. The main cause of energy consumption in such networks is communication subsystem. This paper presents an energy efficient Cluster Cooperative Caching at Sensor (C3S) based upon grid type clustering. Sensor nodes belonging to the same cluster/grid form a cooperative cache system for the node since the cost for communication with them is low both in terms of energy consumption and message exchanges. The proposed scheme uses cache admission control and utility based data replacement policy to ensure that more useful data is retained in the local cache of a node. Simulation results demonstrate that C3S scheme performs better in various performance metrics than NICoCa which is existing cooperative caching protocol for WSNs.

Keywords: Cooperative caching, cache replacement, admission control, WSN, clustering.

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86 An Efficient Burst Errors Combating for Image Transmission over Mobile WPANs

Authors: Mohsen A. M. El-Bendary, Mostafa A. R. El-Tokhy

Abstract:

This paper presents an efficient burst error spreading tool. Also, it studies a vital issue in wireless communications, which is the transmission of images over wireless networks. IEEE ZigBee 802.15.4 is a short-range communication standard that could be used for small distance multimedia transmissions. In fact, the ZigBee network is a Wireless Personal Area Network (WPAN), which needs a strong interleaving mechanism for protection against error bursts. Also, it is low power technology and utilized in the Wireless Sensor Networks (WSN) implementation. This paper presents the chaotic interleaving scheme as a data randomization tool for this purpose. This scheme depends on the chaotic Baker map. The mobility effects on the image transmission are studied with different velocity through utilizing the Jakes’ model. A comparison study between the proposed chaotic interleaving scheme and the traditional block and convolutional interleaving schemes for image transmission over a correlated fading channel is presented. The simulation results show the superiority of the proposed chaotic interleaving scheme over the traditional schemes.

Keywords: WPANs, Burst Errors, Mobility, Interleaving Techniques, Fading channels.

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85 The Effects of Rain and Overland Flow Powers on Agricultural Soil Erodibility

Authors: A. Moussouni, L. Mouzai, M. Bouhadef

Abstract:

The purpose of this investigation is to relate the rain power and the overland flow power to soil erodibility to assess the effects of both parameters on soil erosion using variable rainfall intensity on remoulded agricultural soil. Six rainfall intensities were used to simulate the natural rainfall and are as follows: 12.4mm/h, 20.3mm/h, 28.6mm/h, 52mm/h, 73.5mm/h and 103mm/h. The results have shown that the relationship between overland flow power and rain power is best represented by a linear function (R2=0.99). As regards the relationships between soil erodibility factor and rain and overland flow powers, the evolution of both parameters with the erodibility factor follow a polynomial function with high coefficient of determination. From their coefficients of determination (R2=0.95) for rain power and (R2=0.96) for overland flow power, we can conclude that the flow has more power to detach particles than rain. This could be explained by the fact that the presence of particles, already detached by rain and transported by the flow, give the flow more weight and then contribute to the detachment of particles by collision.

Keywords: Laboratory experiments, soil erosion, flow power, erodibility, rainfall intensity.

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84 Design of Low Power and High Speed Digital IIR Filter in 45nm with Optimized CSA for Digital Signal Processing Applications

Authors: G. Ramana Murthy, C. Senthilpari, P. Velrajkumar, Lim Tien Sze

Abstract:

In this paper, a design methodology to implement low-power and high-speed 2nd order recursive digital Infinite Impulse Response (IIR) filter has been proposed. Since IIR filters suffer from a large number of constant multiplications, the proposed method replaces the constant multiplications by using addition/subtraction and shift operations. The proposed new 6T adder cell is used as the Carry-Save Adder (CSA) to implement addition/subtraction operations in the design of recursive section IIR filter to reduce the propagation delay. Furthermore, high-level algorithms designed for the optimization of the number of CSA blocks are used to reduce the complexity of the IIR filter. The DSCH3 tool is used to generate the schematic of the proposed 6T CSA based shift-adds architecture design and it is analyzed by using Microwind CAD tool to synthesize low-complexity and high-speed IIR filters. The proposed design outperforms in terms of power, propagation delay, area and throughput when compared with MUX-12T, MCIT-7T based CSA adder filter design. It is observed from the experimental results that the proposed 6T based design method can find better IIR filter designs in terms of power and delay than those obtained by using efficient general multipliers.

Keywords: CSA Full Adder, Delay unit, IIR filter, Low-Power, PDP, Parametric Analysis, Propagation Delay, Throughput, VLSI.

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83 Reduction of Leakage Power in Digital Logic Circuits Using Stacking Technique in 45 Nanometer Regime

Authors: P.K. Sharma, B. Bhargava, S. Akashe

Abstract:

Power dissipation due to leakage current in the digital circuits is a biggest factor which is considered specially while designing nanoscale circuits. This paper is exploring the ideas of reducing leakage current in static CMOS circuits by stacking the transistors in increasing numbers. Clearly it means that the stacking of OFF transistors in large numbers result a significant reduction in power dissipation. Increase in source voltage of NMOS transistor minimizes the leakage current. Thus stacking technique makes circuit with minimum power dissipation losses due to leakage current. Also some of digital circuits such as full adder, D flip flop and 6T SRAM have been simulated in this paper, with the application of reduction technique on ‘cadence virtuoso tool’ using specter at 45nm technology with supply voltage 0.7V.

Keywords: Stack, 6T SRAM cell, low power, threshold voltage

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82 Memristor: The Missing Circuit Element and its Application

Authors: Vishnu Pratap Singh Kirar

Abstract:

Memristor is also known as the fourth fundamental passive circuit element. When current flows in one direction through the device, the electrical resistance increases and when current flows in the opposite direction, the resistance decreases. When the current is stopped, the component retains the last resistance that it had, and when the flow of charge starts again, the resistance of the circuit will be what it was when it was last active. It behaves as a nonlinear resistor with memory. Recently memristors have generated wide research interest and have found many applications. In this paper we survey the various applications of memristors which include non volatile memory, nanoelectronic memories, computer logic, neuromorphic computer architectures low power remote sensing applications, crossbar latches as transistor replacements, analog computations and switches.

Keywords: Memristor, non-volatile memory, arithmatic operation, programmable resistor.

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81 The Influence of Low Power Microwave Radiation on the Growth Rate of Listeria Monocytogenes

Authors: Renzo Carta, Francesco Desogus

Abstract:

Variations in the growth rate constant of the Listeria monocytogenes bacterial species were determined at 37°C in irradiated environments and compared to the situation of a nonirradiated environment. The bacteria cells, contained in a suspension made of a nutrient solution of Brain Heart Infusion, were made to grow at different frequency (2.30e2.60 GHz) and power (0e400 mW) values, in a plug flow reactor positioned in the irradiated environment. Then the reacting suspension was made to pass into a cylindrical cuvette where its optical density was read every 2.5 minutes at a wavelength of 600 nm. The obtained experimental data of optical density vs. time allowed the bacterial growth rate constant to be derived; this was found to be slightly influenced by microwave power, but not by microwave frequency; in particular, a minimum value was found for powers in the 50e150 mW field.

Keywords: Growth rate constant, irradiated environment, Listeria monocytogenes, microwaves, plug flow reactor.

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80 Modeling of a Novel Dual-Belt Continuously Variable Transmission for Automobiles

Authors: Y. Q. Chen, P. K. Wong, Z. C. Xie, H. W. Wu, K. U. Chan, J., L. Huang

Abstract:

It is believed that continuously variable transmission (CVT) will dominate the automotive transmissions in the future. The most popular design is Van Doorne-s CVT with single metal pushing V-belt. However, it is only applicable to low power passenger cars because its major limitation is low torque capacity. Therefore, this research studies a novel dual-belt CVT system to overcome the limitation of traditional single-belt CVT, such that it can be applicable to the heavy-duty vehicles. This paper presents the mathematical model of the design and its experimental verification. Experimental and simulated results show that the model developed is valid and the proposed dual-belt CVT can really overcome the traditional limitation of single-belt Van Doorne-s CVT.

Keywords: Analytical model, CVT, Dual belts, Torque capacity.

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79 Low Power Digital System for Reconfigurable Neural Recording System

Authors: Peng Li, Jun Zhou, Xin Liu, Chee Keong Ho, Xiaodan Zou, Minkyu Je

Abstract:

A digital system is proposed for low power 100- channel neural recording system in this paper, which consists of 100 amplifiers, 100 analog-to-digital converters (ADC), digital controller and baseband, transceiver for data link and RF command link. The proposed system is designed in a 0.18 μm CMOS process and 65 nm CMOS process.

Keywords: multiplex, neural recording, synchronization, transceiver

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78 Silicon-based Low-Power Reconfigurable Optical Add-Drop Multiplexer (ROADM)

Authors: Junfeng Song, Xianshu Luo, Qing Fang, Lianxi Jia, Xiaoguang Tu, Tsung-Yang Liow, Mingbin Yu, Guo-Qiang Lo

Abstract:

We demonstrate a 1×4 coarse wavelength division-multiplexing (CWDM) planar concave grating multiplexer/demultiplexer and its application in re-configurable optical add/drop multiplexer (ROADM) system in silicon-on-insulator substrate. The wavelengths of the demonstrated concave grating multiplexer align well with the ITU-T standard. We demonstrate a prototype of ROADM comprising two such concave gratings and four wide-band thermo-optical MZI switches. Undercut technology which removes the underneath silicon substrate is adopted in optical switches in order to minimize the operation power. For all the thermal heaters, the operation voltage is smaller than 1.5 V, and the switch power is ~2.4 mW. High throughput pseudorandom binary sequence (PRBS) data transmission with up to 100 Gb/s is demonstrated, showing the high-performance ROADM functionality.

Keywords: ROADM, Optical switch, low power consumption, Integrated devices.

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