Search results for: Keivan Karimlou

Authors: Keivan Karimlou, Nemat Hassani, Abdollah Rashidi Mehrabadi

Abstract:

Climate change, industrial bloom, population growth and mismanagement are the most important factors that lead to water shortages around the world. Water shortages often lead to forced immigration, war, and thirst and hunger, especially in developing countries. One of the simplest solutions to solve the water shortage issues around the world is transferring water from one watershed to another; however it may not be a suitable solution. Water managers around the world use supply and demand management methods to decrease the incidence of water shortage in a sustainable manner. But as a matter of economic constraints, they must define a method to select the best possible action to reduce and limit water shortages. The following paper recognizes different kinds of criteria to select the best possible policy for reducing water shortage in mega cities by examining a comprehensive literature review.

Keywords: Criteria, management, shortage, sustainable, water.

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Authors: Begol, Moslem, Maghooli, Keivan

Abstract:

Image Edge Detection is one of the most important parts of image processing. In this paper, by fuzzy technique, a new method is used to improve digital image edge detection. In this method, a 3x3 mask is employed to process each pixel by means of vicinity. Each pixel is considered a fuzzy input and by examining fuzzy rules in its vicinity, the edge pixel is specified and by utilizing calculation algorithms in image processing, edges are displayed more clearly. This method shows significant improvement compared to different edge detection methods (e.g. Sobel, Canny).

Keywords: Fuzzy Systems, Edge Detection, Fuzzy edgedetection

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Authors: Mehdi Hosseinzadeh, Amir Sabbagh Molahosseini, Keivan Navi

Abstract:

In this paper, a new reverse converter for the moduli set {2n, 2n–1, 2n–1–1} is presented. We improved a previously introduced conversion algorithm for deriving an efficient hardware design for reverse converter. Hardware architecture of the proposed converter is based on carry-save adders and regular binary adders, without the requirement for modular adders. The presented design is faster than the latest introduced reverse converter for moduli set {2n, 2n–1, 2n–1–1}. Also, it has better performance than the reverse converters for the recently introduced moduli set {2n+1–1, 2n, 2n–1}

Keywords: Residue arithmetic, Residue number system, Residue-to-Binary converter, Reverse converter

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Authors: Mehdi Hosseinzadeh, Amir Sabbagh Molahosseini, Keivan Navi

Abstract:

The residue number system (RNS) is popular in high performance computation applications because of its carry-free nature. The challenges of RNS systems design lie in the moduli set selection and in the reverse conversion from residue representation to weighted representation. In this paper, we proposed a fully parallel reverse conversion algorithm for the moduli set {rn - 2, rn - 1, rn}, based on simple mathematical relationships. Also an efficient hardware realization of this algorithm is presented. Our proposed converter is very faster and results to hardware savings, compared to the other reverse converters.

Keywords: Reverse converter, residue to weighted converter, residue number system, multiple-valued logic, computer arithmetic.

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Authors: Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Keivan Navi

Abstract:

In this paper we present two novel 1-bit full adder cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output structures are used to design the adder blocks. Characteristic of dynamic logic leads to higher speeds than the other standard static full adder cells. Using HSpice and 0.18┬Ám CMOS technology exhibits a significant decrease in the cell delay which can result in a considerable reduction in the power-delay product (PDP). The PDP of Multi-Output design at 1.8v power supply is around 0.15 femto joule that is 5% lower than conventional dynamic full adder cell and at least 21% lower than other static full adders.

Keywords: Bridge Style, Dynamic Logic, Full Adder, HighSpeed, Multi Output, NP-CMOS, Zipper.

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Authors: Keivan Abdollahi, Alireza Mortezaei

Abstract:

The main objective of seismic rehabilitation in the foundations is decreasing the range of horizontal and vertical vibrations and omitting high frequencies contents under the seismic loading. In this regard, the advantages of micropiles network is utilized. Reduction in vibration range of foundation can be achieved by using high dynamic rigidness module such as deep foundations. In addition, natural frequency of pile and soil system increases in regard to rising of system rigidness. Accordingly, the main strategy is decreasing of horizontal and vertical seismic vibrations of the structure. In this case, considering the impact of foundation, pile and improved soil foundation is a primary concern. Therefore, in this paper, effective factors are studied on the seismic rehabilitation of foundations applying network micropiles in sandy soils with nonlinear reaction.

Keywords: Micropile network, rehabilitation, vibration, seismic load.

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Authors: Somayeh Timarchi, Keivan Navi

Abstract:

Efficient modulo 2n+1 adders are important for several applications including residue number system, digital signal processors and cryptography algorithms. In this paper we present a novel modulo 2n+1 addition algorithm for a recently represented number system. The proposed approach is introduced for the reduction of the power dissipated. In a conventional modulo 2n+1 adder, all operands have (n+1)-bit length. To avoid using (n+1)-bit circuits, the diminished-1 and carry save diminished-1 number systems can be effectively used in applications. In the paper, we also derive two new architectures for designing modulo 2n+1 adder, based on n-bit ripple-carry adder. The first architecture is a faster design whereas the second one uses less hardware. In the proposed method, the special treatment required for zero operands in Diminished-1 number system is removed. In the fastest modulo 2n+1 adders in normal binary system, there are 3-operand adders. This problem is also resolved in this paper. The proposed architectures are compared with some efficient adders based on ripple-carry adder and highspeed adder. It is shown that the hardware overhead and power consumption will be reduced. As well as power reduction, in some cases, power-delay product will be also reduced.

Keywords: Modulo 2n+1 arithmetic, residue number system, low power, ripple-carry adders.

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Authors: Mehdi Hosseinzadeh, Somayyeh Jafarali Jassbi, Keivan Navi

Abstract:

Residue Number System (RNS) is a modular representation and is proved to be an instrumental tool in many digital signal processing (DSP) applications which require high-speed computations. RNS is an integer and non weighted number system; it can support parallel, carry-free, high-speed and low power arithmetic. A very interesting correspondence exists between the concepts of Multiple Valued Logic (MVL) and Residue Number Arithmetic. If the number of levels used to represent MVL signals is chosen to be consistent with the moduli which create the finite rings in the RNS, MVL becomes a very natural representation for the RNS. There are two concerns related to the application of this Number System: reaching the most possible speed and the largest dynamic range. There is a conflict when one wants to resolve both these problem. That is augmenting the dynamic range results in reducing the speed in the same time. For achieving the most performance a method is considere named “One-Hot Residue Number System" in this implementation the propagation is only equal to one transistor delay. The problem with this method is the huge increase in the number of transistors they are increased in order m² . In real application this is practically impossible. In this paper combining the Multiple Valued Logic and One-Hot Residue Number System we represent a new method to resolve both of these two problems. In this paper we represent a novel design of an OHRNS-based adder circuit. This circuit is useable for Multiple Valued Logic moduli, in comparison to other RNS design; this circuit has considerably improved the number of transistors and power consumption.

Keywords: Computer Arithmetic, Residue Number System, Multiple Valued Logic, One-Hot, VLSI.

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Authors: Keivan Beheshti Maal, Rasoul Shafiei, Noushin Kabiri

Abstract:

Vinegar or sour wine is a product of alcoholic and subsequent acetous fermentation of sugary precursors derived from several fruits or starchy substrates. This delicious food additive and supplement contains not less than 4 grams of acetic acid in 100 cubic centimeters at 20°C. Among the large number of bacteria that are able to produce acetic acid, only few genera are used in vinegar industry most significant of which are Acetobacter and Gluconobacter. In this research we isolated and identified an Acetobacter strain from Iranian apricot, a very delicious and sensitive summer fruit to decay, we gathered from fruit's stores in Isfahan, Iran. The main culture media we used were Carr, GYC, Frateur and an industrial medium for vinegar production. We isolated this strain using a novel miniature fermentor we made at Pars Yeema Biotechnologists Co., Isfahan Science and Technology Town (ISTT), Isfahan, Iran. The microscopic examinations of isolated strain from Iranian apricot showed gram negative rods to cocobacilli. Their catalase reaction was positive and oxidase reaction was negative and could ferment ethanol to acetic acid. Also it showed an acceptable growth in 5%, 7% and 9% ethanol concentrations at 30°C using modified Carr media after 24, 48 and 96 hours incubation respectively. According to its tolerance against high concentrations of ethanol after four days incubation and its high acetic acid production, 8.53%, after 144 hours, this strain could be considered as a suitable industrial strain for a production of a new type of vinegar, apricot vinegar, with a new and delicious taste. In conclusion this is the first report of isolation and identification of an Acetobacter strain from Iranian apricot with a very good tolerance against high ethanol concentrations as well as high acetic acid productivity in an acceptable incubation period of time industrially. This strain could be used in vinegar industry to convert apricot spoilage to a beneficiary product and mentioned characteristics have made it as an amenable strain in food and agricultural biotechnology.

Keywords: Acetic Acid Bacteria, Acetobacter, Fermentation, Food and Agricultural Biotechnology, Iranian Apricot, Vinegar.

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