Search results for: High Power Application

Authors: Wahab Ali Shah, Junjia He

Abstract:

Transferring electrical power without any wiring has been a dream since late 19^th century. There were some advances in this area as to know more about microwave systems. However, this subject has recently become very attractive due to their practiScal systems. There are low power applications such as charging the batteries of contactless tooth brushes or implanted devices, and higher power applications such as charging the batteries of electrical automobiles or buses. In the first group of applications operating frequencies are in microwave range while the frequency is lower in high power applications. In the latter, the concept is also called inductive power transfer. The aim of the paper is to have an overview of the inductive power transfer for electrical vehicles with a special concentration on coil design and power converter simulation for static charging. Coil design is very important for an efficient and safe power transfer. Coil design is one of the most critical tasks. Power converters are used in both side of the system. The converter on the primary side is used to generate a high frequency voltage to excite the primary coil. The purpose of the converter in the secondary is to rectify the voltage transferred from the primary to charge the battery. In this paper, an inductive power transfer system is studied. Inductive power transfer is a promising technology with several possible applications. Operation principles of these systems are explained, and components of the system are described. Finally, a single phase 2 kW system was simulated and results were presented. The work presented in this paper is just an introduction to the concept. A reformed compensation network based on traditional inductor-capacitor-inductor (LCL) topology is proposed to realize robust reaction to large coupling variation that is common in dynamic wireless charging application. In the future, this type compensation should be studied. Also, comparison of different compensation topologies should be done for the same power level.

Keywords: Coil design, contactless charging, electrical automobiles, inductive power transfer, operating frequency.

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Authors: Guiheng Zhang, Wei Zhang, Jun Fu, Yudong Wang

Abstract:

A 900 MHz three-stage SiGe power amplifier (PA) with high power gain is presented in this paper. Volterra Series is applied to analyze nonlinearity sources of SiGe HBT device model clearly. Meanwhile, the influence of operating current to IMD3 is discussed. Then a β-helper current mirror bias circuit is applied to improve linearity, since the β-helper current mirror bias circuit can offer stable base biasing voltage. Meanwhile, it can also work as predistortion circuit when biasing voltages of three bias circuits are fine-tuned, by this way, the power gain and operating current of PA are optimized for best linearity. The three power stages which fabricated by 0.18 μm SiGe technology are bonded to the printed circuit board (PCB) to obtain impedances by Load-Pull system, then matching networks are done for best linearity with discrete passive components on PCB. The final measured three-stage PA exhibits 21.1 dBm of output power at 1 dB compression point (OP1dB) with power added efficiency (PAE) of 20.6% and 33 dB power gain under 3.3 V power supply voltage.

Keywords: High gain power amplifier, linearization bias circuit, SiGe HBT model, Volterra Series.

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Authors: Pawel P. Czapski, Andrzej Sluzek

Abstract:

This paper presents preliminary results regarding system-level power awareness for FPGA implementations in wireless sensor networks. Re-configurability of field programmable gate arrays (FPGA) allows for significant flexibility in its applications to embedded systems. However, high power consumption in FPGA becomes a significant factor in design considerations. We present several ideas and their experimental verifications on how to optimize power consumption at high level of designing process while maintaining the same energy per operation (low-level methods can be used additionally). This paper demonstrates that it is possible to estimate feasible power consumption savings even at the high level of designing process. It is envisaged that our results can be also applied to other embedded systems applications, not limited to FPGA-based.

Keywords: Power optimization, FPGA, system-level designing, wireless sensor networks.

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Authors: Mohd Iqbal Ridwan, Kerk Lee Yen, Aminuddin Musa, Bahisham Yunus

Abstract:

Protective relays are components of a protection system in a power system domain that provides decision making element for correct protection and fault clearing operations. Failure of the protection devices may reduce the integrity and reliability of the power system protection that will impact the overall performance of the power system. Hence it is imperative for power utilities to assess the reliability of protective relays to assure it will perform its intended function without failure. This paper will discuss the application of reliability analysis using statistical method called Life Data Analysis in Tenaga Nasional Berhad (TNB), a government linked power utility company in Malaysia, namely Transmission Division, to assess and evaluate the reliability of numerical overcurrent protective relays from two different manufacturers.

Keywords: Life data analysis, Protective relays, Reliability, Weibull Distribution.

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Authors: Grigorios D. Dimitroulakos, N. D. Zervas, N. Sklavos, Costas E. Goutis

Abstract:

In this paper, the implementation of low power, high throughput convolutional filters for the one dimensional Discrete Wavelet Transform and its inverse are presented. The analysis filters have already been used for the implementation of a high performance DWT encoder [15] with minimum memory requirements for the JPEG 2000 standard. This paper presents the design techniques and the implementation of the convolutional filters included in the JPEG2000 standard for the forward and inverse DWT for achieving low-power operation, high performance and reduced memory accesses. Moreover, they have the ability of performing progressive computations so as to minimize the buffering between the decomposition and reconstruction phases. The experimental results illustrate the filters- low power high throughput characteristics as well as their memory efficient operation.

Keywords: Discrete Wavelet Transform; JPEG2000 standard; VLSI design; Low Power-Throughput-optimized filters

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Authors: Ankit Mitra

Abstract:

An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.

Keywords: CMOS, TSPC, MTCMOS, ALU, Clock gating, power gating, pipelining.

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Authors: Omid Borazjani, Mahmoud Roosta, Khodakhast Isapour, Ali Reza Rajabi

Abstract:

This paper presents an application of Artificial Neural Network (ANN) algorithm for improving power system voltage stability. The training data is obtained by solving several normal and abnormal conditions using the Linear Programming technique. The selected objective function gives minimum deviation of the reactive power control variables, which leads to the maximization of minimum Eigen value of load flow Jacobian. The considered reactive power control variables are switchable VAR compensators, OLTC transformers and excitation of generators. The method has been implemented on a modified IEEE 30-bus test system. The results obtain from the test clearly show that the trained neural network is capable of improving the voltage stability in power system with a high level of precision and speed.

Keywords: Artificial Neural Network (ANN), Load Flow, Voltage Stability, Power Systems.

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Authors: B. Sathyanandhi, P. M. Balasubramaniam

Abstract:

This paper presents Buck-Boost converter topology to maintain the input power factor by using the power factor stage control and regulation stage control. Suppose, if we are using the RL load the power factor will be reduced due to the presence of total harmonic distortion in the current wave. To improve the power factor the current waveform should follow the fundamental component of the voltage waveform. These can be achieved by using the high -frequency power converter. Based on the resonant circuit the converter is able to perform the function of Buck, Boost, and buck-boost converter. Here ,we have used Buck-Boost converter, because, the buck-boost converter has more advantages than the boost converter. Here the switching action of the power converter can  take place by using the external zero comparator PFC stage control. The power converter consisting of the resonant  circuit which is used to control the output voltage gain of the converter. The power converter is operated at a very high switching frequency in the range of 400KHz in order to overcome the switching losses of the power converter. Due to  presence of high switching frequency, the power factor will improve. Therefore, the total harmonics distortion present in the current waveform has also reduced. These results has generated in the form of simulation by using MATLAB/SIMULINK software.  Similar to the Buck and Boost converters, the operation of the Buck-Boost has best understood, in terms of the inductor's "reluctance" for allowing rapid change in current, which also reduces the Total Harmonic Distortion (THD) in the input current waveform, which can improve the input Power factor, based on the type of load used.

Keywords: Buck-boost converter, High switching frequency, Power factor correction, power factor correction stage Regulation stage, Total harmonic distortion (THD).

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Authors: Kamaraju.M, Lal Kishore.K, Tilak.A.V.N

Abstract:

The general purpose processors that are used in embedded systems must support constraints like execution time, power consumption, code size and so on. On the other hand an Application Specific Instruction-set Processor (ASIP) has advantages in terms of power consumption, performance and flexibility. In this paper, a 16-bit Application Specific Instruction-set processor for the sensor data transfer is proposed. The designed processor architecture consists of on-chip transmitter and receiver modules along with the processing and controlling units to enable the data transmission and reception on a single die. The data transfer is accomplished with less number of instructions as compared with the general purpose processor. The ASIP core operates at a maximum clock frequency of 1.132GHz with a delay of 0.883ns and consumes 569.63mW power at an operating voltage of 1.2V. The ASIP is implemented in Verilog HDL using the Xilinx platform on Virtex4.

Keywords: ASIP, Data transfer, Instruction set, Processor

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Authors: Jingjing Lan, Jun Zhou, Xin Liu

Abstract:

In this paper, a low-power digital controller for DC-DC power conversion was presented. The controller generates the pulse-width modulated (PWM) signal from digital inputs provided by analog-to-digital converter (ADC). An efficient and simple design scheme to develop the control unit was discussed. This method allows minimization of the consumed resources of the chip and it is based on direct digital design approach. In this application, with the proposed scheme, nearly half area and two-third of the power consumption was saved compared to the conventional schemes. This work illustrates the possibility of implementing low-power and area-efficient power management circuit using direct digital design based approach. 

Keywords: Buck converter, DC-DC power conversion, digital control, proportional-integral (PI) controller.

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Authors: Maged A. Mossallam

Abstract:

The objective from this paper is to design a solar thermal engine for space vehicles orbital control and electricity generation. A computational model is developed for the prediction of the solar thermal engine performance for different design parameters and conditions in order to enhance the engine efficiency. The engine is divided into two main subsystems. First, the concentrator dish which receives solar energy from the sun and reflects them to the cavity receiver. The second one is the cavity receiver which receives the heat flux reflected from the concentrator and transfers heat to the fluid passing over. Other subsystems depend on the application required from the engine. For thrust application, a nozzle is introduced to the system for the fluid to expand and produce thrust. Hydrogen is preferred as a working fluid in the thruster application. Results model developed is used to determine the thrust for a concentrator dish 4 meters in diameter (provides 10 kW of energy), focusing solar energy to a 10 cm aperture diameter cavity receiver. The cavity receiver outer length is 50 cm and the internal cavity is 47 cm in length. The suggested design material of the internal cavity is tungsten to withstand high temperature. The thermal model and analysis shows that the hydrogen temperature at the plenum reaches 2000oK after about 250 seconds for hot start operation for a flow rate of 0.1 g/sec.Using solar thermal engine as an electricity generation device on earth is also discussed. In this case a compressor and turbine are used to convert the heat gained by the working fluid (air) into mechanical power. This mechanical power can be converted into electrical power by using a generator.

Keywords: Concentrated Solar Energy, Orbital Control, Power Generation, Solar Thermal Engine, Space Vehicles Propulsion

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Authors: T. Tanitteerapan, E.Thanpo

Abstract:

This paper, a simple continuous conduction mode (CCM) pulse-width-modulated (PWM) controller for high power factor boost converters is introduced. The duty ratios were obtained by the comparison of a sensed signal from inductor current or switch current and a negative slope ramp carrier waveform in each switching period. Due to the proposed control requires only the inductor current or switch current sensor and the output voltage sensor, its circuit implementation was very simple. To verify the proposed control, the circuit experimentation of a 350 W boost converter with the proposed control was applied. From the results, the input current waveform was shaped to be closely sinusoidal, implying high power factor and low harmonics.

Keywords: High power factor converters, boost converters, low harmonic rectifiers, power factor correction, and current control.

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Authors: Ahmed Elsebaay, Maged A. Abu Adma, Mahmoud Ramadan

Abstract:

This study presents a technique clarifying the effect of ambient air temperature and loads power factor changing from standard values on electric generator power rating. The study introduces an optimized technique for selecting the correct electric generator power rating for certain application and operating site ambient temperature. The de-rating factors due to the previous effects will be calculated to be applied on a generator to select its power rating accurately to avoid unsafe operation and save its lifetime. The information in this paper provides a simple, accurate, and general method for synchronous generator selection and eliminates common errors.

Keywords: Ambient temperature, de-rating factor, electric generator, power factor.

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Authors: M. Almutairi, S. Hadjiloucas

Abstract:

The harmonic distortion of voltage is important in relation to power quality due to the interaction between the large diffusion of non-linear and time-varying single-phase and three-phase loads with power supply systems. However, harmonic distortion levels can be reduced by improving the design of polluting loads or by applying arrangements and adding filters. The application of passive filters is an effective solution that can be used to achieve harmonic mitigation mainly because filters offer high efficiency, simplicity, and are economical. Additionally, possible different frequency response characteristics can work to achieve certain required harmonic filtering targets. With these ideas in mind, the objective of this paper is to determine what size single tuned passive filters work in distribution networks best, in order to economically limit violations caused at a given point of common coupling (PCC). This article suggests that a single tuned passive filter could be employed in typical industrial power systems. Furthermore, constrained optimization can be used to find the optimal sizing of the passive filter in order to reduce both harmonic voltage and harmonic currents in the power system to an acceptable level, and, thus, improve the load power factor. The optimization technique works to minimize voltage total harmonic distortions (VTHD) and current total harmonic distortions (ITHD), where maintaining a given power factor at a specified range is desired. According to the IEEE Standard 519, both indices are viewed as constraints for the optimal passive filter design problem. The performance of this technique will be discussed using numerical examples taken from previous publications.

Keywords: Harmonics, passive filter, power factor, power quality.

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Authors: M. Aleshams, A. Shahsavandi

Abstract:

This paper describes a CMOS four-quadrant multiplier intended for use in the front-end receiver by utilizing the square-law characteristic of the MOS transistor in the saturation region. The circuit is based on 0.35 um CMOS technology simulated using HSPICE software. The mixer has a third-order inter the power consumption is 271uW from a single 1.2V power supply. One of the features of the proposed design is using two MOS transistors limitation to reduce the supply voltage, which leads to reduce the power consumption. This technique provides a GHz bandwidth response and low power consumption.

Keywords: RF-Mixer, Multiplier, cut-off frequency, power consumption

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Authors: Rachid.Dehini, Abdesselam.Bassou, Brahim.Ferdi

Abstract:

Active Power Filters (APFs) are today the most widely used systems to eliminate harmonics compensate power factor and correct unbalanced problems in industrial power plants. We propose to improve the performances of conventional APFs by using artificial neural networks (ANNs) for harmonics estimation. This new method combines both the strategies for extracting the three-phase reference currents for active power filters and DC link voltage control method. The ANNs learning capabilities to adaptively choose the power system parameters for both to compute the reference currents and to recharge the capacitor value requested by VDC voltage in order to ensure suitable transit of powers to supply the inverter. To investigate the performance of this identification method, the study has been accomplished using simulation with the MATLAB Simulink Power System Toolbox. The simulation study results of the new (SAPF) identification technique compared to other similar methods are found quite satisfactory by assuring good filtering characteristics and high system stability.

Keywords: Artificial Neural Networks (ANN), p-q theory, (SAPF), Harmonics, Total Harmonic Distortion.

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Authors: Nabil A. Ahmed

Abstract:

This paper presents a novel three-phase utility frequency to high frequency soft switching power conversion circuit with dual mode pulse width modulation and pulse density modulation for high power induction heating applications as melting of steel and non ferrous metals, annealing of metals, surface hardening of steel and cast iron work pieces and hot water producers, steamers and super heated steamers. This high frequency power conversion circuit can operate from three-phase systems to produce high current for high power induction heating applications under the principles of ZVS and it can regulate its ac output power from the rated value to a low power level. A dual mode modulation control scheme based on high frequency PWM in synchronization with the utility frequency positive and negative half cycles for the proposed high frequency conversion circuit and utility frequency pulse density modulation is produced to extend its soft switching operating range for wide ac output power regulation. A dual packs heat exchanger assembly is designed to be used in consumer and industrial fluid pipeline systems and it is proved to be suitable for the hot water, steam and super heated steam producers. Experiment and simulation results are given in this paper to verify the operation principles of the proposed ac conversion circuit and to evaluate its power regulation and conversion efficiency. Also, the paper presents a mutual coupling model of the induction heating load instead of equivalent transformer circuit model.

Keywords: Induction heating, three-phase, conversion circuit, pulse width modulation, pulse density modulation, high frequency, soft switching.

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Authors: Mohammed Amroune, Hadi Sebaa, Tarek Bouktir

Abstract:

Reactive power limit of power system is one of the major causes of voltage instability. The only way to save the system from voltage instability is to reduce the reactive power load or add additional reactive power to reaching the point of voltage collapse. In recent times, the application of FACTS devices is a very effective solution to prevent voltage instability due to their fast and very flexible control. In this paper, voltage stability assessment with SVC and TCSC devices is investigated and compared in the modified IEEE 30-bus test system. The fast voltage stability indicator (FVSI) is used to identify weakest bus and to assess the voltage stability of power system.

Keywords: SVC, TCSC, Voltage stability, Fast Voltage Stability Index (FVSI), Reactive power.

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Authors: Kang Chia Yang, Hushairi HJ Zen, Nur Ikhmar@Najemeen Binti Ayob

Abstract:

Power quality is used to describe the degree of consistency of electrical energy expected from generation source to point of use. The term power quality refers to a wide variety of electromagnetic phenomena that characterize the voltage and current at a given time and at a given location on the power system. Power quality problems can be defined as problem that results in failure of customer equipments, which manifests itself as an economic burden to users, or produces negative impacts on the environment. Voltage stability, power factor, harmonics pollution, reactive power and load unbalance are some of the factors that affect the consistency or the quality level. This research proposal proposes to investigate and analyze the causes and effects of power quality to homes and industries in Sarawak. The increasing application of electronics equipment used in the industries and homes has caused a big impact on the power quality. Many electrical devices are now interconnected to the power network and it can be observed that if the power quality of the network is good, then any loads connected to it will run smoothly and efficiently. On the other hand, if the power quality of the network is bad, then loads connected to it will fail or may cause damage to the equipments and reduced its lifetime. The outcome of this research will enable better and novel solutions of poor power quality to small industries and reduce damage of electrical devices and products in the industries.

Keywords: Power quality, power network, voltage dip.

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Authors: Pejman Hosseiniun, Rose Shayeghi, Iman Rahbari, Mohamad Reza Kalhor

Abstract:

CNFET has emerged as an alternative material to silicon for high performance, high stability and low power SRAM design in recent years. SRAM functions as cache memory in computers and many portable devices. In this paper, a new SRAM cell design based on CNFET technology is proposed. The proposed SRAM cell design for CNFET is compared with SRAM cell designs implemented with the conventional CMOS and FinFET in terms of speed, power consumption, stability, and leakage current. The HSPICE simulation and analysis show that the dynamic power consumption of the proposed 8T CNFET SRAM cell’s is reduced about 48% and the SNM is widened up to 56% compared to the conventional CMOS SRAM structure at the expense of 2% leakage power and 3% write delay increase.

Keywords: SRAM cell, CNFET, low power, HSPICE.

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Authors: Mohammad Hasan Raouf, Azim Nowbakht, Mohammad Bagher Haddadi, Mohammad Reza Tabatabaei

Abstract:

Power quality has become a very important issue recently due to the impact on electricity suppliers, equipment manufacturers and customers. Power quality is described as the variation of voltage, current and frequency in a power system. Voltage magnitude is one of the major factors that determine the quality of power. Indeed, custom power technology, the low-voltage counterpart of the more widely known flexible ac transmission system (FACTS) technology, aimed at high-voltage power transmission applications, has emerged as a credible solution to solve many problems relating to power quality problems. There are various power quality problems such as voltage sags, swells, flickers, interruptions and harmonics etc. Active Power Filter (APF) is one of the custom power devices and can mitigate harmonics, reactive power and unbalanced load currents originating from load side. In this study, an extensive review of APF studies, the advantages and disadvantages of each introduced methods are presented. The study also helps the researchers to choose the optimum control techniques and power circuit configuration for APF applications.

Keywords: Power Quality, Custom Power, Active Filter, Control Approach.

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Authors: Guo-Ming Sung, Naga Raju Naik R.

Abstract:

Paper presents a low power, high speed, sense-amplifier based flip-flop (SAFF). The flip-flop’s power con-sumption and delay are greatly reduced by employing a new conditionally precharge sense-amplifier stage and a single-ended latch stage. Glitch-free and contention-free latch operation is achieved by using a conditional cut-off strategy. The design uses fewer transistors, has a lower clock load, and has a simple structure, all of which contribute to a near-zero setup time. When compared to previous flip-flop structures proposed for similar input/output conditions, this design’s performance and overall PDP have improved. The post layout simulation of the circuit uses 2.91µW of power and has a delay of 65.82 ps. Overall, the power-delay product has seen some enhancements. Cadence Virtuoso Designing tool with CMOS 90nm technology are used for all designs.

Keywords: high-speed, low-power, flip-flop, sense-amplifier

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Authors: Mohamed Azab

Abstract:

In this paper a new maximum power point tracking algorithm for photovoltaic arrays is proposed. The algorithm detects the maximum power point of the PV. The computed maximum power is used as a reference value (set point) of the control system. ON/OFF power controller with hysteresis band is used to control the operation of a Buck chopper such that the PV module always operates at its maximum power computed from the MPPT algorithm. The major difference between the proposed algorithm and other techniques is that the proposed algorithm is used to control directly the power drawn from the PV. The proposed MPPT has several advantages: simplicity, high convergence speed, and independent on PV array characteristics. The algorithm is tested under various operating conditions. The obtained results have proven that the MPP is tracked even under sudden change of irradiation level.

Keywords: Photovoltaic, maximum power point tracking, MPPT.

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Authors: Reza Sedaghati, Mojtaba Hakimzadeh, Mohammad Hasan Raouf, Mostafa Mirzadeh

Abstract:

Nowadays the growth of distributed generation within the bulk power system is feasible by using the optimal control of the transmission lines power flow. Static Synchronous Compensators (STATCOM) is effective for improving voltage stability but it can only exchange reactive power with the power grid. The integration of Superconducting Magnetic Energy Storage (SMES) with a STATCOM can extend the traditional STATCOM capabilities to four-quadrant bulk power system power flow control and providing exchange both the active and reactive power related to the STATCOM with the ac network. This paper shows how the SMES system can be connected to the ac system via the DC bus of a STATCOM and also analyzes how the integration of STATCOM and SMES allows the bus voltage regulation and power oscillation damping (POD) to be achieved simultaneously. The dynamic performance of the integrated STATCOM-SMES is evaluated through simulation by using PSCAD/EMTDC software and the compensation effectiveness of this integrated compensator is shown.

Keywords: STATCOM-SMES compensator, Power Oscillation Damping (POD), stabilizing, signal, voltage.

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Authors: Kanhu Charan Bhuyan, Subhransu Padhee, Rajesh Kumar Patjoshi, Kamalakanta Mahapatra

Abstract:

Fuel cell is an emerging technology in the field of renewable energy sources which has the capacity to replace conventional energy generation sources. Fuel cell utilizes hydrogen energy to produce electricity. The electricity generated by the fuel cell can’t be directly used for a specific application as it needs proper power conditioning. Moreover, the output power fluctuates with different operating conditions. To get a stable output power at an economic rate, power conditioning circuit is essential for fuel cell. This paper implements a two-staged power conditioning unit for fuel cell based distributed generation using hysteresis current control technique.

Keywords: Fuel cell, power conditioning unit, hysteresis control.

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Authors: Sanjay Singh, M Sathish Kumar, H. S Mruthyunjaya

Abstract:

Multicarrier transmission system such as Orthogonal Frequency Division Multiplexing (OFDM) is a promising technique for high bit rate transmission in wireless communication system. OFDM is a spectrally efficient modulation technique that can achieve high speed data transmission over multipath fading channels without the need for powerful equalization techniques. However the price paid for this high spectral efficiency and less intensive equalization is low power efficiency. OFDM signals are very sensitive to nonlinear effects due to the high Peak-to-Average Power Ratio (PAPR), which leads to the power inefficiency in the RF section of the transmitter. This paper investigates the effect of PAPR reduction on the performance parameter of multicarrier communication system. Performance parameters considered are power consumption of Power Amplifier (PA) and Digital-to-Analog Converter (DAC), power amplifier efficiency, SNR of DAC and BER performance of the system. From our analysis it is found that irrespective of PAPR reduction technique being employed, the power consumption of PA and DAC reduces and power amplifier efficiency increases due to reduction in PAPR. Moreover, it has been shown that for a given BER performance the requirement of Input-Backoff (IBO) reduces with reduction in PAPR.

Keywords: BER, Crest Factor (CF), Digital-to-Analog Converter(DAC), Input-Backoff (IBO), Orthogonal Frequency Division Multiplexing(OFDM), Peak-to-Average Power Ratio (PAPR), PowerAmplifier efficiency, SNR

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Authors: M.Hosseinghadiry, H. Mohammadi, M.Nadisenejani

Abstract:

with increasing circuits- complexity and demand to use portable devices, power consumption is one of the most important parameters these days. Full adders are the basic block of many circuits. Therefore reducing power consumption in full adders is very important in low power circuits. One of the most powerconsuming modules in full adders is XOR/XNOR circuit. This paper presents two new full adders based on two new logic approaches. The proposed logic approaches use one XOR or XNOR gate to implement a full adder cell. Therefore, delay and power will be decreased. Using two new approaches and two XOR and XNOR gates, two new full adders have been implemented in this paper. Simulations are carried out by HSPICE in 0.18μm bulk technology with 1.8V supply voltage. The results show that the ten-transistors proposed full adder has 12% less power consumption and is 5% faster in comparison to MB12T full adder. 9T is more efficient in area and is 24% better than similar 10T full adder in term of power consumption. The main drawback of the proposed circuits is output threshold loss problem.

Keywords: Full adder, XNOR, Low power, High performance, Very Large Scale Integrated Circuit.

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Authors: José E. Q. Souza, Marcio Fontana, Antonio C. C. Lima

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This paper presents analysis and characterization of a piezoelectric micro-generator for energy harvesting application. A low-cost experimental prototype was designed to operate as piezoelectric micro-generator in the laboratory. An input acceleration of 9.8m/s2 using a sine signal (peak-to-peak voltage: 1V, offset voltage: 0V) at frequencies ranging from 10Hz to 160Hz generated a maximum average power of 432.4μW (linear mass position = 25mm) and an average power of 543.3μW (angular mass position = 35°). These promising results show that the prototype can be considered for low consumption load application as an energy harvesting micro-generator.

Keywords: Piezoelectric, microgenerator, energy harvesting, cantilever beam.

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Authors: Khaled M. El Naggar

Abstract:

This paper introduces a digital method for fault section identification in transmission lines. The method uses digital set of the measured short circuit current to locate faults in electrical power systems. The digitized current is used to construct a set of overdetermined system of equations. The problem is then constructed and solved using the proposed digital optimization technique to find the fault distance. The proposed optimization methodology is an application of simulated annealing optimization technique. The method is tested using practical case study to evaluate the proposed method. The accurate results obtained show that the algorithm can be used as a powerful tool in the area of power system protection.

Keywords: Optimization, estimation, faults, measurement, high voltage, simulated annealing.

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Authors: R .H. Talwekar, S. S Limaye

Abstract:

The designing of charge pump with high gain Op- Amp is a challenging task for getting faithful response .Design of high performance phase locked loop require ,a design of high performance charge pump .We have designed a operational amplifier for reducing the error caused by high speed glitch in a transistor and mismatch currents . A separate Op-Amp has designed in 180 nm CMOS technology by CADENCE VIRTUOSO tool. This paper describes the design of high performance charge pump for GHz CMOS PLL targeting orthogonal frequency division multiplexing (OFDM) application. A high speed low power consumption Op-Amp with more than 500 MHz bandwidth has designed for increasing the speed of charge pump in Phase locked loop.

Keywords: Charge pump (CP) Orthogonal frequency divisionmultiplexing (OFDM), Phase locked loop (PLL), Phase frequencydetector (PFD), Voltage controlled oscillator (VCO),

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