Search results for: Digital All-Pass Filter.

Authors: Ju-Hong Lee, Chong-Jia Ciou

Abstract:

This paper deals with the problem of two-dimensional (2-D) recursive two-channel quincunx quadrature mirror filter (QQMF) banks design. The analysis and synthesis filters of the 2-D recursive QQMF bank are composed of 2-D recursive digital allpass lattice filters (DALFs) with symmetric half-plane (SHP) support regions. Using the 2-D doubly complementary half-band (DC-HB) property possessed by the analysis and synthesis filters, we facilitate the design of the proposed QQMF bank. For finding the coefficients of the 2-D recursive SHP DALFs, we present a structure of 2-D recursive digital allpass filters by using 2-D SHP recursive digital all-pass lattice filters (DALFs). The novelty of using 2-D SHP recursive DALFs to construct a 2-D recursive QQMF bank is that the resulting 2-D recursive QQMF bank provides better performance than the existing 2-D recursive QQMF banks. Simulation results are also presented for illustration and comparison.

Keywords: All-pass digital filter, doubly complementary, lattice structure, symmetric half-plane digital filter, quincunx QMF bank.

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Authors: Supayotin Na Songkla, Winai Jaikla

Abstract:

This article presents a resistorless current-mode firstorder allpass filter based on second generation current controlled current conveyors (CCCIIs). The features of the circuit are that: the pole frequency can be electronically controlled via the input bias current: the circuit description is very simple, consisting of 2 CCCIIs and single grounded capacitor, without any external resistors and component matching requirements. Consequently, the proposed circuit is very appropriate to further develop into an integrated circuit. Low input and high output impedances of the proposed configuration enable the circuit to be cascaded in current-mode without additional current buffers. The PSpice simulation results are depicted. The given results agree well with the theoretical anticipation. The application example as a current-mode quadrature oscillator is included.

Keywords: First-order all pass filter, current-mode, CCCII.

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Authors: Phuoc Si Nguyen

Abstract:

Frequency transformation with Pascal matrix equations is a method for transforming an electronic filter (analogue or digital) into another filter. The technique is based on frequency transformation in the s-domain, bilinear z-transform with pre-warping frequency, inverse bilinear transformation and a very useful application of the Pascal’s triangle that simplifies computing and enables calculation by hand when transforming from one filter to another. This paper will introduce two methods to transform a filter into a digital filter: frequency transformation from the s-domain into the z-domain; and frequency transformation in the z-domain. Further, two Pascal matrix equations are derived: an analogue to digital filter Pascal matrix equation and a digital to digital filter Pascal matrix equation. These are used to design a desired digital filter from a given filter.

Keywords: Frequency transformation, Bilinear z-transformation, Pre-warping frequency, Digital filters, Analog filters, Pascal’s triangle.

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Authors: Ju-Hong Lee, Chong-Jia Ciou, Yuan-Hau Yang

Abstract:

This paper deals with the problem of two-dimensional (2-D) recursive doubly complementary (DC) digital filter design. We present a structure of 2-D recursive DC filters by using 2-D symmetric half-plane (SHP) recursive digital all-pass lattice filters (DALFs). The novelty of using 2-D SHP recursive DALFs to construct a 2-D recursive DC digital lattice filter is that the resulting 2-D SHP recursive DC digital lattice filter provides better performance than the existing 2-D SHP recursive DC digital filter. Moreover, the proposed structure possesses a favorable 2-D DC half-band (DC-HB) property that allows about half of the 2-D SHP recursive DALF’s coefficients to be zero. This leads to considerable savings in computational burden for implementation. To ensure the stability of a designed 2-D SHP recursive DC digital lattice filter, some necessary constraints on the phase of the 2-D SHP recursive DALF during the design process are presented. Design of a 2-D diamond-shape decimation/interpolation filter is presented for illustration and comparison.

Keywords: All-pass digital filter, doubly complementary, lattice structure, symmetric half-plane digital filter, sampling rate conversion.

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Authors: S. Seyedtabaii, E. Seyedtabaii

Abstract:

Rounding of coefficients is a common practice in hardware implementation of digital filters. Where some coefficients are very close to zero or one, as assumed in this paper, this rounding action also leads to some computation reduction. Furthermore, if the discarded coefficient is of high order, a reduced order filter is obtained, otherwise the order does not change but computation is reduced. In this paper, the Least Squares approximation to rounded (or discarded) coefficient FIR filter is investigated. The result also succinctly extended to general type of FIR filters.

Keywords: Digital filter, filter approximation, least squares, model order reduction.

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Authors: Kah-Hyong Chang, Xin Liu, Jia Hao Cheong, Saisundar Sankaranarayanan, Dexing Pang, Hongzhao Zheng

Abstract:

A digital baseband Application-Specific Integrated Circuit (ASIC) (yclic Redundancy Checkis developed for a microchip transponder to transmit signals and temperature levels from biomedical monitoring devices. The transmission protocol is adapted from the ISO/IEC 11784/85 standard. The module has a decimation filter that employs only a single adder-subtractor in its datapath. The filtered output is coded with cyclic redundancy check and transmitted through backscattering Load Shift Keying (LSK) modulation to a reader. Fabricated using the 0.18-μm CMOS technology, the module occupies 0.116 mm² in chip area (digital baseband: 0.060 mm², decimation filter: 0.056 mm²), and consumes a total of less than 0.9 μW of power (digital baseband: 0.75 μW, decimation filter: 0.14 μW).

Keywords: Biomedical sensor, decimation filter, Radio Frequency Integrated Circuit (RFIC) baseband, temperature sensor.

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Authors: Ju-Hong Lee, Yi-Lin Shieh

Abstract:

The paper deals with the minimax design of two-channel linear-phase (LP) quadrature mirror filter (QMF) banks using infinite impulse response (IIR) digital all-pass filters (DAFs). Based on the theory of two-channel QMF banks using two IIR DAFs, the design problem is appropriately formulated to result in an appropriate Chebyshev approximation for the desired group delay responses of the IIR DAFs and the magnitude response of the low-pass analysis filter. Through a frequency sampling and iterative approximation method, the design problem can be solved by utilizing a weighted least squares approach. The resulting two-channel QMF banks can possess approximately LP response without magnitude distortion. Simulation results are presented for illustration and comparison.

Keywords: Chebyshev approximation, Digital All-Pass Filter, Quadrature Mirror Filter, Weighted Least Squares.

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Authors: Hu Haibo, Liu Yi, He Ming

Abstract:

The binary phase-only filter digital watermarking embeds the phase information of the discrete Fourier transform of the image into the corresponding magnitudes for better image authentication. The paper proposed an approach of how to implement watermark embedding by quantizing the magnitude, with discussing how to regulate the quantization steps based on the frequencies of the magnitude coefficients of the embedded watermark, and how to embed the watermark at low frequency quantization. The theoretical analysis and simulation results show that algorithm flexibility, security, watermark imperceptibility and detection performance of the binary phase-only filter digital watermarking can be effectively improved with quantization based watermark embedding, and the robustness against JPEG compression will also be increased to some extent.

Keywords: binary phase-only filter, discrete Fourier transform, digital watermarking, image authentication, quantization.

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Authors: Mohd Amaluddin Yusoff

Abstract:

In this paper, we consider the design of pulse shaping filter using orthogonal Hermite-Rodriguez basis functions. The pulse shaping filter design problem has been formulated and solved as a quadratic programming problem with linear inequality constraints. Compared with the existing approaches reported in the literature, the use of Hermite-Rodriguez functions offers an effective alternative to solve the constrained filter synthesis problem. This is demonstrated through a numerical example which is concerned with the design of an equalization filter for a digital transmission channel.

Keywords: channel equalization filter, Hermite-Rodriguez, pulseshaping filter, quadratic programming.

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Authors: Ying-Wen Bai, Ju-Maw Chen

Abstract:

To successfully provide a fast FIR filter with FTT algorithms, overlapped-save algorithms can be used to lower the computational complexity and achieve the desired real-time processing. As the length of the input block increases in order to improve the efficiency, a larger volume of zero padding will greatly increase the computation length of the FFT. In this paper, we use the overlapped block digital filtering to construct a parallel structure. As long as the down-sampling (or up-sampling) factor is an exact multiple lengths of the impulse response of a FIR filter, we can process the input block by using a parallel structure and thus achieve a low-complex fast FIR filter with overlapped-save algorithms. With a long filter length, the performance and the throughput of the digital filtering system will also be greatly enhanced.

Keywords: FIR Filter, Overlapped-save Algorithm, ParallelStructure

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Authors: Mohamed Al Mahdi Eshtawie, Masuri Bin Othman

Abstract:

Finite impulse response (FIR) filters have the advantage of linear phase, guaranteed stability, fewer finite precision errors, and efficient implementation. In contrast, they have a major disadvantage of high order need (more coefficients) than IIR counterpart with comparable performance. The high order demand imposes more hardware requirements, arithmetic operations, area usage, and power consumption when designing and fabricating the filter. Therefore, minimizing or reducing these parameters, is a major goal or target in digital filter design task. This paper presents an algorithm proposed for modifying values and the number of non-zero coefficients used to represent the FIR digital pulse shaping filter response. With this algorithm, the FIR filter frequency and phase response can be represented with a minimum number of non-zero coefficients. Therefore, reducing the arithmetic complexity needed to get the filter output. Consequently, the system characteristic i.e. power consumption, area usage, and processing time are also reduced. The proposed algorithm is more powerful when integrated with multiplierless algorithms such as distributed arithmetic (DA) in designing high order digital FIR filters. Here the DA usage eliminates the need for multipliers when implementing the multiply and accumulate unit (MAC) and the proposed algorithm will reduce the number of adders and addition operations needed through the minimization of the non-zero values coefficients to get the filter output.

Keywords: Pulse shaping Filter, Distributed Arithmetic, Optimization algorithm.

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Authors: Sangeeta Mandal, Rajib Kar, Durbadal Mandal, Sakti Prasad Ghoshal

Abstract:

In this paper, an optimal design of linear phase digital high pass finite impulse response (FIR) filter using Particle Swarm Optimization with Constriction Factor and Inertia Weight Approach (PSO-CFIWA) has been presented. In the design process, the filter length, pass band and stop band frequencies, feasible pass band and stop band ripple sizes are specified. FIR filter design is a multi-modal optimization problem. The conventional gradient based optimization techniques are not efficient for digital filter design. Given the filter specifications to be realized, the PSO-CFIWA algorithm generates a set of optimal filter coefficients and tries to meet the ideal frequency response characteristic. In this paper, for the given problem, the designs of the optimal FIR high pass filters of different orders have been performed. The simulation results have been compared to those obtained by the well accepted algorithms such as Parks and McClellan algorithm (PM), genetic algorithm (GA). The results justify that the proposed optimal filter design approach using PSOCFIWA outperforms PM and GA, not only in the accuracy of the designed filter but also in the convergence speed and solution quality.

Keywords: FIR Filter; PSO-CFIWA; PSO; Parks and McClellanAlgorithm, Evolutionary Optimization Technique; MagnitudeResponse; Convergence; High Pass Filter

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Authors: Kar Foo Chong, Pradeep K. Gopalakrishnan, T. Hui Teo

Abstract:

There are multiple ways to implement a decimator filter. This paper addresses usage of CIC (cascaded-integrator-comb) filter and HB (half band) filter as the decimator filter to reduce the frequency sample rate by factor of 64 and detail of the implementation step to realize this design in hardware. Low power design approach for CIC filter and half band filter will be discussed. The filter design is implemented through MATLAB system modeling, ASIC (application specific integrated circuit) design flow and verified using a FPGA (field programmable gate array) board and MATLAB analysis.

Keywords: CIC filter, decimation filter, half-band filter, lowpower.

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Authors: G. Ramana Murthy, C. Senthilpari, P. Velrajkumar, Lim Tien Sze

Abstract:

In this paper, a design methodology to implement low-power and high-speed 2nd order recursive digital Infinite Impulse Response (IIR) filter has been proposed. Since IIR filters suffer from a large number of constant multiplications, the proposed method replaces the constant multiplications by using addition/subtraction and shift operations. The proposed new 6T adder cell is used as the Carry-Save Adder (CSA) to implement addition/subtraction operations in the design of recursive section IIR filter to reduce the propagation delay. Furthermore, high-level algorithms designed for the optimization of the number of CSA blocks are used to reduce the complexity of the IIR filter. The DSCH3 tool is used to generate the schematic of the proposed 6T CSA based shift-adds architecture design and it is analyzed by using Microwind CAD tool to synthesize low-complexity and high-speed IIR filters. The proposed design outperforms in terms of power, propagation delay, area and throughput when compared with MUX-12T, MCIT-7T based CSA adder filter design. It is observed from the experimental results that the proposed 6T based design method can find better IIR filter designs in terms of power and delay than those obtained by using efficient general multipliers.

Keywords: CSA Full Adder, Delay unit, IIR filter, Low-Power, PDP, Parametric Analysis, Propagation Delay, Throughput, VLSI.

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Authors: Vishal Awasthi, Krishna Raj

Abstract:

Unwanted side effects because of spectral aliasing and spectral imaging during signal processing would be the major concern over the sampling rate alteration. Multirate-multistage implementation of digital filter could come about a large computational saving than single rate filter suitable for sample rate conversion. This implementation can further improve through high-level architectural transformation in circuit level. Reallocating registers and  relocating flip-flops across logic gates through retiming certainly a prominent sequential transformation technology, that optimize hardware circuits to achieve faster clocking speed without affecting the functionality. In this paper, we proposed an efficient compensated cascade Integrator comb (CIC) decimation filter structure that analyze the consequence of filter order variation which has a retimed FIR filter being compensator while using the cutset retiming technique and achieved an improvement in the passband droop by 14% to 39%, in computation time by 38.04%, 25.78%, 12.21%, 6.69% and 4.44% and reduction in path delay by 62.27%, 72%, 86.63%, 91.56% and 94.42% of 3, 6, 8, 12 and 24 order filter respectively than the non-retimed CIC compensation filter.

Keywords: Multirate Filtering, CIC decimation filter, Compensation theory, Retiming, Retiming algorithm, Filter order, Synchronous dataflow graph.

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Authors: S. Park, J. Hwang, K. Rou, E. Kim

Abstract:

In this paper, we consider a new particle filter inspired by biological evolution. In the standard particle filter, a resampling scheme is used to decrease the degeneracy phenomenon and improve estimation performance. Unfortunately, however, it could cause the undesired the particle deprivation problem, as well. In order to overcome this problem of the particle filter, we propose a novel filtering method called the genetic filter. In the proposed filter, we embed the genetic algorithm into the particle filter and overcome the problems of the standard particle filter. The validity of the proposed method is demonstrated by computer simulation.

Keywords: Particle filter, genetic algorithm, evolutionary algorithm.

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Authors: A. Diet, M. Villegas, G. Baudoin

Abstract:

This work concerns the measurements of a Bulk Acoustic Waves (BAW) emission filter S parameters and compare with prototypes simulated types. Thanks to HP-ADS, a co-simulation of filters- characteristics in a digital radio-communication chain is performed. Four cases of modulation schemes are studied in order to illustrate the impact of the spectral occupation of the modulated signal. Results of simulations and co-simulation are given in terms of Error Vector Measurements to be useful for a general sensibility analysis of 4th/3rd Generation (G.) emitters (wideband QAM and OFDM signals)

Keywords: RF architectures, BAW filters.

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Authors: M. Lakshmi, J. Senthil Kumar

Abstract:

Digital cameras to reduce cost, use an image sensor to capture color images. Color Filter Array (CFA) in digital cameras permits only one of the three primary (red-green-blue) colors to be sensed in a pixel and interpolates the two missing components through a method named demosaicking. Captured data is interpolated into a full color image and compressed in applications. Color interpolation before compression leads to data redundancy. This paper proposes a new Vector Quantization (VQ) technique to construct a VQ codebook with Differential Evolution (DE) Algorithm. The new technique is compared to conventional Linde- Buzo-Gray (LBG) method.

Keywords: Color Filter Array (CFA), Biorthogonal Wavelet, Vector Quantization (VQ), Differential Evolution (DE).

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Authors: Vishal Awasthi, Krishna Raj

Abstract:

Any digital processing performed on a signal with larger nyquist interval requires more computation than signal processing performed on smaller nyquist interval. The sampling rate alteration generates the unwanted effects in the system such as spectral aliasing and spectral imaging during signal processing. Multirate-multistage implementation of digital filter can result a significant computational saving than single rate filter designed for sample rate conversion. In this paper, we presented an efficient cascaded integrator comb (CIC) decimation filter that perform fast down sampling using signed digit adder algorithm with compensated frequency droop that arises due to aliasing effect during the decimation process. This proposed compensated CIC decimation filter structure with a hybrid signed digit (HSD) fast adder provide an improved performance in terms of down sampling speed by 65.15% than ripple carry adder (RCA) and reduced area and power by 57.5% and 0.01 % than signed digit (SD) adder algorithms respectively.

Keywords: Sampling rate conversion, Multirate Filtering, Compensation Theory, Decimation filter, CIC filter, Redundant signed digit arithmetic, Fast adders.

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Authors: V.R.Vijaykumar, P.T.Vanathi, P.Kanagasabapathy, D.Ebenezer

Abstract:

In this paper, a robust statistics based filter to remove salt and pepper noise in digital images is presented. The function of the algorithm is to detect the corrupted pixels first since the impulse noise only affect certain pixels in the image and the remaining pixels are uncorrupted. The corrupted pixels are replaced by an estimated value using the proposed robust statistics based filter. The proposed method perform well in removing low to medium density impulse noise with detail preservation upto a noise density of 70% compared to standard median filter, weighted median filter, recursive weighted median filter, progressive switching median filter, signal dependent rank ordered mean filter, adaptive median filter and recently proposed decision based algorithm. The visual and quantitative results show the proposed algorithm outperforms in restoring the original image with superior preservation of edges and better suppression of impulse noise

Keywords: Image denoising, Nonlinear filter, Robust Statistics, and Salt and Pepper Noise.

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Authors: Ju-Hong Lee, Yi-Lin Shieh

Abstract:

This paper deals with the optimal design of two-channel recursive parallelogram quadrature mirror filter (PQMF) banks. The analysis and synthesis filters of the PQMF bank are composed of two-dimensional (2-D) recursive digital all-pass filters (DAFs) with nonsymmetric half-plane (NSHP) support region. The design problem can be facilitated by using the 2-D doubly complementary half-band (DC-HB) property possessed by the analysis and synthesis filters. For finding the coefficients of the 2-D recursive NSHP DAFs, we appropriately formulate the design problem to result in an optimization problem that can be solved by using a weighted least-squares (WLS) algorithm in the minimax (L_∞) optimal sense. The designed 2-D recursive PQMF bank achieves perfect magnitude response and possesses satisfactory phase response without requiring extra phase equalizer. Simulation results are also provided for illustration and comparison.

Keywords: Parallelogram Quadrature Mirror Filter Bank, Doubly Complementary Filter, Nonsymmetric Half-Plane Filter, Weighted Least Squares Algorithm, Digital All-Pass Filter.

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Authors: Kar Foo Chong, Andreas Lee Astuti, Pradeep K. Gopalakrishnan, T. Hui Teo

Abstract:

This paper describes design of a digital feedback loop for a low switching frequency dc-dc switching converters. Low switching frequencies were selected in this design. A look up table for the digital PID (proportional integrator differentiator) compensator was implemented using Altera Stratix II with built-in ADC (analog-to-digital converter) to achieve this hardware realization. Design guidelines are given for the PID compensator, high frequency DPWM (digital pulse width modulator) and moving average filter.

Keywords: dc-dc converter, FPGA, PID, power management, .

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Authors: K.Ramesh, A.Nirmalkumar, G.Gurusamy

Abstract:

In this paper, a new model order reduction phenomenon is introduced at the design stage of linear phase digital IIR filter. The complexity of a system can be reduced by adopting the model order reduction method in their design. In this paper a mixed method of model order reduction is proposed for linear IIR filter. The proposed method employs the advantages of factor division technique to derive the reduced order denominator polynomial and the reduced order numerator is obtained based on the resultant denominator polynomial. The order reduction technique is used to reduce the delay units at the design stage of IIR filter. The validity of the proposed method is illustrated with design example in frequency domain and stability is also examined with help of nyquist plot.

Keywords: Error index (J), Factor division method, IIR filter, Nyquist plot, Order reduction.

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Authors: Sangeeta Mondal, Vasundhara, Rajib Kar, Durbadal Mandal, S. P. Ghoshal

Abstract:

This paper presents an optimal design of linear phase digital high pass finite impulse response (FIR) filter using Improved Particle Swarm Optimization (IPSO). In the design process, the filter length, pass band and stop band frequencies, feasible pass band and stop band ripple sizes are specified. FIR filter design is a multi-modal optimization problem. An iterative method is introduced to find the optimal solution of FIR filter design problem. Evolutionary algorithms like real code genetic algorithm (RGA), particle swarm optimization (PSO), improved particle swarm optimization (IPSO) have been used in this work for the design of linear phase high pass FIR filter. IPSO is an improved PSO that proposes a new definition for the velocity vector and swarm updating and hence the solution quality is improved. A comparison of simulation results reveals the optimization efficacy of the algorithm over the prevailing optimization techniques for the solution of the multimodal, nondifferentiable, highly non-linear, and constrained FIR filter design problems.

Keywords: FIR Filter, IPSO, GA, PSO, Parks and McClellan Algorithm, Evolutionary Optimization, High Pass Filter

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Authors: Hyeongbok Kim, Lingling Zhao, Xiaohong Su, Junjie Wang

Abstract:

The Bernoulli filter is a precise Bayesian filter for single target tracking based on the random finite set theory. The standard Bernoulli filter often underestimates the number of the targets. This study proposes a Gaussian particle flow (GPF) Bernoulli filter employing particle flow to migrate particles from prior to posterior positions to improve the performance of the standard Bernoulli filter. By employing the particle flow filter, the computational speed of the Bernoulli filters is significantly improved. In addition, the GPF Bernoulli filter provides more accurate estimation compared with that of the standard Bernoulli filter. Simulation results confirm the improved tracking performance and computational speed in two- and three-dimensional scenarios compared with other algorithms.

Keywords: Bernoulli filter, particle filter, particle flow filter, random finite sets, target tracking.

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Authors: Tarek A. Kasmieh, Hassan S. Omran

Abstract:

This paper aims to give a full study of the dynamic behavior of a mono-phase active power filter. First, the principle of the parallel active power filter will be introduced. Then, a dimensioning procedure for all its components will be explained in detail, such as the input filter, the current and voltage controllers. This active power filter is simulated using OrCAD program showing the validity of the theoretical study.

Keywords: Active power filter, Power Quality, Hysteresiscurrent controller.

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Authors: Nicholas D. Assimakis

Abstract:

In linear estimation, the traditional Kalman filter uses the Kalman filter gain in order to produce estimation and prediction of the n-dimensional state vector using the m-dimensional measurement vector. The computation of the Kalman filter gain requires the inversion of an m x m matrix in every iteration. In this paper, a variation of the Kalman filter eliminating the Kalman filter gain is proposed. In the time varying case, the elimination of the Kalman filter gain requires the inversion of an n x n matrix and the inversion of an m x m matrix in every iteration. In the time invariant case, the elimination of the Kalman filter gain requires the inversion of an n x n matrix in every iteration. The proposed Kalman filter gain elimination algorithm may be faster than the conventional Kalman filter, depending on the model dimensions.

Keywords: Discrete time, linear estimation, Kalman filter, Kalman filter gain.

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Authors: Mahdi Shaneh, Arash Golibagh Mahyari

Abstract:

Image enhancement is the most important challenging preprocessing for almost all applications of Image Processing. By now, various methods such as Median filter, α-trimmed mean filter, etc. have been suggested. It was proved that the α-trimmed mean filter is the modification of median and mean filters. On the other hand, ε-filters have shown excellent performance in suppressing noise. In spite of their simplicity, they achieve good results. However, conventional ε-filter is based on moving average. In this paper, we suggested a new ε-filter which utilizes α-trimmed mean. We argue that this new method gives better outcomes compared to previous ones and the experimental results confirmed this claim.

Keywords: Image enhancement, median filter, ε-filter – α-trimmed mean filter.

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Authors: Rekha V. Dundur , M.V.Latte, S.Y. Kulkarni, M.K.Venkatesha

Abstract:

The advent of multi-million gate Field Programmable Gate Arrays (FPGAs) with hardware support for multiplication opens an opportunity to recreate a significant portion of the front end of a human cochlea using this technology. In this paper we describe the implementation of the cochlear filter and show that it is entirely suited to a single device XC3S500 FPGA implementation .The filter gave a good fit to real time data with efficiency of hardware usage.

Keywords: Cochlea, FPGA, IIR (Infinite Impulse Response), Multiplier.

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Authors: Muhammad Yasir Wadood, Fatemeh Babaeian

Abstract:

By developing ultra-wideband (UWB) systems, there is a high demand for UWB filters with low insertion loss, wide bandwidth, and having a planar structure which is compatible with other components of the UWB system. A microstrip interdigital filter is a great option for designing UWB filters. However, the presence of via holes in this structure creates difficulties in the fabrication procedure of the filter. Especially in the higher frequency band, any misalignment of the drilled via hole with the Microstrip stubs causes large errors in the measurement results compared to the desired results. Moreover, in this case (high-frequency designs), the line width of the stubs are very narrow, so highly precise small via holes are required to be implemented, which increases the cost of fabrication significantly. Also, in this case, there is a risk of having fabrication errors. To combat this issue, in this paper, a via-less UWB microstrip filter is proposed which is designed based on a modification of a conventional inter-digital bandpass filter. The novel approaches in this filter design are 1) replacement of each via hole with a quarter-wavelength open circuit stub to avoid the complexity of manufacturing, 2) using a bend structure to reduce the unwanted coupling effects and 3) minimising the size. Using the proposed structure, a UWB filter operating in the frequency band of 3.9-6.6 GHz (1-dB bandwidth) is designed and fabricated. The promising results of the simulation and measurement are presented in this paper. The selected substrate for these designs was Rogers RO4003 with a thickness of 20 mils. This is a common substrate in most of the industrial projects. The compact size of the proposed filter is highly beneficial for applications which require a very miniature size of hardware.

Keywords: Band-pass filters, inter-digital filter, microstrip, via-less.

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