Search results for: Complementary Metal Oxide Semiconductor (CMOS)

Authors: Junya Takenami, Md. Azhar Uddin, Eiji Sasaoka, Yasushi Shioya, Tsuneyoshi Takase

Abstract:

In this study, we sought to investigate the mercury removal efficiency of manganese oxides from natural gas. The fundamental studies on mercury removal with manganese oxides sorbents were carried out in a laboratory scale fixed bed reactor at 30 °C with a mixture of methane (20%) and nitrogen gas laden with 4.8 ppb of elemental mercury. Manganese oxides with varying surface area and crystalline phase were prepared by conventional precipitation method in this study. The effects of surface area, crystallinity and other metal oxides on mercury removal efficiency were investigated. Effect of Ag impregnation on mercury removal efficiency was also investigated. Ag supported on metal oxide such titania and zirconia as reference materials were also used in this study for comparison. The characteristics of mercury removal reaction with manganese oxide was investigated using a temperature programmed desorption (TPD) technique. Manganese oxides showed very high Hg removal activity (about 73-93% Hg removal) for first time use. Surface area of the manganese oxide samples decreased after heat-treatment and resulted in complete loss of Hg removal ability for repeated use after Hg desorption in the case of amorphous MnO2, and 75% loss of the initial Hg removal activity for the crystalline MnO2. Mercury desorption efficiency of crystalline MnO2 was very low (37%) for first time use and high (98%) after second time use. Residual potassium content in MnO2 may have some effect on the thermal stability of the adsorbed Hg species. Desorption of Hg from manganese oxides occurs at much higher temperatures (with a peak at 400 °C) than Ag/TiO2 or Ag/ZrO2. Mercury may be captured on manganese oxides in the form of mercury manganese oxide.

Keywords: Mercury removal, Metal and metal oxide sorbents, Methane, Natural gas.

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Authors: Vincent King Soon Wong, Hong Seng Ng, Florinna Sim

Abstract:

Negative Bias Temperature Instability (NBTI) is one of the critical degradation mechanisms in semiconductor device reliability that causes shift in the threshold voltage (Vth). However, thorough understanding of this reliability failure mechanism is still unachievable due to a recovery characteristic known as NBTI recovery. This paper will demonstrate the severity of NBTI recovery as well as one of the effective methods used to mitigate, which is the minimization of measurement system delays. Comparison was done in between two measurement systems that have significant differences in measurement delays to show how NBTI recovery causes result deviations and how fast measurement systems can mitigate NBTI recovery. Another method to minimize NBTI recovery without the influence of measurement system known as Fast Wafer Level Reliability (FWLR) NBTI was also done to be used as reference.

Keywords: Fast vs slow BTI, Fast wafer level reliability, Negative bias temperature instability, NBTI measurement system, metal-oxide-semiconductor field-effect transistor, MOSFET, NBTI recovery, reliability.

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Authors: Hassan Jassim Motlak

Abstract:

A novel design technique employing CMOS Current Feedback Operational Amplifier (CFOA) is presented. The feature of consumption very low power in designing pseudo-OTA is used to decreasing the total power consumption of the proposed CFOA. This design approach applies pseudo-OTA as input stage cascaded with buffer stage. Moreover, the DC input offset voltage and harmonic distortion (HD) of the proposed CFOA are very low values compared with the conventional CMOS CFOA due to the symmetrical input stage. P-Spice simulation results are obtained using 0.18μm MIETEC CMOS process parameters and supply voltage of ±1.2V, 50μA biasing current. The p-spice simulation shows excellent improvement of the proposed CFOA over existing CMOS CFOA. Some of these performance parameters, for example, are DC gain of 62. dB, openloop gain bandwidth product of 108 MHz, slew rate (SR+) of +71.2V/μS, THD of -63dB and DC consumption power (PC) of 2mW.

Keywords: Pseudo-OTA used CMOS CFOA, low power CFOA, high-performance CFOA, novel CFOA.

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Authors: Su Jeong Lee, Tae Il Lee, Jung Han Kim, Chul-Hong Kim, Gee Sung Chae, Jae-Min Myoung

Abstract:

The contact resistance between source/drain electrodes and semiconductor layer is an important parameter affecting electron transporting performance in the thin film transistor (TFT). In this work, we introduced a transparent and the solution prossable single-walled carbon nanotube (SWCNT)/Al-doped ZnO nano particle (AZO NP) bilayer electrodes showing low contact resistance with indium-oxide (In2O3) sol gel thin film. By inserting low work function AZO NPs into the interface between the SWCNTs and the In2O3 which has a high energy barrier, we could obtain an electrical Ohmic contact between them. Finally, with the SWCNT-AZO NP bilayer electrodes, we successfully fabricated a TFT showing a field effect mobility of 5.38 cm2/V·s at 250°C.

Keywords: Single-walled carbon nanotube (SWCNT), Al-doped ZnO (AZO) nanoparticle, contact resistance, Thin-film transistor (TFT).

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Authors: Soo-Yeon Lee, Seung-Min Song, Moon-Kyu Song, Woo-Geun Lee, Kap-Soo Yoon, Jang-Yeon Kwon, Min-Koo Han

Abstract:

We fabricated the inverted-staggered etch stopper structure oxide-based TFT and investigated the characteristics of oxide TFT under the 400 nm wavelength light illumination. When 400 nm light was illuminated, the threshold voltage (Vth) decreased and subthreshold slope (SS) increased at forward sweep, while Vth and SS were not altered when larger wavelength lights, such as 650 nm, 550 nm and 450 nm, were illuminated. At reverse sweep, the transfer curve barely changed even under 400 nm light. Our experimental results support that photo-induced hole carriers are captured by donor-like interface trap and it caused the decrease of Vth and increase of SS. We investigated the interface trap density increases proportionally to the photo-induced hole concentration at active layer.

Keywords: thin film transistor, oxide-based semiconductor, lightresponse

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Authors: Shiyang Zhu, G. Q. Lo, D. L. Kwong

Abstract:

Silicon photonics has generated an increasing interest in recent years mainly for optical communications optical interconnects in microelectronic circuits or bio-sensing applications. The development of elementary passive and active components (including detectors and modulators), which are mainly fabricated on the silicon on insulator platform for CMOS-compatible fabrication, has reached such a performance level that the integration challenge of silicon photonics with microelectronic circuits should be addressed. Since crystalline silicon can only be grown from another silicon crystal, making it impossible to deposit in this state, the optical devices are typically limited to a single layer. An alternative approach is to integrate a photonic layer above the CMOS chip using back-end CMOS fabrication process. In this paper, various materials, including silicon nitride, amorphous silicon, and polycrystalline silicon, for this purpose are addressed.

Keywords: Silicon photonics, CMOS, Integration.

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Authors: Q. Zafar, R. Akram, Kh.S. Karimov, T.A. Khan, M. Farooq, M.M. Tahir

Abstract:

In this study we present the effect of elevated temperatures from 300K to 400K on the electrical properties of copper Phthalocyanine (CuPc) based organic field effect transistors (OFET). Thin films of organic semiconductor CuPc (40nm) and semitransparent Al (20nm) were deposited in sequence, by vacuum evaporation on a glass substrate with previously deposited Ag source and drain electrodes with a gap of 40 μm. Under resistive mode of operation, where gate was suspended it was observed that drain current of this organic field effect transistor (OFET) show an increase with temperature. While in grounded gate condition metal (aluminum) – semiconductor (Copper Phthalocyanine) Schottky junction dominated the output characteristics and device showed switching effect from low to high conduction states like Zener diode at higher bias voltages. This threshold voltage for switching effect has been found to be inversely proportional to temperature and shows an abrupt decrease after knee temperature of 360K. Change in dynamic resistance (Rd = dV/dI) with respect to temperature was observed to be -1%/K.

Keywords: Copper Phthalocyanine, Metal-Semiconductor Schottky Junction, Organic Field Effect Transistor, Switching effect, Temperature Sensor

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Authors: PoiSim Khiew, WeeSiong Chiu, ThianKhoonTan, Shahidan Radiman, Roslan Abd-Shukor, Muhammad Azmi Abd-Hamid, ChinHua Chia

Abstract:

Magnetic and semiconductor nanomaterials exhibit novel magnetic and optical properties owing to their unique size and shape-dependent effects. With shrinking the size down to nanoscale region, various anomalous properties that normally not present in bulk start to dominate. Ability in harnessing of these anomalous properties for the design of various advance electronic devices is strictly dependent on synthetic strategies. Hence, current research has focused on developing a rational synthetic control to produce high quality nanocrystals by using organometallic approach to tune both size and shape of the nanomaterials. In order to elucidate the growth mechanism, transmission electron microscopy was employed as a powerful tool in performing real time-resolved morphologies and structural characterization of magnetic (Fe3O4) and semiconductor (ZnO) nanocrystals. The current synthetic approach is found able to produce nanostructures with well-defined shapes. We have found that oleic acid is an effective capping ligand in preparing oxide-based nanostructures without any agglomerations, even at high temperature. The oleate-based precursors and capping ligands are fatty acid compounds, which are respectively originated from natural palm oil with low toxicity. In comparison with other synthetic approaches in producing nanostructures, current synthetic method offers an effective route to produce oxide-based nanomaterials with well-defined shapes and good monodispersity. The nanocystals are well-separated with each other without any stacking effect. In addition, the as-synthesized nanopellets are stable in terms of chemically and physically if compared to those nanomaterials that are previous reported. Further development and extension of current synthetic strategy are being pursued to combine both of these materials into nanocomposite form that will be used as “smart magnetic nanophotocatalyst" for industry waste water treatment.

Keywords: Metal oxide nanomaterials, Nanophotocatalyst, Organometallic synthesis, Morphology Control

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Authors: Gao Wei, Xu Minglu, Xu Yan, Zhang Xiaotong, Wang Xinghua

Abstract:

A 3.5-bit stage of the CMOS pipelined ADC is proposed. In this report, the main part of 3.5-bit stage ADC is introduced. How the MDAC, comparator and encoder worked and designed are shown in details. Besides, an OTA which is used in fully differential pipelined ADC was described. Using gain-boost architecture with differential amplifier, this OTA achieve high-gain and high-speed. This design was using CMOS 0.18um process and simulation in Cadence. The result of the simulation shows that the OTA has a gain up to 80dB, the unity gain bandwidth of about 1.138GHz with 2pF load.

Keywords: pipelined ADC, MDAC, operational amplifier.

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Authors: Nasir Mehmood, Saad Rahman, Vinodh Ravinath, Mahesh Balaji

Abstract:

This paper describes the design of a programmable FSK-modulator based on VCO and its implementation in 0.35m CMOS process. The circuit is used to transmit digital data at 100Kbps rate in the frequency range of 400-600MHz. The design and operation of the modulator is discussed briefly. Further the characteristics of PLL, frequency synthesizer, VCO and the whole design are elaborated. The variation among the proposed and tested specifications is presented. Finally, the layout of sub-modules, pin configurations, final chip and test results are presented.

Keywords: FSK Modulator, CMOS, VCO, Phase Locked Loop, Frequency Synthesizer.

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Authors: Wai Pan Chan, Minkyu Je

Abstract:

A precision CMOS chopping amplifier is adopted in this work to improve a CMOS temperature sensor high sensitive enough for intracranial temperature monitoring. An amplified temperature sensitivity of 18.8 ± 3*0.2 mV/oC is attained over the temperature range from 20 oC to 80 oC from a given 10 samples of the same wafer. The analog frontend design outputs the temperature dependent and the temperature independent signals which can be directly interfaced to a 10 bit ADC to accomplish an accurate temperature instrumentation system.

Keywords: Chopping, analog frontend, CMOS temperature sensor, traumatic brain injury (TBI), intracranial temperature monitoring.

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Authors: M. Aleshams, A. Shahsavandi

Abstract:

This paper describes a CMOS four-quadrant multiplier intended for use in the front-end receiver by utilizing the square-law characteristic of the MOS transistor in the saturation region. The circuit is based on 0.35 um CMOS technology simulated using HSPICE software. The mixer has a third-order inter the power consumption is 271uW from a single 1.2V power supply. One of the features of the proposed design is using two MOS transistors limitation to reduce the supply voltage, which leads to reduce the power consumption. This technique provides a GHz bandwidth response and low power consumption.

Keywords: RF-Mixer, Multiplier, cut-off frequency, power consumption

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Authors: Ashwani K. Rana, Narottam Chand, Vinod Kapoor

Abstract:

This paper presents a new compact analytical model of the gate leakage current in high-k based nano scale MOSFET by assuming a two-step inelastic trap-assisted tunneling (ITAT) process as the conduction mechanism. This model is based on an inelastic trap-assisted tunneling (ITAT) mechanism combined with a semiempirical gate leakage current formulation in the BSIM 4 model. The gate tunneling currents have been calculated as a function of gate voltage for different gate dielectrics structures such as HfO2, Al2O3 and Si3N4 with EOT (equivalent oxide thickness) of 1.0 nm. The proposed model is compared and contrasted with santaurus simulation results to verify the accuracy of the model and excellent agreement is found between the analytical and simulated data. It is observed that proposed analytical model is suitable for different highk gate dielectrics simply by adjusting two fitting parameters. It was also shown that gate leakages reduced with the introduction of high-k gate dielectric in place of SiO2.

Keywords: Analytical model, High-k gate dielectrics, inelastic trap assisted tunneling, metal–oxide–semiconductor (MOS) devices.

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Authors: J. Uka, B. McKay, T. Minton, O. Adole, R. Lewis, S. J. Glanvill, L. Anguilano

Abstract:

Effective heat treatment conditions to obtain maximum aluminium swarf recycling are investigated in this work. Aluminium swarf briquettes underwent treatments at different temperatures and cooling times to investigate the improvements obtained in the recovery of aluminium metal. The main issue for the recovery of the metal from swarfs is to overcome the constraints due to the oxide layers present in high concentration in the swarfs since they have a high surface area. Briquettes supplied by Renishaw were heat treated at 650, 700, 750, 800 and 850 ℃ for 1-hour and then cooled at 2.3, 3.5 and 5 ℃/min. The resulting material was analysed using SEM EDX to observe the oxygen diffusion and aluminium coalescence at the boundary between adjacent swarfs. Preliminary results show that, swarf needs to be heat treated at a temperature of 850 ℃ and cooled down slowly at 2.3 ℃/min to have thin and discontinuous alumina layers between the adjacent swarf and consequently allowing aluminium coalescence. This has the potential to save energy and provide maximum financial profit in preparation of swarf briquettes for recycling.

Keywords: Aluminium, swarf, oxide layers, recycle, reuse.

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Authors: J. S. Kim, N. P. Hong

Abstract:

In this paper, a CMOS vector modulator designed for wireless backhaul system based on 802.11ac is presented. A poly phase filter and sign select switches yield two orthogonal signal paths. Two variable gain amplifiers with strongly reduced phase shift of only ±5 ° are used to weight these paths. It has a phase control range of 360 ° and a gain range of -10 dB to 10 dB. The current drawn from a 1.2 V supply amounts 20.4 mA. Using a 0.13 mm technology, the chip die area amounts 1.47x0.75 mm².

Keywords: CMOS, vector modulator, backhaul, 802.11ac.

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Authors: Alpana Agarwal, Akhil Sharma

Abstract:

This work presents a fully differential CMOS amplifier consisting of two self-biased gain boosted inverter stages, that provides an alternative to the power hungry operational amplifier. The self-biasing avoids the use of external biasing circuitry, thus reduces the die area, design efforts, and power consumption. In the present work, regulated cascode technique has been employed for gain boosting. The Miller compensation is also applied to enhance the phase margin. The circuit has been designed and simulated in 1.8 V 0.18 µm CMOS technology. The simulation results show a high DC gain of 100.7 dB, Unity-Gain Bandwidth of 107.8 MHz, and Phase Margin of 66.7^o with a power dissipation of 286 μW and makes it suitable candidate for the high resolution pipelined ADCs.

Keywords: CMOS amplifier, gain boosting, inverter-based amplifier, self-biased inverter.

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Authors: Shashank Gautam

Abstract:

This paper proposes techniques like MT CMOS, POWER GATING, DUAL STACK, GALEOR and LECTOR to reduce the leakage power. A Full Adder has been designed using these techniques and power dissipation is calculated and is compared with general CMOS logic of Full Adder. Simulation results show the validity of the proposed techniques is effective to save power dissipation and to increase the speed of operation of the circuits to a large extent.

Keywords: Low Power, MT CMOS, Galeor, Lector, Power Gating, Dual Stack, Full Adder.

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Authors: Montree Kumngern, Kobchai Dejhan

Abstract:

Versatile dual-mode class-AB CMOS four-quadrant analog multiplier circuit is presented. The dual translinear loops and current mirrors are the basic building blocks in realization scheme. This technique provides; wide dynamic range, wide-bandwidth response and low power consumption. The major advantages of this approach are; its has single ended inputs; since its input is dual translinear loop operate in class-AB mode which make this multiplier configuration interesting for low-power applications; current multiplying, voltage multiplying, or current and voltage multiplying can be obtainable with balanced input. The simulation results of versatile analog multiplier demonstrate a linearity error of 1.2 %, a -3dB bandwidth of about 19MHz, a maximum power consumption of 0.46mW, and temperature compensated. Operation of versatile analog multiplier was also confirmed through an experiment using CMOS transistor array.

Keywords: Class-AB, dual-mode CMOS analog multiplier, CMOS analog integrated circuit, CMOS translinear integrated circuit.

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Authors: Hai-Qing Xie, Yun Zeng, Yong-Hong Yan, Guo-Liang Zhang, Tai-Hong Wang

Abstract:

We propose photo-BJMOSFET (Bipolar Junction Metal-Oxide-Semiconductor Field Effect Transistor) fabricated on SOI film. ITO film is adopted in the device as gate electrode to reduce light absorption. I-V characteristics of photo-BJMOSFET obtained in dark (dark current) and under 570nm illumination (photo current) are studied furthermore to achieve high photo-to-dark-current contrast ratio. Two variables in the calculation were the channel length and the thickness of the film which were set equal to six different values, i.e., L=2, 4, 6, 8, 10, and 12μm and three different values, i.e., dsi =100, 200 and 300nm, respectively. The results indicate that the greatest photo-to-dark-current contrast ratio is achieved with L=10μm and dsi=200 nm at VGK=0.6V.

Keywords: Photo-to-dark-current contrast ratio, Photo-current, Dark-current, Process parameter

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Authors: Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Keivan Navi

Abstract:

In this paper we present two novel 1-bit full adder cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output structures are used to design the adder blocks. Characteristic of dynamic logic leads to higher speeds than the other standard static full adder cells. Using HSpice and 0.18┬Ám CMOS technology exhibits a significant decrease in the cell delay which can result in a considerable reduction in the power-delay product (PDP). The PDP of Multi-Output design at 1.8v power supply is around 0.15 femto joule that is 5% lower than conventional dynamic full adder cell and at least 21% lower than other static full adders.

Keywords: Bridge Style, Dynamic Logic, Full Adder, HighSpeed, Multi Output, NP-CMOS, Zipper.

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Authors: Ashot Navasardian, Mariam Vardanian, Vladik Vardanian

Abstract:

The photovoltaic and the semiconductor industries are in growth and it is necessary to supply a large amount of silicon to maintain this growth. Since silicon is still the best material for the manufacturing of solar cells and semiconductor components so the pure silicon like solar grade and semiconductor grade materials are demanded. There are two main routes for silicon production: metallurgical and chemical. In this article, we reviewed the electrotecnological installations and systems for semiconductor manufacturing. The main task is to design the installation which can produce SOG Silicon from river sand by one work unit.

Keywords: Metallurgical grade silicon, solar grade silicon, impurity, refining, plasma.

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Authors: Yashvir Singh, Mayank Joshi

Abstract:

A lateral trench-gate power metal-oxide-semiconductor on 4H-SiC is proposed. The device consists of two separate trenches in which two gates are placed on both sides of P-body region resulting two parallel channels. Enhanced current conduction and reduced-surface-field effect in the structure provide substantial improvement in the device performance. Using two dimensional simulations, the performance of proposed device is evaluated and compare of with that of the conventional device for same cell pitch. It is demonstrated that the proposed structure provides two times higher output current, 11% decrease in threshold voltage, 70% improvement in transconductance, 70% reduction in specific ON-resistance, 52% increase in breakdown voltage, and nearly eight time improvement in figure-of-merit over the conventional device.

Keywords: 4H-SiC, lateral, trench-gate, power MOSFET.

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Authors: Abdelmonaem Ayachi, Belgacem Hamdi

Abstract:

This paper presents a fault-tolerant implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to standard CMOS technology.

Keywords: Semiconductors, digital electronics, double pass transistor technology, Full adder, fault tolerance.

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Authors: Hamed Rezazadeh, Majid Ebrahimzadeh, Mohammad Reza Zeidi Yam

Abstract:

Anodizing is an electrochemical process that converts the metal surface into a decorative, durable, corrosion-resistant, anodic oxide finish. Aluminum is ideally suited to anodizing, although other nonferrous metals, such as magnesium and titanium, also can be anodized. The anodic oxide structure originates from the aluminum substrate and is composed entirely of aluminum oxide. This aluminum oxide is not applied to the surface like paint or plating, but is fully integrated with the underlying aluminum substrate, so cannot chip or peel. It has a highly ordered, porous structure that allows for secondary processes such as coloring and sealing. In this experimental paper, we focus on a reliable method for fabricating nanoporous alumina with high regularity. Starting from study of nanostructure materials synthesize methods. After that, porous alumina fabricate in the laboratory by anodization of aluminum oxide. Hard anodization processes are employed to fabricate the nanoporous alumina using 0.3M oxalic acid and 90, 120 and 140 anodized voltages. The nanoporous templates were characterized by SEM and FFT. The nanoporous templates using 140 voltages have high ordered. The pore formation, influence of the experimental conditions on the pore formation, the structural characteristics of the pore and the oxide chemical reactions involved in the pore growth are discuss.

Keywords: Alumina, Nanoporous Template, Anodization

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Authors: K. Karami, S. Hassan, S. Taking, A. Ofiare, A. Dhongde, A. Al-Khalidi, E. Wasige

Abstract:

We have made a comparative study on the influence of Al2O3 and HfO2 grown using Atomic Layer Deposition (ALD) technique as dielectric in the AlGaN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) structure. Five samples consisting of 20 nm and 10 nm each of A2lO3 and HfO2 respectively and a Schottky gate HEMT, were fabricated and measured. The threshold voltage shifts towards negative by 0.1 V and 1.8 V for 10 nm thick HfO2 and 10 nm thick Al2O3 gate dielectric layers, respectively. The negative shift for the 20 nm HfO2 and 20 nm Al2O3 were 1.2 V and 4.9 V, respectively. Higher gm/IDS (transconductance to drain current) ratio was also obtained in HfO2 than Al2O3. With both materials as dielectric, a significant reduction in the gate leakage current in the order of 104 was obtained compared to the sample without the dielectric material.

Keywords: AlGaN/GaN HEMTs, Al2O3, HfO2, MOSHEMTs.

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Authors: M. Gómez-Gómez, M. E. Sánchez-Vergara

Abstract:

Many sustainable approaches to generate electric energy have emerged in the last few decades; one of them is through solar cells. Yet, this also has the disadvantage of highly polluting inorganic semiconductor manufacturing processes. Therefore, the use of molecular semiconductors must be considered. In this work, allene compounds C24H26O4 and C24H26O5 were used as dopants to manufacture semiconductor films based on PbPc by high-vacuum evaporation technique. IR spectroscopy was carried out to determine the phase and any significant chemical changes which may occur during the thermal evaporation. According to UV-visible spectroscopy and Tauc’s model, the deposition process generated thin films with an activation energy range of 1.47 eV to 1.55 eV for direct transitions and 1.29 eV to 1.33 eV for indirect transitions. These values place the manufactured films within the range of low bandgap semiconductors. The flexible devices were manufactured: polyethylene terephthalate (PET), Indium tin oxide (ITO)/organic semiconductor/Cubic Close Packed (CCP). The characterization of the devices was carried out by evaluating electrical conductivity using the four-probe collinear method. I-V curves were obtained under different lighting conditions at room temperature. OS1 (PbPc/C24H26O4) showed an Ohmic behavior, while OS2 (PbPc/C24H26O5) reached higher current values at lower voltages. The results obtained show that the semiconductor devices doped with allene compounds can be used in the manufacture of optoelectronic devices.

Keywords: Electrical properties, optical gap, phthalocyanine, thin film.

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Authors: M.Yousefi, A.Vatanjou, F.Nazeri

Abstract:

A fast settling multipath CMOS OTA for high speed switched capacitor applications is presented here. With the basic topology similar to folded-cascode, bandwidth and DC gain of the OTA are enhanced by adding extra paths for signal from input to output. Designed circuit is simulated with HSPICE using level 49 parameters (BSIM 3v3) in 0.35mm standard CMOS technology. DC gain achieved is 56.7dB and Unity Gain Bandwidth (UGB) obtained is 1.15GHz. These results confirm that adding extra paths for signal can improve DC gain and UGB of folded-cascode significantly.

Keywords: OTA (Operational Transconductance Amplifier), DC gain, Unity Gain Bandwidth (UGBW)

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Authors: Chang Soo Kang, In Ho Im, Sergey Churayev, Timour Paltashev

Abstract:

This paper describes the design of new method of propagation delay measurement in micro and nanostructures during characterization of ASIC standard library cell. Providing more accuracy timing information about library cell to the design team we can improve a quality of timing analysis inside of ASIC design flow process. Also, this information could be very useful for semiconductor foundry team to make correction in technology process. By comparison of the propagation delay in the CMOS element and result of analog SPICE simulation. It was implemented as digital IP core for semiconductor manufacturing process. Specialized method helps to observe the propagation time delay in one element of the standard-cell library with up-to picoseconds accuracy and less. Thus, the special useful solutions for VLSI schematic to parameters extraction, basic cell layout verification, design simulation and verification are announced.

Keywords: phase error accumulation methodology, gatepropagation delay, Processor Testing, MEMS Testing

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Authors: Nasir Mehmood, Jens Ogniewski, Vinodh Ravinath

Abstract:

This paper describes the design of a real-time audiorange digital oscilloscope and its implementation in 90nm CMOS FPGA platform. The design consists of sample and hold circuits, A/D conversion, audio and video processing, on-chip RAM, clock generation and control logic. The design of internal blocks and modules in 90nm devices in an FPGA is elaborated. Also the key features and their implementation algorithms are presented. Finally, the timing waveforms and simulation results are put forward.

Keywords: CMOS, VLSI, Oscilloscope, Field Programmable Gate Array (FPGA), VHDL, Video Graphics Array (VGA)

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Authors: N. Aldea, V. Rednic, F. Matei, Tiandou Hu, M. Neumann

Abstract:

The nickel and gold nanoclusters as supported catalysts were analyzed by XAS, XRD and XPS in order to determine their local, global and electronic structure. The present study has pointed out a strong deformation of the local structure of the metal, due to its interaction with oxide supports. The average particle size, the mean squares of the microstrain, the particle size distribution and microstrain functions of the supported Ni and Au catalysts were determined by XRD method using Generalized Fermi Function for the X-ray line profiles approximation. Based on EXAFS analysis we consider that the local structure of the investigated systems is strongly distorted concerning the atomic number pairs. Metal-support interaction is confirmed by the shape changes of the probability densities of electron transitions: Ni K edge (1s → continuum and 2p), Au LIII-edge (2p3/2 → continuum, 6s, 6d5/2 and 6d3/2). XPS investigations confirm the metal-support interaction at their interface.

Keywords: local and global structure, metal-support interaction, supported metal catalysts, synchrotron radiation, X-ray absorptionspectroscopy, X-ray diffraction, X-ray photoelectron spectroscopy.

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