Search results for: CMOS analog to digital converter

Authors: Fahad Alanazi, Andrew Jones

Abstract:

Digital forensics seeks to achieve the successful investigation of digital crimes through obtaining acceptable evidence from digital devices that can be presented in a court of law. Thus, the digital forensics investigation is normally performed through a number of phases in order to achieve the required level of accuracy in the investigation processes. Since 1984 there have been a number of models and frameworks developed to support the digital investigation processes. In this paper, we review a number of the investigation processes that have been produced throughout the years and introduce a proposed digital forensic model which is based on the scope of the Saudi Arabia investigation process. The proposed model has been integrated with existing models for the investigation processes and produced a new phase to deal with a situation where there is initially insufficient evidence.

Keywords: Digital forensics, Process, Metadata, Traceback, Saudi Arabia.

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Authors: Vladimir Korovkin, Albert Park, Evgeny Kaganer

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Digital divide, the gap in the access to the world of digital technologies and the socio-economic opportunities that they create is an important phenomenon of the XXI century. This gap may exist between countries, regions within a country or socio-demographic groups, creating the classes of “digital have and have nots”. While the 1st-level divide (the difference in opportunities to access the digital networks) was demonstrated to diminish with time, the issues of 2nd level divide (the difference in skills and usage of digital systems) and 3rd level divide (the difference in effects obtained from digital technology) may grow. The paper offers a systemic review of literature on the measurement of the digital divide, noting the certain conceptual stagnation due to the lack of effective instruments that would capture the complex nature of the phenomenon. As a result, many important concepts do not receive the empiric exploration they deserve. As a solution the paper suggests a composite Digital Life Index, that studies separately the digital supply and demand across seven independent dimensions providing for 14 subindices. The Index is based on Internet-borne data, a distinction from traditional research approaches that rely on official statistics or surveys. The application of the model to the study of the digital divide between Russian regions and between cities in China have brought promising results. The paper advances the existing methodological literature on the 2nd level digital divide and can also inform practical decision-making regarding the strategies of national and regional digital development.

Keywords: Digital transformation, second-level digital divide, composite index, digital policy.

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Authors: Eduardo Romero, Marcelo Costamagna, Gabriela Peretti, Carlos Marqués

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This work evaluates the ability of OBT for detecting parametric faults in continuous-time filters. To this end, we adopt two filters with quite different topologies as cases of study and a previously reported statistical fault model. In addition, we explore the behavior of the test schemes when a particular test condition is changed. The new data reported here, obtained from a fault simulation process, reveal a lower performance of OBT not observed in previous work using single-deviation faults, even under the change in the test condition.

Keywords: Testing, analog fault simulation, analog filter test, oscillation based test.

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Authors: James Dunia, Bakari M. M. Mwinyiwiwa

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Photovoltaic (PV) energy is one of the most important energy resources since it is clean, pollution free, and endless. Maximum Power Point Tracking (MPPT) is used in photovoltaic (PV) systems to maximize the photovoltaic output power, irrespective the variations of temperature and radiation conditions. This paper presents a comparison between Ćuk and SEPIC converter in maximum power point tracking (MPPT) of photovoltaic (PV) system. In the paper, advantages and disadvantages of both converters are described. Incremental conductance control method has been used as maximum power point tracking (MPPT) algorithm. The two converters and MPPT algorithm were modelled using MATLAB/Simulink software for simulation. Simulation results show that both Ćuk and SEPIC converters can track the maximum power point with some minor variations. 

Keywords: Ćuk Converter, Incremental Conductance, Maximum Power Point Tracking, PV Module, SEPIC Converter.

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Authors: Arun Kumar Datta, Manisha Dubey, Shailendra Jain

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Electric machines are driven nowadays by static system popularly known as soft starter. This paper describes a thyristor based static frequency converter (SFC) to run a large synchronous machine installed at a short circuit test laboratory. Normally a synchronous machine requires prime mover or some other driving mechanism to run. This machine doesn’t need a prime mover as it operates in dual mode. In the beginning SFC starts this machine as a motor to achieve the full speed. Thereafter whenever required it can be converted to generator mode. This paper begins with the various starting methodology of synchronous machine. Detailed of SFC with different operational modes have been analyzed. Shaft voltage is a very common phenomenon for the machines with static drives. Various causes of shaft voltages in perspective with this machine are the main attraction of this paper.

Keywords: Capacitive coupling, electric discharge machining, inductive coupling, Shaft voltage, static frequency converter.

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Authors: Z. Feng, V. Viswanathan, D. Navarro, I. O'Connor

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This paper presents a new high speed simulation methodology to solve the long simulation time problem of CMOS image sensor matrix. Generally, for integrating the pixel matrix in SOC and simulating the system performance, designers try to model the pixel in various modeling languages such as VHDL-AMS, SystemC or Matlab. We introduce a new alternative method based on spice model in cadence design platform to achieve accuracy and reduce simulation time. The simulation results indicate that the pixel output voltage maximum error is at 0.7812% and time consumption reduces from 2.2 days to 13 minutes achieving about 240X speed-up for the 256x256 pixel matrix.

Keywords: CMOS image sensor, high speed simulation, image sensor matrix simulation.

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Authors: P. Ruttanee, K-N. Areerak, K-L. Areerak

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Dynamic models of power converters are normally time-varying because of their switching actions. Several approaches are applied to analyze the power converters to achieve the timeinvariant models suitable for system analysis and design via the classical control theory. The paper presents how to derive dynamic models of the power system consisting of a three-phase controlled rectifier feeding an uncontrolled buck converter by using the combination between the well known techniques called the DQ and the generalized state-space averaging methods. The intensive timedomain simulations of the exact topology model are used to support the accuracies of the reported model. The results show that the proposed model can provide good accuracies in both transient and steady-state responses.

Keywords: DQ method, Generalized state-space averaging method, Three-phase controlled rectifier, Uncontrolled buck converter, Averaging model, Modeling, Simulation.

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Authors: Gianluca Cornetta, David J. Santos

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This paper describes a 2.4 GHz passive switch mixer and a 5/2.5 GHz voltage-controlled negative Gm oscillator (VCO) with an inversion-mode MOS varactor. Both circuits are implemented using a 1P8M 0.13 μm process. The switch mixer has an input referred 1 dB compression point of -3.89 dBm and a conversion gain of -0.96 dB when the local oscillator power is +2.5 dBm. The VCO consumes only 1.75 mW, while drawing 1.45 mA from a 1.2 V supply voltage. In order to reduce the passives size, the VCO natural oscillation frequency is 5 GHz. A clocked CMOS divideby- two circuit is used for frequency division and quadrature phase generation. The VCO has a -109 dBc/Hz phase noise at 1 MHz frequency offset and a 2.35-2.5 GHz tuning range (after the frequency division), thus complying with ZigBee requirements.

Keywords: Switch Mixers, Varactors, IEEE 802.15.4 (ZigBee), Direct Conversion Receiver, Wireless Sensor Networks.

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Authors: Anupam Kumar, Abdul Hamid Bhat, Pramod Agarwal

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Bidirectional energy transfer capability with high efficiency and reduced cost is fast gaining prominence in the central part of a lot of power conversion systems in Direct Current (DC) microgrid. Preferably, under the economics constraints, these systems utilise a single high efficiency power electronics conversion system and a dual active bridge converter. In this paper, modeling and performance of Dual Active Bridge (DAB) converter with Extended Phase Shift (EPS) is evaluated with two batteries on both sides of DC bus and bidirectional energy transfer is facilitated and this is further compared with the Single Phase Shift (SPS) mode of operation. Optimum operating zone is identified through exhaustive simulations using MATLAB/Simulink and SimPowerSystem software. Reduced rules based fuzzy logic controller is implemented for closed loop control of DAB converter. The control logic enables the bidirectional energy transfer within the batteries even at lower duty ratios. Charging and discharging of batteries is supervised by the fuzzy logic controller. State of charge, current and voltage for both the batteries are plotted in the battery characteristics. Power characteristics of batteries are also obtained using MATLAB simulations.

Keywords: Fuzzy logic controller, rule base, membership functions, dual active bridge converter, bidirectional power flow, duty ratio, extended phase shift, state of charge.

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Authors: Dalia Suša Vugec, Ana-Marija Stjepić, Darija Ivandić Vidović

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Digital transformation is one of the latest trends on the global market. In order to maintain the competitive advantage and sustainability, increasing number of organizations are conducting digital transformation processes. Those organizations are changing their business processes and creating new business models with the help of digital technologies. In that sense, one should also observe the role of business process management (BPM) and its maturity in driving digital transformation. Therefore, the goal of this paper is to investigate the role of BPM in digital transformation process within one organization. Since experiences from practice show that organizations from financial sector could be observed as leaders in digital transformation, an insurance company has been selected to participate in the study. That company has been selected due to the high level of its BPM maturity and the fact that it has previously been through a digital transformation process. In order to fulfill the goals of the paper, several interviews, as well as questionnaires, have been conducted within the selected company. The results are presented in a form of a case study. Results indicate that digital transformation process within the observed company has been successful, with special focus on the development of digital strategy, BPM and change management. The role of BPM in the digital transformation of the observed company is further discussed in the paper.

Keywords: Business process management, case study, Croatia, digital transformation, insurance company.

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Authors: H. Daoud Dammak, S. Bensalem, S. Zouari, M. Loulou

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This paper presents an optimized methodology to folded cascode operational transconductance amplifier (OTA) design. The design is done in different regions of operation, weak inversion, strong inversion and moderate inversion using the gm/ID methodology in order to optimize MOS transistor sizing. Using 0.35μm CMOS process, the designed folded cascode OTA achieves a DC gain of 77.5dB and a unity-gain frequency of 430MHz in strong inversion mode. In moderate inversion mode, it has a 92dB DC gain and provides a gain bandwidth product of around 69MHz. The OTA circuit has a DC gain of 75.5dB and unity-gain frequency limited to 19.14MHZ in weak inversion region.

Keywords: CMOS IC design, Folded Cascode OTA, gm/ID methodology, optimization.

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Authors: Muhaned Zaidi, Ian Grout, Abu Khari bin A’ain

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In this paper, a two-stage op-amp design is considered using both Miller and negative Miller compensation techniques. The first op-amp design uses Miller compensation around the second amplification stage, whilst the second op-amp design uses negative Miller compensation around the first stage and Miller compensation around the second amplification stage. The aims of this work were to compare the gain and phase margins obtained using the different compensation techniques and identify the ability to choose either compensation technique based on a particular set of design requirements. The two op-amp designs created are based on the same two-stage rail-to-rail output CMOS op-amp architecture where the first stage of the op-amp consists of differential input and cascode circuits, and the second stage is a class AB amplifier. The op-amps have been designed using a 0.35mm CMOS fabrication process.

Keywords: Op-amp, rail-to-rail output, Miller compensation, negative Miller capacitance.

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Authors: Makoto Nagatomo, Yasuo Uchida, Makoto Sakamoto, Tuo Zhang, Tatsuma Kurogi, Takao Ito, Tsunehiro Yoshinaga, Satoshi Ikeda, Masahiro Yokomichi, Hiroshi Furutani

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This paper presents a four-dimensional computational model, k-neighborhood template A-type three-dimensional bounded cellular acceptor (abbreviated as A-3BCA(k)), and discusses the hierarchical properties. An A-3BCA(k) is a four-dimensional automaton which consists of a pair of a converter and a configuration-reader. The former converts the given four-dimensional tape to the three- and two- dimensional configuration and the latter determines the acceptance or nonacceptance of given four-dimensional tape whether or not the derived two-dimensional configuration is accepted. We mainly investigate the difference of the accepting power based on the difference of the configuration-reader. It is shown that the difference of the accepting power of the configuration-reader tends to affect directly that of the A-3BCA(k) for the case when the converter is deterministic. On the other hand, results are not analogous for the nondeterministic case.

Keywords: Cellular acceptor, configuration-reader, converter, finite automaton, four-dimension, on-line tessellation acceptor, parallel/sequential array acceptor, turing machine.

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Authors: Prapoj Na Bangchang

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The research aimed to study the satisfaction of Suan Sunandha Rajabhat University students towards the university radio station which broadcasts in both analog on FM 97.25 MHz and online via the university website. The sample used in this study consists of undergraduate students year 1 to year 4 from 6 faculties i.e. Faculty of Education, Faculty of Humanities and Social Sciences, Faculty of Management Science and Faculty of Industrial Technology, and Faculty of Fine and Applied Arts totaling 200 students. The tools used for data collection is survey. Data analysis applied statistics that are percentage, mean and standard deviation. The results showed that Suan Sunandha Rajabhat University students were satisfied to the place of listening service, followed by channels of broadcasting that cover both analog signals on 97.25 MHz FM and online via the Internet. However, the satisfaction level of the content offered was very low. Most of the students want the station to improve the content. Entertainment content was requested the most, followed by sports content. The lowest satisfaction level is with the broadcasting quality through analog signal. Most students asked the station to improve on the issue. However, overall, Suan Sunandha Rajabhat University students were satisfied with the university radio station broadcasted online via the university website.

Keywords: Satisfaction, students, radio station, Suan Sunandha Rajabhat University.

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Authors: Ju-Hong Lee, Chong-Jia Ciou, Yuan-Hau Yang

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This paper deals with the problem of two-dimensional (2-D) recursive doubly complementary (DC) digital filter design. We present a structure of 2-D recursive DC filters by using 2-D symmetric half-plane (SHP) recursive digital all-pass lattice filters (DALFs). The novelty of using 2-D SHP recursive DALFs to construct a 2-D recursive DC digital lattice filter is that the resulting 2-D SHP recursive DC digital lattice filter provides better performance than the existing 2-D SHP recursive DC digital filter. Moreover, the proposed structure possesses a favorable 2-D DC half-band (DC-HB) property that allows about half of the 2-D SHP recursive DALF’s coefficients to be zero. This leads to considerable savings in computational burden for implementation. To ensure the stability of a designed 2-D SHP recursive DC digital lattice filter, some necessary constraints on the phase of the 2-D SHP recursive DALF during the design process are presented. Design of a 2-D diamond-shape decimation/interpolation filter is presented for illustration and comparison.

Keywords: All-pass digital filter, doubly complementary, lattice structure, symmetric half-plane digital filter, sampling rate conversion.

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Authors: Moorthi S., Meganathan D., Janarthanan D., Praveen Kumar P., J. Raja paul perinbam

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An efficient architecture for low jitter All Digital Phase Locked Loop (ADPLL) suitable for high speed SoC applications is presented in this paper. The ADPLL is designed using standard cells and described by Hardware Description Language (HDL). The ADPLL implemented in a 90 nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. The simulation result shows that PLL has cycle to cycle jitter of 164 ps and period jitter of 100 ps at 100MHz. Since the digitally controlled oscillator (DCO) can achieve both high resolution and wide frequency range, it can meet the demands of system-level integration. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for System-on-Chip (SoC) applications.

Keywords: All Digital Phase Locked Loop (ADPLL), Systemon-Chip (SoC), Phase Locked Loop (PLL), Very High speedIntegrated Circuit (VHSIC) Hardware Description Language(VHDL), Digitally Controlled Oscillator (DCO), Phase frequencydetector (PFD) and Voltage Controlled Oscillator (VCO).

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Authors: Jae Hyung Noh, Hang Geun Jeong

Abstract:

The charge-pump circuit is an important component in a phase-locked loop (PLL). The charge-pump converts Up and Down signals from the phase/frequency detector (PFD) into current. A conventional CMOS charge-pump circuit consists of two switched current sources that pump charge into or out of the loop filter according to two logical inputs. The mismatch between the charging current and the discharging current causes phase offset and reference spurs in a PLL. We propose a new charge-pump circuit to reduce the current mismatch by using a regulated cascode circuit. The proposed charge-pump circuit is designed and simulated by spectre with TSMC 0.18-μm 1.8-V CMOS technology.

Keywords: Phase-locked loop (PLL), charge-pump, phase/frequency detector (PFD), regulated cascode.

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Authors: S. Chauhan, T.P.K. Grewal, S.K. Aggarwal, V.K. Srivastava

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Solution for the complete removal of carbon monoxide from the exhaust gases still poses a challenge to the researchers and this problem is still under development. Modeling for reduction of carbon monoxide is carried out using heterogeneous reaction using low cost non-noble metal based catalysts for the purpose of controlling emissions released to the atmosphere. A simple one-dimensional model was developed for the monolith using hopcalite catalyst. The converter is assumed to be an adiabatic monolith operating under warm-up conditions. The effect of inlet gas temperatures and catalyst loading on carbon monoxide reduction during cold start period in the converter is analysed.

Keywords: carbon monoxide, catalytic, modeling, monolith

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Authors: B. Ferdousi

Abstract:

This study examines the adoption of digital technology in academic assessment or e-assessment in higher education. The main focus of this research is to determine the impact of advanced digital technology on different assessment techniques such as formative assessment and summative assessment. The goal of this study is to critically evaluate the selection of different assessment methods using digital technology to enhance assessment for more effective learning. Given the increasing use of digital technology in the assessment of students' achievement in the learning process, this research is significant. Based on a literature review of different assessment techniques using technology, this study focuses on the formative and summative techniques of e-assessment. The paper offers an in-depth analysis of the innovative and creative use of digital technology in assessment. The findings of this research will enhance knowledge and in-depth understanding of using technology in assessment, especially in active learning environments, in higher academic institutions.

Keywords: E-assessment techniques, assessment for learning, assessment of learning, digital technology.

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Authors: D. Krishnaveni, M. Geetha Priya

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Applications of reversible logic gates in the design of complex integrated circuits provide power optimization.  This technique finds a great use in low power CMOS design, optical computing, quantum computing and nanotechnology. This paper proposes a reversible signed division circuit that can divide an n-bit signed dividend with an n-bit signed divisor using non-restoration division logic. The proposed design adequately addresses the ‘delay’ there by improving the efficiency of the circuit. An attempt is made to design a reversible signed division circuit. This paper provides a threshold to build more complex arithmetic systems using reversible logic, thus increasing the performance of computing systems.

Keywords: Low power CMOS, quantum computing, reversible logic gates, shift register, signed division.

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Authors: Mohamed Kholif, Suaad Awad Mohamed

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In this paper we present semantic assistant agent (SAA), an open source digital library agent which takes user query for finding information in the digital library and takes resources- metadata and stores it semantically. SAA uses Semantic Web to improve browsing and searching for resources in digital library. All metadata stored in the library are available in RDF format for querying and processing by SemanSreach which is a part of SAA architecture. The architecture includes a generic RDF-based model that represents relationships among objects and their components. Queries against these relationships are supported by an RDF triple store.

Keywords: Digital Library, Dublin Core, Ontology, Semantic web.

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Authors: Syed Islam, Yiyun Huang, Sebastian Magierowski, Ebrahim Ghafar-Zadeh

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This paper presents system level CMOS solid-state nanopore techniques enhancement for speedup next generation molecular recording and high throughput channels. This discussion also considers optimum number of base-pair (bp) measurements through channel as an important role to enhance potential read accuracy. Effective power consumption estimation offered suitable range of multi-channel configuration. Nanopore bp extraction model in statistical method could contribute higher read accuracy with longer read-length (200 < read-length). Nanopore ionic current switching with Time Multiplexing (TM) based multichannel readout system contributed hardware savings.

Keywords: DNA, Nanopore, Amplifier, ADC, Multichannel.

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Authors: Nasser Erfani Majd, Mojtaba Lotfizad

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In this paper, an ultra low power and low jitter 12bit CMOS digitally controlled oscillator (DCO) design is presented. Based on a ring oscillator implemented with low power Schmitt trigger based inverters. Simulation of the proposed DCO using 32nm CMOS Predictive Transistor Model (PTM) achieves controllable frequency range of 550MHz~830MHz with a wide linearity and high resolution. Monte Carlo simulation demonstrates that the time-period jitter due to random power supply fluctuation is under 31ps and the power consumption is 0.5677mW at 750MHz with 1.2V power supply and 0.53-ps resolution. The proposed DCO has a good robustness to voltage and temperature variations and better linearity comparing to the conventional design.

Keywords: digitally controlled oscillator (DCO), low power, jitter; good linearity, robust

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Authors: Badr M. Alshammari, A. Rabeh, A. K. Mohamed

Abstract:

This paper presents the modeling and the control of a grid-connected photovoltaic system (PVS). Firstly, the MPPT control of the PVS and its associated DC/DC converter has been analyzed in order to extract the maximum of available power. Secondly, the control system of the grid side converter (GSC) which is a three-phase voltage source inverter (VSI) has been presented. A special attention has been paid to the control algorithms of the GSC converter during grid voltages imbalances. Especially, three different control objectives are to achieve; the mitigation of the grid imbalance adverse effects, at the point of common coupling (PCC), on the injected currents, the elimination of double frequency oscillations in active power flow, and the elimination of double frequency oscillations in reactive power flow. Simulation results of two control strategies have been performed via MATLAB software in order to demonstrate the particularities of each control strategy according to power quality standards.

Keywords: Renewable energies, photovoltaic systems, DC link, voltage source inverter, space vector SVPWM, unbalanced voltage dips, symmetrical components.

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Authors: Susmita Sahoo, Madhumanti Datta, Rajib Kar

Abstract:

The resistive-inductive-capacitive behavior of long interconnects which are driven by CMOS gates are presented in this paper. The analysis is based on the ¤Ç-model of a RLC load and is developed for submicron devices. Accurate and analytical expressions for the output load voltage, the propagation delay and the short circuit power dissipation have been proposed after solving a system of differential equations which accurately describe the behavior of the circuit. The effect of coupling capacitance between input and output and the short circuit current on these performance parameters are also incorporated in the proposed model. The estimated proposed delay and short circuit power dissipation are in very good agreement with the SPICE simulation with average relative error less than 6%.

Keywords: Delay, Inverter, Short Circuit Power, ¤Ç-Model, RLCInterconnect, VLSI

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Authors: A. K. Razilan, A. B. Amzari, B. Ap-azli, A. R. Safawi

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Explosion in information management and information system technology has brought dramatic changes in learning and library system environments. The use of academic digital libraries does witness the spectacular impact on academic societies’ way of performing their study in Malaysia, a country with a multi-racial people. This paper highlights a research on examining the socio-demographic differences on the preference and use of academic digital libraries as compared to physical libraries at higher learning institutions. Findings indicate that preference towards digital libraries differed between ethnicity, gender and university. However none of the socio-demographic factors is statistically significant in terms of the use of digital libraries.

Keywords: Socio-demographic, academic digital library, preference, use.

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Authors: Pejman Hosseiniun, Rose Shayeghi, Iman Rahbari, Mohamad Reza Kalhor

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CNFET has emerged as an alternative material to silicon for high performance, high stability and low power SRAM design in recent years. SRAM functions as cache memory in computers and many portable devices. In this paper, a new SRAM cell design based on CNFET technology is proposed. The proposed SRAM cell design for CNFET is compared with SRAM cell designs implemented with the conventional CMOS and FinFET in terms of speed, power consumption, stability, and leakage current. The HSPICE simulation and analysis show that the dynamic power consumption of the proposed 8T CNFET SRAM cell’s is reduced about 48% and the SNM is widened up to 56% compared to the conventional CMOS SRAM structure at the expense of 2% leakage power and 3% write delay increase.

Keywords: SRAM cell, CNFET, low power, HSPICE.

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Authors: P. Vaculik

Abstract:

The newest semiconductor devices on the market are MOSFET transistors based on the silicon carbide – SiC. This material has exclusive features thanks to which it becomes a better switch than Si – silicon semiconductor switch. There are some special features that need to be understood to enable the device’s use to its full potential. The advantages and differences of SiC MOSFETs in comparison with Si IGBT transistors have been described in first part of this article. Second part describes driver for SiC MOSFET transistor and last part of article represents SiC MOSFET in the application of buck converter (step-down) and design of simple RC snubber. 

Keywords: SiC, Si, MOSFET, IGBT, SBD, RC snubber.

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Authors: Chen-Chien Hsu, Chun-Hui Gao

Abstract:

In this paper, a PSO-based approach is proposed to derive a digital controller for redesigned digital systems having an interval plant based on resemblance of the extremal gain/phase margins. By combining the interval plant and a controller as an interval system, extremal GM/PM associated with the loop transfer function can be obtained. The design problem is then formulated as an optimization problem of an aggregated error function revealing the deviation on the extremal GM/PM between the redesigned digital system and its continuous counterpart, and subsequently optimized by a proposed PSO to obtain an optimal set of parameters for the digital controller. Computer simulations have shown that frequency responses of the redesigned digital system having an interval plant bare a better resemblance to its continuous-time counter part by the incorporation of a PSO-derived digital controller in comparison to those obtained using existing open-loop discretization methods.

Keywords: Digital redesign, Extremal systems, Particle swarm optimization, Uncertain interval systems

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Authors: K. Divya, G. Sugumaran

Abstract:

This paper proposes an improved Maximum Power Point Tracking of PhotoVoltaic system using Deterministic Partical Swarm Optimization technique. This method has the ability to track the maximum power under varying environmental conditions i.e. partial shading conditions. The advantage of this method, particles moves in the restricted value of velocity to achieve the maximum power. SEPIC converter is employed to boost up the voltage of PV system. To estimate the value of the proposed method, MATLAB simulation carried out under partial shading condition.

Keywords: DPSO, Partial shading condition, P&O, PV, SEPIC.

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