Search results for: Amita%20Maheshwari

Authors: Shobha Sharma, Amita Dev, Akanksha Kant

Abstract:

Digital signal processor, image signal processor and FIR filters have multipliers as an important part of their design. On the basis of Vedic mathematics, Vedic multipliers have come out to be very fast multipliers. One of the image processing applications is edge detection. This research presents a small area and high speed 8 bit Vedic multiplier system comprising of compressor based adders. This results in faster edge detection. This architecture is tested on Xilinx vertex 4 FPGA board and simulations were carried out using the Xilinx synthesis tool. Comparisons are made and this system is found to be smaller in area with high speed (the lesser propagation delay). This compressor based Vedic multiplier is 1.1 times speedier than a typical Vedic multiplier. Also, this Vedic Multiplier is 2 times speedier than a ‘simple’ multiplier.

Keywords: Detection of edges, Vedic multiplier, image processing, Urdhva Tiryakbhyam sutra.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1765

Authors: Shobha Sharma, Amita Dev

Abstract:

This research paper presents highly optimized barrel shifter at 22nm Hi K metal gate strained Si technology node. This barrel shifter is having a unique combination of static and dynamic body bias which gives lowest power delay product. This power delay product is compared with the same circuit at same technology node with static forward biasing at ‘supply/2’ and also with normal reverse substrate biasing and still found to be the lowest. The power delay product of this barrel sifter is .39362X10-17J and is lowered by approximately 78% to reference proposed barrel shifter at 32nm bulk CMOS technology. Power delay product of barrel shifter at 22nm Hi K Metal gate technology with normal reverse substrate bias is 2.97186933X10-17J and can be compared with this design’s PDP of .39362X10-17J. This design uses both static and dynamic substrate biasing and also has approximately 96% lower power delay product compared to only forward body biased at half of supply voltage. The NMOS model used are predictive technology models of Arizona state university and the simulations to be carried out using HSPICE simulator.

Keywords: Dynamic body biasing, highly optimized barrel shifter, PDP, Static body biasing.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1845

Authors: Shobha Sharma, Amita Dev

Abstract:

Data driven dynamic logic is the high speed dynamic circuit with low area. The clock of the dynamic circuit is removed and data drives the circuit instead of clock for precharging purpose. This data driven dynamic nand gate is given static forward substrate biasing of Vsupply/2 as well as the substrate bias is connected to the input data, resulting in dynamic substrate bias. The dynamic substrate bias gives the shortest propagation delay with a penalty on the power dissipation. Propagation delay is reduced by 77.8% compared to the normal reverse substrate bias Data driven dynamic nand. Also dynamic substrate biased D3nand’s propagation delay is reduced by 31.26% compared to data driven dynamic nand gate with static forward substrate biasing of Vdd/2. This data driven dynamic nand gate with dynamic body biasing gives us the highest speed with no area penalty and finds its applications where power penalty is acceptable. Also combination of Dynamic and static Forward body bias can be used with reduced propagation delay compared to static forward biased circuit and with comparable increase in an average power. The simulations were done on hspice simulator with 22nm High-k metal gate strained Si technology HP models of Arizona State University, USA.

Keywords: Data driven nand gate, dynamic substrate biasing, nand gate, static substrate biasing.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1564

Authors: Manjusha R. Vagal, Shyam K. Shrivastava, Umesh Mahantshetty, Sudeep Gupta, Supriya Chopra, Reena Engineer, Amita Maheshwari, Atul Buduk

Abstract:

Vaginal stenosis is a common side effect associated with pelvic radiotherapy in cervical cancer patients which contributes negatively to woman’s health and prevents adequate vaginal/cervical examination. Vaginal dilation with a dilator is routine practice and is internationally advocated as a prophylactic measure to preserve vaginal patency. This retrospective study was carried out with the aim to know the usefulness of vaginal dilation following pelvic radiation therapy in cervical cancer patients in India. Data from medical records of 183 cervical cancer patients, which met the study criteria, were collected related to the stage of the disease, treatment received, commencement period of dilation post radiation therapy, sexual status and side effects associated to dilation practice. Data related to vaginal dimensions as per the length of insertion of a small, medium and large dilator were collected on regular follow-ups until 36 months and/or more. Vaginal dimensions as measured with the length of medium dilator insertion were used for analysis of dilation therapy results using paired t-test. Patients who underwent vaginal dilation with dilator maintained vaginal patency, also the mean vaginal length significantly increased, from 8.02 cm ± 2.69 to 9.96 ± 2.89 cm with a p value <0.001. There was no significant difference found on vaginal patency with different intervals of initiation of dilation therapy. At the third year and more following dilation therapy, significant increase in vaginal length observed with a p value of 0.0001 in both sexually active and inactive patients. Compilation of vaginal dosage during brachytherapy was inadequate, and hence, the secondary objective of the study to determine the effect of radiotherapy on the outcome of rehabilitation intervention was not studied in detail. This retrospective study has found that dilation therapy with vaginal dilators post pelvic radiotherapy is effective in preventing vaginal stenosis and improving vaginal patency and cannot be substituted with vaginal intercourse. Sexual quality of life assessment in the Indian population needs much attention.

Keywords: Dilator, sexually active, vaginal dilation, vaginal stenosis.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1413