Search results for: A. Sarchami
2 Three Dimensional Numerical Simulation of a Full Scale CANDU Reactor Moderator to Study Temperature Fluctuations
Authors: A. Sarchami, N. Ashgriz, M. Kwee
Abstract:
Threedimensional numerical simulations are conducted on a full scale CANDU Moderator and Transient variations of the temperature and velocity distributions inside the tank are determined. The results show that the flow and temperature distributions inside the moderator tank are three dimensional and no symmetry plane can be identified.Competition between the upward moving buoyancy driven flows and the downward moving momentum driven flows, results in the formation of circulation zones. The moderator tank operates in the buoyancy driven mode and any small disturbances in the flow or temperature makes the system unstable and asymmetric. Different types of temperature fluctuations are noted inside the tank: (i) large amplitude are at the boundaries between the hot and cold (ii) low amplitude are in the core of the tank (iii) high frequency fluctuations are in the regions with high velocities and (iv) low frequency fluctuations are in the regions with lower velocities.
Keywords: Bruce, Fluctuations, Numerical, Temperature, Thermal hydraulics
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 19301 A Low Power SRAM Base on Novel Word-Line Decoding
Authors: Arash Azizi Mazreah, Mohammad T. Manzuri Shalmani, Hamid Barati, Ali Barati, Ali Sarchami
Abstract:
This paper proposes a low power SRAM based on five transistor SRAM cell. Proposed SRAM uses novel word-line decoding such that, during read/write operation, only selected cell connected to bit-line whereas, in conventional SRAM (CV-SRAM), all cells in selected row connected to their bit-lines, which in turn develops differential voltages across all bit-lines, and this makes energy consumption on unselected bit-lines. In proposed SRAM memory array divided into two halves and this causes data-line capacitance to reduce. Also proposed SRAM uses one bit-line and thus has lower bit-line leakage compared to CV-SRAM. Furthermore, the proposed SRAM incurs no area overhead, and has comparable read/write performance versus the CV-SRAM. Simulation results in standard 0.25μm CMOS technology shows in worst case proposed SRAM has 80% smaller dynamic energy consumption in each cycle compared to CV-SRAM. Besides, energy consumption in each cycle of proposed SRAM and CV-SRAM investigated analytically, the results of which are in good agreement with the simulation results.Keywords: SRAM, write Operation, read Operation, capacitances, dynamic energy consumption.
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