Search results for: vertical silicon nanowire.

Authors: Z. X. Chen, T. S. Phua, X. P. Wang, G. -Q. Lo, D. -L. Kwong

Abstract:

This paper presents device simulations on the vertical silicon nanowire tunneling FET (VSiNW TFET). Simulations show that a narrow nanowire and thin gate oxide is required for good performance, which is expected even for conventional MOSFETs. The gate length also needs to be more than the nanowire diameter to prevent short channel effects. An effect more unique to TFET is the need for abrupt source to channel junction, which is shown to improve the performance. The ambipolar effect suppression by reducing drain doping concentration is also explored and shown to have little or no effect on performance.

Keywords: Device simulation, MEDICI, tunneling FET (TFET), vertical silicon nanowire.

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Authors: Z. X. Chen, N. Singh, D.-L. Kwong

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This paper presents a vertical silicon nanowire n- MOSFET integrated with a CMOS-compatible fully-silicided (FUSI) NiSi2 gate. Devices with nanowire diameter of 50nm show good electrical performance (SS < 70mV/dec, DIBL < 30mV/V, Ion/Ioff > 107). Most significantly, threshold voltage tunability of about 0.2V is shown. Although threshold voltage remains low for the 50nm diameter device, it is expected to become more positive as nanowire diameter reduces.

Keywords: NiSi , fully-silicided (FUSI) gate, vertical siliconnanowire (SiNW), CMOS compatible.

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Authors: N. Shen, T. T. Le, H. Y. Yu, Z. X. Chen, K. T. Win, N. Singh, G. Q. Lo, D. -L. Kwong

Abstract:

In this paper, we present a vertical nanowire thin film transistor with gate-all-around architecture, fabricated using CMOS compatible processes. A novel method of fabricating polysilicon vertical nanowires of diameter as small as 30 nm using wet-etch is presented. Both n-type and p-type vertical poly-silicon nanowire transistors exhibit superior electrical characteristics as compared to planar devices. On a poly-crystalline nanowire of 30 nm diameter, high Ion/Ioff ratio of 106, low drain-induced barrier lowering (DIBL) of 50 mV/V, and low sub-threshold slope SS~100mV/dec are demonstrated for a device with channel length of 100 nm.

Keywords: Nanowire (NW), Gate-all-around (GAA), polysilicon (poly-Si), thin-film transistor (TFT).

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Authors: N. Shen, Z. X. Chen, K.D. Buddharaju, H. M. Chua, X. Li, N. Singh, G.Q Lo, D.-L. Kwong

Abstract:

In this paper, we present a vertical wire NMOS device fabricated using CMOS compatible processes. The impact of temperature on various device parameters is investigated in view of usual increase in surrounding temperature with device density.

Keywords: Gate-all-around, temperature dependence, silicon nanowire

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Authors: Xiang Li, Zhixian Chen, Zheng Fang, Aashit Kamath, Xinpeng Wang, Navab Singh, Guo-Qiang Lo, Dim-Lee Kwong

Abstract:

We integrate TiN/Ni/HfO2/Si RRAM cell with a vertical gate-all-around (GAA) nanowire transistor to achieve compact 4F2 footprint in a 1T1R configuration. The tip of the Si nanowire (source of the transistor) serves as bottom electrode of the memory cell. Fabricated devices with nanowire diameter ~ 50nm demonstrate ultra-low current/power switching; unipolar switching with 10μA/30μW SET and 20μA/30μW RESET and bipolar switching with 20nA/85nW SET and 0.2nA/0.7nW RESET. Further, the switching current is found to scale with nanowire diameter making the architecture promising for future scaling.

Keywords: RRAM, 1T1R, gate-all-around FET, nanowire FET, vertical MOSFETs

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Authors: Amin Nekoubin, Abdolamir Nekoubin

Abstract:

Vertical ZnO nanowire array films were synthesized based on aqueous method for sensing applications. ZnO nanowires were investigated structurally using X-ray diffraction (XRD) and scanning electron microscopy (SEM). The gas-sensing properties of ZnO nanowires array films are studied. It is found that the ZnO nanowires array film sensor exhibits excellent sensing properties towards O2 and CO2 at 100 °C with the response time shorter than 5 s. High surface area / volume ratio of vertical ZnO nanowire and high mobility accounts for the fast response and recovery. The sensor response was measured in the range from 100 to 500 ppm O2 and CO2 in this study.

Keywords: Gas sensor, semiconductor, ZnO, Nanowire array

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Authors: Y. Li, K. Buddharaju, N. Singh, G. Q. Lo, S. J. Lee

Abstract:

Silicon nanowire (SiNW) based thermoelectric device (TED) has potential applications in areas such as chip level cooling/ energy harvesting. It is a great challenge however, to assemble an efficient device with these SiNW. The presence of parasitic in the form of interfacial electrical resistance will have a significant impact on the performance of the TED. In this work, we explore the effect of the electrical contact resistance on the performance of a TED. Numerical simulations are performed on SiNW to investigate such effects on its cooling performance. Intrinsically, SiNW individually without the unwanted parasitic effect has excellent cooling power density. However, the cooling effect is undermined with the contribution of the electrical contact resistance.

Keywords: Thermoelectric, silicon, nanowire, electrical contact resistance, parasitics.

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Authors: Fatemeh Karimi, Morteza Fathipour, Hamdam Ghanatian, Vala Fathipour

Abstract:

In this paper electrical characteristics of various kinds of multiple-gate silicon nanowire transistors (SNWT) with the channel length equal to 7 nm are compared. A fully ballistic quantum mechanical transport approach based on NEGF was employed to analyses electrical characteristics of rectangular and cylindrical silicon nanowire transistors as well as a Double gate MOS FET. A double gate, triple gate, and gate all around nano wires were studied to investigate the impact of increasing the number of gates on the control of the short channel effect which is important in nanoscale devices. Also in the case of triple gate rectangular SNWT inserting extra gates on the bottom of device can improve the application of device. The results indicate that by using gate all around structures short channel effects such as DIBL, subthreshold swing and delay reduces.

Keywords: SNWT (silicon nanowire transistor), non equilibriumGreen's function (NEGF), double gate (DG), triple gate (TG), multiple gate, cylindrical nano wire (CW), rectangular nano wire(RW), Poisson_ Schrödinger solver, drain induced barrier lowering(DIBL).

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Authors: Fatemeh Karimi, Morteza Fathipour, Hamdam Ghanatian, Vala Fathipour

Abstract:

In this paper we investigate the electrical characteristics of a new structure of gate all around strained silicon nanowire field effect transistors (FETs) with dual dielectrics by changing the radius (RSiGe) of silicon-germanium (SiGe) wire and gate dielectric. Indeed the effect of high-κ dielectric on Field Induced Barrier Lowering (FIBL) has been studied. Due to the higher electron mobility in tensile strained silicon, the n-type FETs with strained silicon channel have better drain current compare with the pure Si one. In this structure gate dielectric divided in two parts, we have used high-κ dielectric near the source and low-κ dielectric near the drain to reduce the short channel effects. By this structure short channel effects such as FIBL will be reduced indeed by increasing the RSiGe, ID-VD characteristics will be improved. The leakage current and transfer characteristics, the threshold-voltage (Vt), the drain induced barrier height lowering (DIBL), are estimated with respect to, gate bias (VG), RSiGe and different gate dielectrics. For short channel effects, such as DIBL, gate all around strained silicon nanowire FET have similar characteristics with the pure Si one while dual dielectrics can improve short channel effects in this structure.

Keywords: SNWT (silicon nanowire transistor), Tensile Strain, high-κ dielectric, Field Induced Barrier Lowering (FIBL), cylindricalnano wire (CW), drain induced barrier lowering (DIBL).

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Authors: Y. Li, K. Buddharaju, X. P. Wang

Abstract:

The mechanism of nickel (Ni) metallization in silicon-germanium (Si_0.5Ge_0.5) alloy nanowire (NW) was studied. Transmission electron microscope imaging with in-situ annealing was conducted at temperatures of 200^oC to 600°C. During rapid formation of Ni germanosilicide, loss of material from from the SiGe NW occurred which led to the formation of a thin Ni germanosilicide filament and eventual void. Energy dispersive X-ray spectroscopy analysis along the SiGe NW before and after annealing determined that Ge atoms tend to out-diffuse from the Ni germanosilicide towards the Ni source in the course of annealing. A model for the Ni germanosilicide formation in SiGe NW is proposed to explain this observation.

Keywords: SiGe, nanowires, germanosilicide.

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Authors: J. Davoodi, F. Katouzi

Abstract:

The aim of this research was to calculate the thermal properties of Au3Ni Nanowire. The molecular dynamics (MD) simulation technique was used to obtain the effect of radius size on the energy, the melting temperature and the latent heat of fusion at the isobaric-isothermal (NPT) ensemble. The Quantum Sutton-Chen (Q-SC) many body interatomic potentials energy have been used for Gold (Au) and Nickel (Ni) elements and a mixing rule has been devised to obtain the parameters of these potentials for nanowire stats. Our MD simulation results show the melting temperature and latent heat of fusion increase upon increasing diameter of nanowire. Moreover, the cohesive energy decreased with increasing diameter of nanowire.

Keywords: Au3Ni Nanowire, Thermal properties, Molecular dynamics simulation

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Authors: Sang Hoon Lee, Tae Il Lee, Su Jeong Lee, Jae Min Myoung

Abstract:

In order to manufacture short gap single Si nanowire (NW) field effect transistor (FET) by imprinting and transferring method, we introduce the method using Al2O3 sacrificial layer. The diameters of cylindrical Si NW addressed between Au electrodes by dielectrophoretic (DEP) alignment method are controlled to 106, 128, and 148 nm. After imprinting and transfer process, cylindrical Si NW is embedded in PVP adhesive and dielectric layer. By curing transferred cylindrical Si NW and Au electrodes on PVP-coated p++ Si substrate with 200nm-thick SiO2, 3μm gap Si NW FET fabrication was completed. As the diameter of embedded Si NW increases, the mobility of FET increases from 80.51 to 121.24 cm2/V·s and the threshold voltage moves from –7.17 to –2.44 V because the ratio of surface to volume gets reduced.

Keywords: Al2O3 Sacrificial transfer layer, cylindrical silicon nanowires, Dielectrophorestic alignment, Field effect transistor.

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Authors: K. E. Kaharudin, A. H. Hamidon, F. Salehuddin

Abstract:

Vertical Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is believed to suppress various short channel effect problems. The gate to channel coupling in vertical DG-MOSFET are doubled, thus resulting in higher current density. By having two gates, both gates are able to control the channel from both sides and possess better electrostatic control over the channel. In order to ensure that the transistor possess a superb turn-off characteristic, the subs-threshold swing (SS) must be kept at minimum value (60-90mV/dec). By utilizing SILVACO TCAD software, an n-channel vertical DG-MOSFET was successfully designed while keeping the sub-threshold swing (SS) value as minimum as possible. From the observation made, the value of sub-threshold swing (SS) was able to be varied by adjusting the height of the silicon pillar. The minimum value of sub-threshold swing (SS) was found to be 64.7mV/dec with threshold voltage (V_TH) of 0.895V. The ideal height of the vertical DG-MOSFET pillar was found to be at 0.265 µm.

Keywords: DG-MOSFET, pillar, SCE, vertical

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Authors: Seyed Ali Sedigh Zyabari, A. Zarifkar

Abstract:

Single photon detectors have been fabricated NbN nano wire. These detectors are fabricated from high quality, ultra high vacuum sputtered NbN thin films on a sapphire substrate. In this work a typical schematic of the nanowire Single Photon Detector structure and then driving and measurement electronic circuit are shown. The response of superconducting nanowire single photon detectors during a photo detection event, is modeled by a special electrical circuits (two circuit). Finally, current through the wire is calculated by solving equations of models.

Keywords: NbN, nanowire meander, superconducting single photon detector, kinetic inductance.

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Authors: Ajay Kushwaha, Hemen Kalita, M. Aslam

Abstract:

Post growth annealing of solution grown ZnO nanowire array is performed under controlled oxygen ambience. The role of annealing over surface defects and their consequence on dark/photo-conductivity and photosensitivity of nanowire array is investigated. Surface defect properties are explored using various measurement tools such as contact angle, photoluminescence, Raman spectroscopy and XPS measurements. The contact angle of the NW films reduces due to oxygen annealing and nanowire film surface changes from hydrophobic (96°) to hydrophilic (16°). Raman and XPS spectroscopy reveal that oxygen annealing improves the crystal quality of the nanowire films. The defect band emission intensity (relative to band edge emission, ID/IUV) reduces from 1.3 to 0.2 after annealing at 600 °C at 10 SCCM flow of oxygen. An order enhancement in dark conductivity is observed in O2 annealed samples, while photoconductivity is found to be slightly reduced due to lower concentration of surface related oxygen defects.

Keywords: Zinc Oxide, Surface defects, Photoluminescence, Photoconductivity, Photosensor and Nanowire thin film.

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Authors: Ashot Navasardian, Mariam Vardanian, Vladik Vardanian

Abstract:

The photovoltaic and the semiconductor industries are in growth and it is necessary to supply a large amount of silicon to maintain this growth. Since silicon is still the best material for the manufacturing of solar cells and semiconductor components so the pure silicon like solar grade and semiconductor grade materials are demanded. There are two main routes for silicon production: metallurgical and chemical. In this article, we reviewed the electrotecnological installations and systems for semiconductor manufacturing. The main task is to design the installation which can produce SOG Silicon from river sand by one work unit.

Keywords: Metallurgical grade silicon, solar grade silicon, impurity, refining, plasma.

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Authors: Shiyang Zhu, G. Q. Lo, D. L. Kwong

Abstract:

Silicon photonics has generated an increasing interest in recent years mainly for optical communications optical interconnects in microelectronic circuits or bio-sensing applications. The development of elementary passive and active components (including detectors and modulators), which are mainly fabricated on the silicon on insulator platform for CMOS-compatible fabrication, has reached such a performance level that the integration challenge of silicon photonics with microelectronic circuits should be addressed. Since crystalline silicon can only be grown from another silicon crystal, making it impossible to deposit in this state, the optical devices are typically limited to a single layer. An alternative approach is to integrate a photonic layer above the CMOS chip using back-end CMOS fabrication process. In this paper, various materials, including silicon nitride, amorphous silicon, and polycrystalline silicon, for this purpose are addressed.

Keywords: Silicon photonics, CMOS, Integration.

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Authors: W. L. Liong, Srimala Sreekantan, Sabar D. Hutagalung

Abstract:

The effect of concentration of reduction agent of sodium borohydrate (NaBH4) on the properties of silicon nanoparticles synthesized via microemulsion route is reported. In this work, the concentration of the silicon tetrachloride (SiCl4) that served as silicon source with sodium hydroxide (NaOH) and polyethylene glycol (PEG) as stabilizer and surfactant, respectively, are keep fixed. Four samples with varied concentration of NaBH4 from 0.05 M to 0.20 M were synthesized. It was found that the lowest concentration of NaBH4 gave better formation of silicon nanoparticles.

Keywords: Microelmusion, nanoparticles, reduction, silicon

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Authors: M. R. Gad El- Kareem, A. M. K. Abdel Aal, A. Y. Mohamed

Abstract:

During 2011 and 2012 seasons, Zaghloul date palms received four sprays of silicon (Si) at 0.05 to 0.1% and selenium (Se) at 0.01 to 0.02%. Growth, nutritional status, yield as well as physical and chemical characteristics of the fruits in response to application of silicon and selenium were investigated. Single and combined applications of silicon at 0.05 to 0.1% and selenium at 0.01 to 0.02% was very effective in enhancing the leaf area, total chlorophylls, percentages of N, P and K in the leaves, yield, bunch weight as well as physical and chemical characteristics of the fruits in relative to the check treatment. Silicon was superior to selenium in this respect. Combined application was favorable than using each alone in this connection. Treating Zaghloul date palms four times with a mixture of silicon at 0.05% + selenium at 0.01% resulted in an economical yield and producing better fruit quality.

Keywords: Date Palms, Zaghloul, Silicon, Selenium, leaf area.

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Authors: A. Ould-Abbas, M. Bouchaour, , M. Madani, D. Trari, O. Zeggai, M. Boukais, N.-E.Chabane-Sari

Abstract:

The porous silicon (PS), formed from the anodization of a p+ type substrate silicon, consists of a network organized in a pseudo-column as structure of multiple side ramifications. Structural micro-topology can be interpreted as the fraction of the interconnected solid phase contributing to thermal transport. The reduction of dimensions of silicon of each nanocristallite during the oxidation induced a reduction in thermal conductivity. Integration of thermal sensors in the Microsystems silicon requires an effective insulation of the sensor element. Indeed, the low thermal conductivity of PS consists in a very promising way in the fabrication of integrated thermal Microsystems.In this work we are interesting in the measurements of thermal conductivity (on the surface and in depth) of PS by the micro-Raman spectroscopy. The thermal conductivity is studied according to the parameters of anodization (initial doping and current density. We also, determine porosity of samples by spectroellipsometry.

Keywords: micro-Raman spectroscopy, mono-crysatl silicon, porous silicon, thermal conductivity

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Authors: N. I. Kargin, G. K. Safaraliev, A. S. Gusev, A. O. Sultanov, N. V. Siglovaya, S. M. Ryndya, A. A. Timofeev

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In this paper, an experimental and theoretical study of the processes of mesoporous silicon carbonization during the formation of buffer layers for the subsequent epitaxy of 3C-SiC films and related wide-band-gap semiconductors is performed. Experimental samples were obtained by the method of chemical vapor deposition and investigated by scanning electron microscopy. Analytic expressions were obtained for the effective diffusion factor and carbon atoms diffusion length in a porous system. The proposed model takes into account the processes of Knudsen diffusion, coagulation and overgrowing of pores during the formation of a silicon carbide layer.

Keywords: Silicon carbide, porous silicon, carbonization, electrochemical etching, diffusion.

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Authors: Shahrazed Medeghri, Saad Hamzaoui, Mokhtar Zerdali

Abstract:

The metallurgical grade silicon (MG-Si) is obtained from the reduction of silica (SiO₂) in an induction furnace or an electric arc furnace. Impurities inherent in reduction process also depend on the quality of the raw material used. Among the applications of the silicon, it is used as a substrate for the photovoltaic conversion of solar energy and this conversion is wider as the purity of the substrate is important. Research is being done where the purpose is looking for new methods of manufacturing and purification of silicon, as well as new materials that can be used as substrates for the photovoltaic conversion of light energy. In this research, the technique of production of silicon in an induction furnace, using a high vacuum for fusion. Diatomaceous Silica (SiO2) used is 99 mass% initial purities, the carbon used is 6N of purity and the particle size of 63μm as starting materials. The final achieved purity of the material was above 50% by mass. These results demonstrate that this method is a technically reliable, and allows obtaining a better return on the amount 50% of silicon.

Keywords: Induction, amorphous silica, carbon microstructure, silicon.

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Authors: George C. Yao, Chao-Yu Tu, Wei-Chung Chen, Fung-Wen Kuo, Yu-Shan Chang

Abstract:

Building structures are subjected to both horizontal and vertical ground motions during earthquakes, but only the horizontal ground motion has been extensively studied and considered in design. Most of the prevailing seismic codes assume the vertical component to be 1/2 to 2/3 of the horizontal one. In order to understand the building responses from vertical ground motions, many earthquakes records are studied in this paper. System identification methods (ARX Model) are used to analyze the strong motions and to find out the characteristics of the vertical amplification factors and the natural frequencies of buildings. Analysis results show that the vertical amplification factors for high-rise buildings and low-rise building are 1.78 and 2.52 respectively, and the average vertical amplification factor of all buildings is about 2. The relationship between the vertical natural frequency and building height was regressed to a suggested formula in this study. The result points out an important message; the taller the building is, the greater chance of resonance of vertical vibration on the building will be.

Keywords: Vertical ground motion, vertical amplification factor, natural frequency, component.

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Authors: Li Long, Thomas Ortlepp

Abstract:

The transport properties of carriers in polycrystalline silicon film affect the performance of polycrystalline silicon-based devices. They depend strongly on the grain structure, grain boundary trap properties and doping concentration, which in turn are determined by the film deposition and processing conditions. Based on the properties of charge carriers, phonons, grain boundaries and their interactions, the thermoelectric properties of polycrystalline silicon are analyzed with the relaxation time approximation of the Boltzmann transport equation. With this approach, thermal conductivity, electrical conductivity and Seebeck coefficient as a function of grain size, trap properties and doping concentration can be determined. Experiment on heavily doped polycrystalline silicon is carried out and measurement results are compared with the model.

Keywords: Conductivity, polycrystalline silicon, relaxation time approximation, Seebeck coefficient, thermoelectric property.

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Authors: Beibei Han, Yong-Jin Yoon, Muhammad Hamidullah, Angel Tsu-Hui Lin, Woo-Tae Park

Abstract:

This paper presents the design of a ring-shaped tri-axial fore sensor that can be incorporated into the tip of a guidewire for use in minimally invasive surgery (MIS). The designed sensor comprises a ring-shaped structure located at the center of four cantilever beams. The ringdesign allows surgical tools to be easily passed through which largely simplified the integration process. Silicon nanowires (SiNWs) are used aspiezoresistive sensing elementsembeddedon the four cantilevers of the sensor to detect the resistance change caused by the applied load.An integration scheme with new designed guidewire tip structure having two coils at the distal end is presented. Finite element modeling has been employed in the sensor design to find the maximum stress location in order to put the SiNWs at the high stress regions to obtain maximum output. A maximum applicable force of 5 mN is found from modeling. The interaction mechanism between the designed sensor and a steel wire has been modeled by FEM. A linear relationship between the applied load on the steel wire and the induced stress on the SiNWs were observed.

Keywords: Triaxial MEMS force sensor, Ring shape, Silicon Nanowire, Minimally invasive surgery.

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Authors: Qing Fang, Lianxi Jia, JunFeng Song, Xiaoguang Tu, Mingbin Yu, Andy Eu-jin Lim, Guo Qiang Lo

Abstract:

The first pn-type carrier-induced silicon Bragg-grating filter is demonstrated. The extinction-ratio modulations are 11.5 dB and 10 dB with reverse and forward biases, respectively. 8-Gpbs data rate is achieved with a reverse bias.

Keywords: Silicon photonics, Waveguide grating, Carrier-induced, Extinction-ratio modulation.

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Authors: Isao Tomita

Abstract:

The principle of all-silicon Raman lasers for an output wavelength of 1.3 μm is presented, which employs quasi-phase-matched structures and resonators to enhance the output power. 1.3-μm laser beams for GE-PONs in FTTH systems generated from a silicon device are very important because such a silicon device can be monolithically integrated with the silicon planar lightwave circuits (Si PLCs) used in the GE-PONs. This reduces the device fabrication processes and time and also optical losses at the junctions between optical waveguides of the Si PLCs and Si laser devices when compared with 1.3-μm III-V semiconductor lasers set on the Si PLCs employed at present. We show that the quasi-phase-matched Si Raman laser with resonators can produce about 174 times larger laser power at 1.3 μm (at maximum) than that without resonators for a Si waveguide of Raman gain 20 cm/GW and optical loss 1.2 dB/cm, pumped at power 10 mW, where the length of the waveguide is 3 mm and its cross-section is (1.5 μm)2.

Keywords: All-silicon raman laser, FTTH, GE-PON, quasi-phase-matched structure, resonator.

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Authors: Qing Fang, Lianxi Jia, Junfeng Song, Chao Li, Xianshu Luo, Mingbin Yu, Guoqiang Lo

Abstract:

In this paper, we demonstrated a 1 × 4 silicon photonic cascaded arrayed waveguide grating, which is fabricated on a SOI wafer with a 220 nm top Si layer and a 2µm buried oxide layer. The measured on-chip transmission loss of this cascaded arrayed waveguide grating is ~ 5.6 dB, including the fiber-to-waveguide coupling loss. The adjacent crosstalk is 33.2 dB. Compared to the normal single silicon photonic arrayed waveguide grating with a crosstalk of ~ 12.5 dB, the crosstalk of this device has been dramatically increased.

Keywords: Silicon photonic, arrayed waveguide grating, high-crosstalk, cascaded structure.

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Authors: V.Fathipour, M. A. Malakootian, S. Fathipour, M. Fathipour

Abstract:

In this paper we propose a novel RF LDMOS structure which employs a thin strained silicon layer at the top of the channel and the N-Drift region. The strain is induced by a relaxed Si0.8 Ge0.2 layer which is on top of a compositionally graded SiGe buffer. We explain the underlying physics of the device and compare the proposed device with a conventional LDMOS in terms of energy band diagram and carrier concentration. Numerical simulations of the proposed strained silicon laterally diffused MOS using a 2 dimensional device simulator indicate improvements in saturation and linear transconductance, current drivability, cut off frequency and on resistance. These improvements are however accompanied with a suppression in the break down voltage.

Keywords: High Frequency MOSFET, Design of RF LDMOS, Strained-Silicon, LDMOS.

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Authors: Wei Sun, Ruilin Zheng, Xuyuan Chen

Abstract:

Micro power sources are required to be used in autonomous microelectromechanical system (MEMS). In this paper,  we designed and fabricated a three dimensional (3D) MEMS supercapacitor, which is consisting of conformal silicon  dioxide/titanium/polypyrrole (PPy) layers on silicon substrate. At first, ''through-structure'' was fabricated on the silicon substrate by high-aspect-ratio deep reactive ion etching (DRIE) method, which enlarges the available surface area significantly. Then the SiO2/Ti/PPy layers grew sequentially on the ³through-structure´. Finally, the supercapacitor was investigated by electrochemical methods.

Keywords: MEMS, Supercapacitor, DRIE, 3D.

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