Search results for: p-type MOSFETs device
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 754

Search results for: p-type MOSFETs device

754 Optimization of HALO Structure Effects in 45nm p-type MOSFETs Device Using Taguchi Method

Authors: F. Salehuddin, I. Ahmad, F. A. Hamid, A. Zaharim, H. A. Elgomati, B. Y. Majlis, P. R. Apte

Abstract:

In this study, the Taguchi method was used to optimize the effect of HALO structure or halo implant variations on threshold voltage (VTH) and leakage current (ILeak) in 45nm p-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) device. Besides halo implant dose, the other process parameters which used were Source/Drain (S/D) implant dose, oxide growth temperature and silicide anneal temperature. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, the most effective process parameters with respect to VTH and ILeak are halo implant dose (40%) and S/D implant dose (52%) respectively. Whereas the second ranking factor affecting VTH and ILeak are oxide growth temperature (32%) and halo implant dose (34%) respectively. The results show that after optimizations approaches is -0.157V at ILeak=0.195mA/μm.

Keywords: Optimization, p-type MOSFETs device, HALO Structure, Taguchi Method.

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753 3D Quantum Numerical Simulation of Horizontal Rectangular Dual Metal Gate\Gate All Around MOSFETs

Authors: M. Khaouani, A. Guen-Bouazza, B. Bouazza, Z. Kourdi

Abstract:

The integrity and issues related to electrostatic performance associated with scaling Si MOSFET bulk sub 10nm channel length promotes research in new device architectures such as SOI, double gate and GAA MOSFET. In this paper, we present some novel characteristic of horizontal rectangular gate\gate all around MOSFETs with dual metal of gate we obtained using SILVACO TCAD tools. We will also exhibit some simulation results we obtained relating to the influence of some parameters variation on our structure, that having a direct impact on their threshold voltage and drain current. In addition, our TFET showed reasonable ION/IOFF ratio of (104) and low drain induced barrier lowering (DIBL) of 39 mV/V.

Keywords: GAA, SILVACO, QUANTUM, MOSFETs.

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752 Impact of Process Variations on the Vertical Silicon Nanowire Tunneling FET (TFET)

Authors: Z. X. Chen, T. S. Phua, X. P. Wang, G. -Q. Lo, D. -L. Kwong

Abstract:

This paper presents device simulations on the vertical silicon nanowire tunneling FET (VSiNW TFET). Simulations show that a narrow nanowire and thin gate oxide is required for good performance, which is expected even for conventional MOSFETs. The gate length also needs to be more than the nanowire diameter to prevent short channel effects. An effect more unique to TFET is the need for abrupt source to channel junction, which is shown to improve the performance. The ambipolar effect suppression by reducing drain doping concentration is also explored and shown to have little or no effect on performance.

Keywords: Device simulation, MEDICI, tunneling FET (TFET), vertical silicon nanowire.

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751 A Comparative Study of Electrical Transport Phenomena in Ultrathin vs. Nanoscale SOI MOSFETs Devices

Authors: A. Karsenty, A. Chelly

Abstract:

Ultrathin (UTD) and Nanoscale (NSD) SOI-MOSFET devices, sharing a similar W/L but with a channel thickness of 46nm and 1.6nm respectively, were fabricated using a selective “gate recessed” process on the same silicon wafer. The electrical transport characterization at room temperature has shown a large difference between the two kinds of devices and has been interpreted in terms of a huge unexpected series resistance. Electrical characteristics of the Nanoscale device, taken in the linear region, can be analytically derived from the ultrathin device ones. A comparison of the structure and composition of the layers, using advanced techniques such as Focused Ion Beam (FIB) and High Resolution TEM (HRTEM) coupled with Energy Dispersive X-ray Spectroscopy (EDS), contributes an explanation as to the difference of transport between the devices.

Keywords: Nanoscale Devices, SOI MOSFET, Analytical Model, Electron Transport.

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750 Analytical Modeling of Channel Noise for Gate Material Engineered Surrounded/Cylindrical Gate (SGT/CGT) MOSFET

Authors: Pujarini Ghosh A, Rishu Chaujar B, Subhasis Haldar C, R.S Gupta D, Mridula Gupta E

Abstract:

In this paper, an analytical modeling is presentated to describe the channel noise in GME SGT/CGT MOSFET, based on explicit functions of MOSFETs geometry and biasing conditions for all channel length down to deep submicron and is verified with the experimental data. Results shows the impact of various parameters such as gate bias, drain bias, channel length ,device diameter and gate material work function difference on drain current noise spectral density of the device reflecting its applicability for circuit design applications.

Keywords: Cylindrical/Surrounded gate (SGT/CGT) MOSFET, Gate Material Engineering (GME), Spectral Noise and short channeleffect (SCE).

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749 Investigation of Multiple Material Gate Impact on Short Channel Effects and Reliability of Nanoscale SOI MOSFETs

Authors: Paniz Tafakori, Ali A. Orouji

Abstract:

In this paper the features of multiple material gate silicon-on-insulator MOSFETs are presented and compared with single material gate silicon-on-insulator MOSFET structures. The results indicate that the multiple material gate structures reduce short channel effects such as drain induce barrier lowering, hot electron effect and better current characteristics in comparison with single material structures

Keywords: Short-channel effects (SCEs), Dual material gate (DMG), Triple material gate (TMG), Pentamerous material gate (PMG).

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748 Low Voltage Squarer Using Floating Gate MOSFETs

Authors: Rishikesh Pandey, Maneesha Gupta

Abstract:

A new low-voltage floating gate MOSFET (FGMOS) based squarer using square law characteristic of the FGMOS is proposed in this paper. The major advantages of the squarer are simplicity, rail-to-rail input dynamic range, low total harmonic distortion, and low power consumption. The proposed circuit is biased without body effect. The circuit is designed and simulated using SPICE in 0.25μm CMOS technology. The squarer is operated at the supply voltages of ±0.75V . The total harmonic distortion (THD) for the input signal 0.75Vpp at 25 KHz, and maximum power consumption were found to be less than 1% and 319μW respectively.

Keywords: Analog signal processing, floating gate MOSFETs, low-voltage, Spice, squarer.

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747 The Experience with SiC MOSFET and Buck Converter Snubber Design

Authors: P. Vaculik

Abstract:

The newest semiconductor devices on the market are MOSFET transistors based on the silicon carbide – SiC. This material has exclusive features thanks to which it becomes a better switch than Si – silicon semiconductor switch. There are some special features that need to be understood to enable the device’s use to its full potential. The advantages and differences of SiC MOSFETs in comparison with Si IGBT transistors have been described in first part of this article. Second part describes driver for SiC MOSFET transistor and last part of article represents SiC MOSFET in the application of buck converter (step-down) and design of simple RC snubber. 

Keywords: SiC, Si, MOSFET, IGBT, SBD, RC snubber.

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746 Improving the LDMOS Temperature Compensation Bias Circuit to Optimize Back-Off

Authors: Antonis Constantinides, Christos Yiallouras, Christakis Damianou

Abstract:

The application of today's semiconductor transistors in high power UHF DVB-T linear amplifiers has evolved significantly by utilizing LDMOS technology. This fact provides engineers with the option to design a single transistor signal amplifier which enables output power and linearity that was unobtainable previously using bipolar junction transistors or later type first generation MOSFETS. The quiescent current stability in terms of thermal variations of the LDMOS guarantees a robust operation in any topology of DVB-T signal amplifiers. Otherwise, progressively uncontrolled heat dissipation enhancement on the LDMOS case can degrade the amplifier’s crucial parameters in regards to the gain, linearity and RF stability, resulting in dysfunctional operation or a total destruction of the unit. This paper presents one more sophisticated approach from the traditional biasing circuits used so far in LDMOS DVB-T amplifiers. It utilizes a microprocessor control technology, providing stability in topologies where IDQ must be perfectly accurate.

Keywords: Amplifier, DVB-T, LDMOS, MOSFETS.

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745 Highly-Efficient Photoreaction Using Microfluidic Device

Authors: Shigenori Togashi, Yukako Asano

Abstract:

We developed an effective microfluidic device for photoreactions with low reflectance and good heat conductance. The performance of this microfluidic device was tested by carrying out a photoreactive synthesis of benzopinacol and acetone from benzophenone and 2-propanol. The yield reached 36% with an irradiation time of 469.2 s and was improved by more than 30% when compared to the values obtained by the batch method. Therefore, the microfluidic device was found to be effective for improving the yields of photoreactions.

Keywords: Microfluidic device, Photoreaction, Benzophenone, Black Aluminum Oxide, Detection, Yield Improvement.

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744 Linear Pocket Profile based Threshold Voltage Model for sub-100 nm n-MOSFET

Authors: Muhibul Haque Bhuyan, Quazi Deen Mohd Khosru

Abstract:

This paper presents a threshold voltage model of pocket implanted sub-100 nm n-MOSFETs incorporating the drain and substrate bias effects using two linear pocket profiles. Two linear equations are used to simulate the pocket profiles along the channel at the surface from the source and drain edges towards the center of the n-MOSFET. Then the effective doping concentration is derived and is used in the threshold voltage equation that is obtained by solving the Poisson-s equation in the depletion region at the surface. Simulated threshold voltages for various gate lengths fit well with the experimental data already published in the literature. The simulated result is compared with the two other pocket profiles used to derive the threshold voltage models of n-MOSFETs. The comparison shows that the linear model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI devices.

Keywords: Linear pocket profile, pocket implantation, nMOSFET, threshold voltage, short channel effect (SCE), reverse short channeleffect (RSCE).

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743 Vertical GAA Silicon Nanowire Transistor with Impact of Temperature on Device Parameters

Authors: N. Shen, Z. X. Chen, K.D. Buddharaju, H. M. Chua, X. Li, N. Singh, G.Q Lo, D.-L. Kwong

Abstract:

In this paper, we present a vertical wire NMOS device fabricated using CMOS compatible processes. The impact of temperature on various device parameters is investigated in view of usual increase in surrounding temperature with device density.

Keywords: Gate-all-around, temperature dependence, silicon nanowire

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742 Replacing MOSFETs with Single Electron Transistors (SET) to Reduce Power Consumption of an Inverter Circuit

Authors: Ahmed Shariful Alam, Abu Hena M. Mustafa Kamal, M. Abdul Rahman, M. Nasmus Sakib Khan Shabbir, Atiqul Islam

Abstract:

According to the rules of quantum mechanics there is a non-vanishing probability of for an electron to tunnel through a thin insulating barrier or a thin capacitor which is not possible according to the laws of classical physics. Tunneling of electron through a thin insulating barrier or tunnel junction is a random event and the magnitude of current flowing due to the tunneling of electron is very low. As the current flowing through a Single Electron Transistor (SET) is the result of electron tunneling through tunnel junctions of its source and drain the supply voltage requirement is also very low. As a result, the power consumption across a Single Electron Transistor is ultra-low in comparison to that of a MOSFET. In this paper simulations have been done with PSPICE for an inverter built with both SETs and MOSFETs. 35mV supply voltage was used for a SET built inverter circuit and the supply voltage used for a CMOS inverter was 3.5V.

Keywords: ITRS, enhancement type MOSFET, island, DC analysis, transient analysis, power consumption, background charge co-tunneling.

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741 Analysis of Gas Disturbance Characteristics in Lunar Sample Storage

Authors: Lv Shizeng, Han Xiao, Zhang Yi, Ding Wenjing

Abstract:

The lunar sample storage device is mainly used for the preparation of the lunar samples, observation, physical analysis and other work. The lunar samples and operating equipment are placed directly inside the storage device. The inside of the storage device is a high purity nitrogen environment to ensure that the sample is not contaminated by the Earth's environment. In order to ensure that the water and oxygen indicators in the storage device meet the sample requirements, a dynamic gas cycle is required between the storage device and the external purification equipment. However, the internal gas disturbance in the storage device can affect the operation of the sample. In this paper, the storage device model is established, and the tetrahedral mesh is established by Tetra/Mixed method. The influence of different inlet position and gas flow on the internal flow field disturbance is calculated, and the disturbed flow area should be avoided during the sampling operation.

Keywords: Lunar samples, gas disturbance, storage device, characteristic analysis.

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740 Nepros- An Innovated Crystal Necklace

Authors: Amir A. N, Fadzilan A. M, Baskaran G.

Abstract:

In this paper, we proposed an invention of an accessory into a communication device that will help humans to be connected universally. Generally, this device will be made up of crystal and will combine many technologies that will enable the user to run various applications and software anywhere and everywhere. Bringing up the concept of from being user friendly, we had used the crystal as the main material of the device that will trap the surrounding lights to produce projection of its screen. This leads to a lesser energy consumption and allows smaller sized battery to be used, making the device less bulky. Additionally, we proposed the usage of micro batteries as our energy source. Thus, researches regarding crystal were made along with explanations in details of specification and function of the technology used in the device. Finally, we had also drawn several views of the invention from different sides to be visualized.

Keywords: Crystal, Communication Technology, Future concept device, Micro batteries.

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739 Implementation of Terrain Rendering on Mobile Device

Authors: S.A.M. Isa, M.S.M. Rahim, M.D. Kasmuni, D. Daman

Abstract:

Recently, there are significant improvements in the capabilities of mobile devices; rendering large terrain is tedious because of the constraint in resources of mobile devices. This paper focuses on the implementation of terrain rendering on mobile device to observe some issues and current constraints occurred. Experiments are performed using two datasets with results based on rendering speed and appearance to ascertain both the issues and constraints. The result shows a downfall of frame rate performance because of the increase of triangles. Since the resolution between computer and mobile device is different, the terrain surface on mobile device looks more unrealistic compared to on a computer. Thus, more attention in the development of terrain rendering on mobile devices is required. The problems highlighted in this paper will be the focus of future research and will be a great importance for 3D visualization on mobile device.

Keywords: Mobile Device, Mobile Rendering, OpenGL ES, Terrain Rendering.

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738 Electrical Characteristics of SCR - based ESD Device for I/O and Power Rail Clamp in 0.35um Process

Authors: Yong Seo Koo, Dong Su Kim, Byung Seok Lee, Won Suk Park, Bo Bea Song

Abstract:

This paper presents a SCR-based ESD protection devices for I/O clamp and power rail clamp, respectably. These devices have a low trigger voltage and high holding voltage characteristics than conventional SCR device. These devices are fabricated by using 0.35um BCD (Bipolar-CMOS-DMOS) processes. These devices were validated using a TLP system. From the experimental results, the device for I/O ESD clamp has a trigger voltage of 5.8V. Also, the device for power rail ESD clamp has a holding voltage of 7.7V.

Keywords: ESD (Electro-Static Discharge), ESD protection device, SCR (Silicon Controlled Rectifier), Latch-up

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737 Designing and Analyzing Sensor and Actuator of a Nano/Micro-System for Fatigue and Fracture Characterization of Nanomaterials

Authors: Mohammad Reza Zamani Kouhpanji

Abstract:

This paper presents a MEMS/NEMS device for fatigue and fracture characterization of nanomaterials. This device can apply static loads, cyclic loads, and their combinations in nanomechanical experiments. It is based on the electromagnetic force induced between paired parallel wires carrying electrical currents. Using this concept, the actuator and sensor parts of the device were designed and analyzed while considering the practical limitations. Since the PWCC device only uses two wires for actuation part and sensing part, its fabrication process is extremely easier than the available MEMS/NEMS devices. The total gain and phase shift of the MEMS/NEMS device were calculated and investigated. Furthermore, the maximum gain and sensitivity of the MEMS/NEMS device were studied to demonstrate the capability and usability of the device for wide range of nanomaterials samples. This device can be readily integrated into SEM/TEM instruments to provide real time study of the mechanical behaviors of nanomaterials as well as their fatigue and fracture properties, softening or hardening behaviors, and initiation and propagation of nanocracks.

Keywords: Sensors and actuators, MEMS/NEMS devices, fatigue and fracture nanomechanical testing device, static and cyclic nanomechanical testing device.

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736 Functional Sample of the Portable Device for Fast Analysis of Explosives

Authors: A. Bumbová, J. Kellner, Z. Večeřa, V. Kahle, J. Navrátil

Abstract:

The construction of original functional sample of the portable device for fast analysis of energetic materials has been described in the paper. The portable device consisting of two parts – an original miniaturized microcolumn liquid chromatograph and a unique chemiluminescence detector – has been proposed and realized. In a very short time, this portable device is capable of identifying selectively most of military nitramine- and nitroesterbased explosives as well as inorganic nitrates occurring in trace concentrations in water or in soil. The total time required for the identification of extracts is shorter than 8 minutes.

Keywords: Chemiluminescence, microcolumn liquid chromatograph, nitramines, nitroesters, portable device.

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735 A Novel Portable Device for Fast Analysis of Energetic Materials in the Environment

Authors: Jozef Šesták, Zbyněk Večeřa, Vladislav Kahle, Dana Moravcová, Pavel Mikuška, Josef Kellner, František Božek

Abstract:

Construction of portable device for fast analysis of energetic materials is described in this paper. The developed analytical system consists of two main parts: a miniaturized microcolumn liquid chromatograph of unique construction and original chemiluminescence detector. This novel portable device is able to determine selectively most of nitramine- and nitroester-based explosives as well as inorganic nitrates at trace concentrations in water or soil extracts in less than 8 minutes.

Keywords: Portable device, uLC, chemiluminescence, nitramines, nitroesters.

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734 Behavioral Study of TCSC Device – A MATLAB/Simulink Implementation

Authors: S. Meikandasivam, Rajesh Kumar Nema, Shailendra Kumar Jain

Abstract:

A basic conceptual study of TCSC device on Simulink is a teaching aid and helps in understanding the rudiments of the topic. This paper thus stems out from basics of TCSC device and analyzes the impedance characteristics and associated single & multi resonance conditions. The Impedance characteristics curve is drawn for different values of inductance in MATLAB using M-files. The study is also helpful in estimating the appropriate inductance and capacitance values which have influence on multi resonance point in TCSC device. The capacitor voltage, line current, thyristor current and capacitor current waveforms are discussed briefly as simulation results. Simulink model of TCSC device is given and corresponding waveforms are analyzed. The subsidiary topics e.g. power oscillation damping, SSR mitigation and transient stability is also brought out.

Keywords: TCSC device, Impedance characteristics, Resonance point, Simulink model

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733 Simulation Study of Lateral Trench Gate Power MOSFET on 4H-SiC

Authors: Yashvir Singh, Mayank Joshi

Abstract:

A lateral trench-gate power metal-oxide-semiconductor on 4H-SiC is proposed. The device consists of two separate trenches in which two gates are placed on both sides of P-body region resulting two parallel channels. Enhanced current conduction and reduced-surface-field effect in the structure provide substantial improvement in the device performance. Using two dimensional simulations, the performance of proposed device is evaluated and compare of with that of the conventional device for same cell pitch. It is demonstrated that the proposed structure provides two times higher output current, 11% decrease in threshold voltage, 70% improvement in transconductance, 70% reduction in specific ON-resistance, 52% increase in breakdown voltage, and nearly eight time improvement in figure-of-merit over the conventional device.

Keywords: 4H-SiC, lateral, trench-gate, power MOSFET.

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732 GPS Navigator for Blind Walking in a Campus

Authors: Rangsipan Marukatat, Pongmanat Manaspaibool, Benjawan Khaiprapay, Pornpimon Plienjai

Abstract:

We developed a GPS-based navigation device for the blind, with audio guidance in Thai language. The device is composed of simple and inexpensive hardware components. Its user interface is quite simple. It determines optimal routes to various landmarks in our university campus by using heuristic search for the next waypoints. We tested the device and made note of its limitations and possible extensions.

Keywords: Blind, global positioning system (GPS), navigation

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731 Bluetooth Piconet System for Child Care Applications

Authors: Ching-Sung Wang, Teng-Wei Wang, Zhen-Ting Zheng

Abstract:

This study mainly concerns a safety device designed for child care. When children are out of sight or the caregivers cannot always pay attention to the situation, through the functions of this device, caregivers can immediately be informed to make sure that the children do not get lost or hurt, and thus, ensure their safety. Starting from this concept, a device is produced based on the relatively low-cost Bluetooth piconet system and a three-axis gyroscope sensor. This device can transmit data to a mobile phone app through Bluetooth, in order that the user can learn the situation at any time. By simply clipping the device in a pocket or on the waist, after switching on/starting the device, it will send data to the phone to detect the child’s fall and distance. Once the child is beyond the angle or distance set by the app, it will issue a warning to inform the phone owner.

Keywords: Children care, piconet system, three-axis gyroscope, distance detection, falls detection.

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730 Transient Analysis & Performance Estimation of Gate Inside Junctionless Transistor (GI-JLT)

Authors: Sangeeta Singh, Pankaj Kumar, P. N. Kondekar

Abstract:

In this paper, the transient device performance analysis of n-type Gate Inside JunctionLess Transistor (GI-JLT) has been evaluated. 3-D Bohm Quantum Potential (BQP) transport device simulation has been used to evaluate the delay and power dissipation performance. GI-JLT has a number of desirable device parameters such as reduced propagation delay, dynamic power dissipation, power and delay product, intrinsic gate delay and energy delay product as compared to Gate-all-around transistors GAA-JLT. In addition to this, various other device performance parameters namely, on/off current ratio, short channel effects (SCE), transconductance Generation Factor (TGF) and unity gain cut-off frequency (fT ) and subthreshold slope (SS) of the GI-JLT and GAA-JLT have been analyzed and compared. GI-JLT shows better device performance characteristics than GAA-JLT for low power and high frequency applications, because of its larger gate electrostatic control on the device operation.

Keywords: Gate-inside junctionless transistor GI-JLT, Gate-all-around junctionless transistor GAA-JLT, propagation delay, power delay product.

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729 Saturated Gain of Doped Multilayer Quantum Dot Semiconductor Optical Amplifiers

Authors: Omar Qasaimeh

Abstract:

The effect of the number of quantum dot (QD) layers on the saturated gain of doped QD semiconductor optical amplifiers (SOAs) has been studied using multi-population coupled rate equations. The developed model takes into account the effect of carrier coupling between adjacent layers. It has been found that increasing the number of QD layers (K) increases the unsaturated optical gain for K<8 and approximately has no effect on the unsaturated gain for K ≥ 8. Our analysis shows that the optimum ptype concentration that maximizes the unsaturated optical gain of the ground state is NA Ôëê 0.75 ×1018cm-3 . On the other hand, it has been found that the saturated optical gain for both the ground state and the excited state are strong function of both the doping concentration and K where we find that it is required to dope the dots with n-type concentration for very large K at high photon energy.

Keywords: doping, multilayer, quantum dot optical amplifier, saturated gain.

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728 Design of Novel SCR-based ESD Protection Device for I/O Clamp in BCD Process

Authors: Yong-Seo Koo, Jin-Woo Jung, Byung-Seok Lee, Dong-Su Kim, Yil-Suk Yang

Abstract:

In this paper, a novel LVTSCR-based device for electrostatic discharge (ESD) protection of integrated circuits (ICs) is designed, fabricated and characterized. The proposed device is similar to the conventional LVTSCR but it has an embedded PMOSFET in the anode n-well to enhance the turn on speed, the clamping capability and the robustness. This is possible because the embedded PMOSFET provides the sub-path of ESD discharge current. The TLP, HBM and MM testing are carried out to verify the ESD performance of the proposed devices, which are fabricated in 0.35um (Bipolar-CMOS-DMOS) BCDMOS process. The device has the robustness of 70mA/um that is higher about 60mA/um than the LVTSCR, approximately.

Keywords: ESD Protection, grounded gate NMOS (GGNMOS), low trigger voltage SCR (LVTSCR)

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727 Photoplethysmography-Based Device Designing for Cardiovascular System Diagnostics

Authors: S. Botman, D. Borchevkin, V. Petrov, E. Bogdanov, M. Patrushev, N. Shusharina

Abstract:

In this paper, we report the development of the device for diagnostics of cardiovascular system state and associated automated workstation for large-scale medical measurement data collection and analysis. It was shown that optimal design for the monitoring device is wristband as it represents engineering trade-off between accuracy and usability. Monitoring device is based on the infrared reflective photoplethysmographic sensor, which allows collecting multiple physiological parameters, such as heart rate and pulsing wave characteristics. Developed device uses BLE interface for medical and supplementary data transmission to the coupled mobile phone, which processes it and send it to the doctor's automated workstation. Results of this experimental model approbation confirmed the applicability of the proposed approach.

Keywords: Cardiovascular diseases, health monitoring systems, photoplethysmography, pulse wave, remote diagnostics.

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726 A Highly Sensitive Dip Strip for Detection of Phosphate in Water

Authors: Hojat Heidari-Bafroui, Amer Charbaji, Constantine Anagnostopoulos, Mohammad Faghri

Abstract:

Phosphorus is an essential nutrient for plant life which is most frequently found as phosphate in water. Once phosphate is found in abundance in surface water, a series of adverse effects on an ecosystem can be initiated. Therefore, a portable and reliable method is needed to monitor the phosphate concentrations in the field. In this paper, an inexpensive dip strip device with the ascorbic acid/antimony reagent dried on blotting paper along with wet chemistry is developed for the detection of low concentrations of phosphate in water. Ammonium molybdate and sulfuric acid are separately stored in liquid form so as to improve significantly the lifetime of the device and enhance the reproducibility of the device’s performance. The limit of detection and quantification for the optimized device are 0.134 ppm and 0.472 ppm for phosphate in water, respectively. The device’s shelf life, storage conditions, and limit of detection are superior to what has been previously reported for the paper-based phosphate detection devices.

Keywords: Phosphate detection, paper-based device, molybdenum blue method, colorimetric assay.

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725 Effect of Field Dielectric Material on Performance of InGaAs Power LDMOSFET

Authors: Yashvir Singh, Swati Chamoli

Abstract:

In this paper, a power laterally-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) on In0.53Ga0.47As is presented. The device utilizes a thicker field-oxide with low dielectric constant under the field-plate in order to achieve possible reduction in device capacitances and reduced-surface-field effect. Using 2D numerical simulations, performance of the proposed device is analyzed and compared with that of the conventional LDMOSFET. The proposed structure provides 50% increase in the breakdown voltage, 21% increase in transit frequency, and 72% improvement in figure-of-merit over the conventional device for same cell pitch.

Keywords: InGaAs, dielectric, lateral, power MOSFET.

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