Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 16

Search results for: VCO

16 On-Chip Aging Sensor Circuit Based on Phase Locked Loop Circuit

Authors: Ararat Khachatryan, Davit Mirzoyan

Abstract:

In sub micrometer technology, the aging phenomenon starts to have a significant impact on the reliability of integrated circuits by bringing performance degradation. For that reason, it is important to have a capability to evaluate the aging effects accurately. This paper presents an accurate aging measurement approach based on phase-locked loop (PLL) and voltage-controlled oscillator (VCO) circuit. The architecture is rejecting the circuit self-aging effect from the characteristics of PLL, which is generating the frequency without any aging phenomena affects. The aging monitor is implemented in low power 32 nm CMOS technology, and occupies a pretty small area. Aging simulation results show that the proposed aging measurement circuit improves accuracy by about 2.8% at high temperature and 19.6% at high voltage.

Keywords: Aging, Nanoscale, HCI, effect, NBTI

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15 A Trends Analysis of Dinghy Yacht Simulator

Authors: Jae-Neung Lee, Sung-Bum Pan, Keun-Chang Kwak

Abstract:

This paper describes an analysis of Yacht Simulator international trends and also explains about Yacht. The results are summarized as follows. Attached to the cockpit are sensors that feed -back information on rudder angle, boat heel angle and mainsheet tension to the computer. Energy expenditure of the sailor measure indirectly using expired gas analysis for the measurement of VO2 and VCO2. At sea course configurations and wind conditions can be preset to suit any level of sailor from complete beginner to advanced sailor.

Keywords: Sailing, yacht simulator, trends analysis

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14 A CFD Analysis of Flow through a High-Pressure Natural Gas Pipeline with an Undeformed and Deformed Orifice Plate

Authors: R. Kiš, M. Malcho, M. Janovcová

Abstract:

This work aims to present a numerical analysis of the natural gas which flows through a high-pressure pipeline and an orifice plate, through the use of CFD methods. The paper contains CFD calculations for the flow of natural gas in a pipe with different geometry used for the orifice plates. One of them has a standard geometry and a shape without any deformation and the other is deformed by the action of the pressure differential. It shows the behavior of natural gas in a pipeline using the velocity profiles and pressure fields of the gas in both models with their differences. The entire research is based on the elimination of any inaccuracy which should appear in the flow of the natural gas measured in the high-pressure pipelines of the gas industry and which is currently not given in the relevant standard.

Keywords: Natural Gas, orifice plate, high-pressure pipeline, CFD analysis

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13 A Few Descriptive and Optimization Issues on the Material Flow at a Research-Academic Institution: The Role of Simulation

Authors: D. R. Delgado Sobrino, P. Košťál, J. Oravcová

Abstract:

Lately, significant work in the area of Intelligent Manufacturing has become public and mainly applied within the frame of industrial purposes. Special efforts have been made in the implementation of new technologies, management and control systems, among many others which have all evolved the field. Aware of all this and due to the scope of new projects and the need of turning the existing flexible ideas into more autonomous and intelligent ones, i.e.: Intelligent Manufacturing, the present paper emerges with the main aim of contributing to the design and analysis of the material flow in either systems, cells or work stations under this new “intelligent" denomination. For this, besides offering a conceptual basis in some of the key points to be taken into account and some general principles to consider in the design and analysis of the material flow, also some tips on how to define other possible alternative material flow scenarios and a classification of the states a system, cell or workstation are offered as well. All this is done with the intentions of relating it with the use of simulation tools, for which these have been briefly addressed with a special focus on the Witness simulation package. For a better comprehension, the previous elements are supported by a detailed layout, other figures and a few expressions which could help obtaining necessary data. Such data and others will be used in the future, when simulating the scenarios in the search of the best material flow configurations.

Keywords: Flexible/Intelligent Manufacturing System/Cell (F/IMS/C), material flow/design/configuration (MF/D/C), workstation

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12 20 GHz Fractional Phased Locked Loop Circuit for the Gbps Wireless Communication

Authors: Ki-Jin Kim, Sanghoon Park, K. H. Ahn

Abstract:

This paper presents the 20-GHz fractional PLL (Phase Locked Loop) circuit for the next generation Wi-Fi by using 90 nm TSMC process. The newly suggested millimeter wave 16/17 pre-scalar is designed and verified by measurement to make the fractional PLL having a low quantization noise. The operational bandwidth of the 60 GHz system is 15 % of the carrier frequency which requires large value of Kv (VCO control gain) resulting in degradation of phase noise. To solve this problem, this paper adopts AFC (Automatic Frequency Controller) controlled 4-bit millimeter wave VCO with small value of Kv. Also constant Kv is implemented using 4-bit varactor bank. The measured operational bandwidth is 18.2 ~ 23.2 GHz which is 25 % of the carrier frequency. The phase noise of -58 and -96.2 dBc/Hz at 100 KHz and 1 MHz offset is measured respectively. The total power consumption of the PLL is only 30 mW.

Keywords: Millimeter Wave Fractional PLL, Wide band VCO, WPAN Transceiver

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11 A Novel Portable Device for Fast Analysis of Energetic Materials in the Environment

Authors: Jozef Šesták, Zbyněk Večeřa, Vladislav Kahle, Dana Moravcová, Pavel Mikuška, Josef Kellner, František Božek

Abstract:

Construction of portable device for fast analysis of energetic materials is described in this paper. The developed analytical system consists of two main parts: a miniaturized microcolumn liquid chromatograph of unique construction and original chemiluminescence detector. This novel portable device is able to determine selectively most of nitramine- and nitroester-based explosives as well as inorganic nitrates at trace concentrations in water or soil extracts in less than 8 minutes.

Keywords: Chemiluminescence, Nitramines, portable device, uLC, nitroesters

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10 Design of High Gain, High Bandwidth Op-Amp for Reduction of Mismatch Currents in Charge Pump PLL in 180 nm CMOS Technology

Authors: R .H. Talwekar, S. S Limaye

Abstract:

The designing of charge pump with high gain Op- Amp is a challenging task for getting faithful response .Design of high performance phase locked loop require ,a design of high performance charge pump .We have designed a operational amplifier for reducing the error caused by high speed glitch in a transistor and mismatch currents . A separate Op-Amp has designed in 180 nm CMOS technology by CADENCE VIRTUOSO tool. This paper describes the design of high performance charge pump for GHz CMOS PLL targeting orthogonal frequency division multiplexing (OFDM) application. A high speed low power consumption Op-Amp with more than 500 MHz bandwidth has designed for increasing the speed of charge pump in Phase locked loop.

Keywords: phase locked loop (PLL), Charge pump (CP) Orthogonal frequency divisionmultiplexing (OFDM), Phase frequencydetector (PFD), Voltage controlled oscillator (VCO)

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9 A Programmable FSK-Modulator in 350nm CMOS Technology

Authors: Nasir Mehmood, Saad Rahman, Vinodh Ravinath, Mahesh Balaji

Abstract:

This paper describes the design of a programmable FSK-modulator based on VCO and its implementation in 0.35m CMOS process. The circuit is used to transmit digital data at 100Kbps rate in the frequency range of 400-600MHz. The design and operation of the modulator is discussed briefly. Further the characteristics of PLL, frequency synthesizer, VCO and the whole design are elaborated. The variation among the proposed and tested specifications is presented. Finally, the layout of sub-modules, pin configurations, final chip and test results are presented.

Keywords: CMOS, VCO, phase locked loop, FSK Modulator, Frequency Synthesizer

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8 Temperature Effect on the Organic Solar Cells Parameters

Authors: F.Belhocine-Nemmar; MS.Belkaid D. Hatem, O Boughias

Abstract:

In this work, the influence of temperature on the different parameters of solar cells based on organic semiconductors are studied. The short circuit current Isc increases so monotonous with temperature and then saturates to a maximum value before decreasing at high temperatures. The open circuit voltage Vco decreases linearly with temperature. The fill factor FF and efficiency, which are directly related with Isc and Vco follow the variations of the letters. The phenomena are explained by the behaviour of the mobility which is a temperature activated process.

Keywords: temperature effect, Organic Materials, Solar Cells, cells parameters

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7 A SAW-less Dual-Band CDMA Diversity and Simultaneous-GPS Zero-IF Receiver

Authors: Bassem Fahs, Philippe Barré, Patrick Ozenne, Eric Chartier, Guillaume Hérault, Sébastien Jacquet, Sébastien Clamagirand

Abstract:

We present a dual-band (Cellular & PCS) dual-path zero-IF receiver for CDMA2000 diversity, monitoring and simultaneous-GPS. The secondary path is a SAW-less diversity CDMA receiver which can be also used for advanced features like monitoring when supported with an additional external VCO. A GPS receiver is integrated with its dedicated VCO allowing simultaneous positioning during a cellular call. The circuit is implemented in a 0.25μm 40GHz-fT BiCMOS process and uses a HVQFN 56-pin package. It consumes a maximum 300mW from a 2.8V supply in dual-modes. The chip area is 12.8mm2.

Keywords: Diversity, CDMA, GPS, zero-IF, SAW-less

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6 A Direct Down-conversion Receiver for Low-power Wireless Sensor Networks

Authors: Gianluca Cornetta, Abdellah Touhafi, David J. Santos, Jose Manuel Vazquez

Abstract:

A direct downconversion receiver implemented in 0.13 μm 1P8M process is presented. The circuit is formed by a single-end LNA, an active balun for conversion into balanced mode, a quadrature double-balanced passive switch mixer and a quadrature voltage-controlled oscillator. The receiver operates in the 2.4 GHz ISM band and complies with IEEE 802.15.4 (ZigBee) specifications. The circuit exhibits a very low noise figure of only 2.27 dB and dissipates only 14.6 mW with a 1.2 V supply voltage and is hence suitable for low-power applications.

Keywords: VCO, LNA, Active Balun, Passive Mixer, IEEE 802.15.4(ZigBee)

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5 130 nm CMOS Mixer and VCO for 2.4 GHz Low-power Wireless Personal Area Networks

Authors: Gianluca Cornetta, David J. Santos

Abstract:

This paper describes a 2.4 GHz passive switch mixer and a 5/2.5 GHz voltage-controlled negative Gm oscillator (VCO) with an inversion-mode MOS varactor. Both circuits are implemented using a 1P8M 0.13 μm process. The switch mixer has an input referred 1 dB compression point of -3.89 dBm and a conversion gain of -0.96 dB when the local oscillator power is +2.5 dBm. The VCO consumes only 1.75 mW, while drawing 1.45 mA from a 1.2 V supply voltage. In order to reduce the passives size, the VCO natural oscillation frequency is 5 GHz. A clocked CMOS divideby- two circuit is used for frequency division and quadrature phase generation. The VCO has a -109 dBc/Hz phase noise at 1 MHz frequency offset and a 2.35-2.5 GHz tuning range (after the frequency division), thus complying with ZigBee requirements.

Keywords: Wireless Sensor Networks, IEEE 802.15.4 (ZigBee), Switch Mixers, Varactors, Direct Conversion Receiver

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4 Low Jitter ADPLL based Clock Generator for High Speed SoC Applications

Authors: Moorthi S., Meganathan D., Janarthanan D., Praveen Kumar P., J. Raja paul perinbam

Abstract:

An efficient architecture for low jitter All Digital Phase Locked Loop (ADPLL) suitable for high speed SoC applications is presented in this paper. The ADPLL is designed using standard cells and described by Hardware Description Language (HDL). The ADPLL implemented in a 90 nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. The simulation result shows that PLL has cycle to cycle jitter of 164 ps and period jitter of 100 ps at 100MHz. Since the digitally controlled oscillator (DCO) can achieve both high resolution and wide frequency range, it can meet the demands of system-level integration. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for System-on-Chip (SoC) applications.

Keywords: phase locked loop (PLL), All Digital Phase Locked Loop (ADPLL), Systemon-Chip (SoC), Very High speedIntegrated Circuit (VHSIC) Hardware Description Language(VHDL), Digitally Controlled Oscillator (DCO), Phase frequencydetector (PFD) and Voltage Controlled Oscillator (VCO)

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3 3 State Current Mode of a Grid Connected PV Converter

Authors: Attila Balogh, Eszter Varga, István Varjasi

Abstract:

Nowadays in applications of renewable energy sources it is important to develop powerful and energy-saving photovoltaic converters and to keep the prescriptions of the standards. In grid connected PV converters the obvious solution to increase the efficiency is to reduce the switching losses. Our new developed control method reduces the switching losses and keeps the limitations of the harmonic distortion standards. The base idea of the method is the utilization of 3-state control causing discontinuous current mode at low input power. In the following sections the control theory, the realizations and the simulation results are presented.

Keywords: high efficiency, control method, Discontinuous current, PVconverter

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2 Multi Band Frequency Synthesizer Based on ISPD PLL with Adapted LC Tuned VCO

Authors: Bilel Gassara, Mahmoud Abdellaoui, Nouri Masmoud

Abstract:

The 4G front-end transceiver needs a high performance which can be obtained mainly with an optimal architecture and a multi-band Local Oscillator. In this study, we proposed and presented a new architecture of multi-band frequency synthesizer based on an Inverse Sine Phase Detector Phase Locked Loop (ISPD PLL) without any filters and any controlled gain block and associated with adapted multi band LC tuned VCO using a several numeric controlled capacitive branches but not binary weighted. The proposed architecture, based on 0.35μm CMOS process technology, supporting Multi-band GSM/DCS/DECT/ UMTS/WiMax application and gives a good performances: a phase noise @1MHz -127dBc and a Factor Of Merit (FOM) @ 1MHz - 186dB and a wide band frequency range (from 0.83GHz to 3.5GHz), that make the proposed architecture amenable for monolithic integration and 4G multi-band application.

Keywords: Wireless, multi-band, GSM/DCS/DECT/UMTS/WiMax, ISPD PLL, keep and capture range, Synthesizer

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1 A 3.125Gb/s Clock and Data Recovery Circuit Using 1/4-Rate Technique

Authors: Il-Do Jeong, Hang-Geun Jeong

Abstract:

This paper describes the design and fabrication of a clock and data recovery circuit (CDR). We propose a new clock and data recovery which is based on a 1/4-rate frequency detector (QRFD). The proposed frequency detector helps reduce the VCO frequency and is thus advantageous for high speed application. The proposed frequency detector can achieve low jitter operation and extend the pull-in range without using the reference clock. The proposed CDR was implemented using a 1/4-rate bang-bang type phase detector (PD) and a ring voltage controlled oscillator (VCO). The CDR circuit has been fabricated in a standard 0.18 CMOS technology. It occupies an active area of 1 x 1 and consumes 90 mW from a single 1.8V supply.

Keywords: Clock and data recovery

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