Search results for: Sampling clock generator

Authors: Se-Jin Ko, Deok-Min Kim, Seok-Yoon Kim

Abstract:

The trend of growing density on chips has increases not only the temperature in chips but also the gradient of the temperature depending on locations. In this paper, we propose the balanced skew tree generation technique for minimizing the clock skew that is affected by the temperature gradients on chips. We calculate the interconnect delay using Elmore delay equation, and find out the optimal balanced clock tree by modifying the clock trees generated through the Deferred Merge Embedding(DME) algorithm. The experimental results show that the distance variance of clock insertion points with and without considering the temperature gradient can be lowered below 54% and we confirm that the skew is remarkably decreased after applying the proposed technique.

Keywords: clock, clock-skew, temperature, thermal.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1681

Authors: Aakash Subramanian, Vansh Pal Singh Makh, Abhijit Mitra

Abstract:

A new digital transceiver circuit for asynchronous frame detection is proposed where both the transmitter and receiver contain all digital components, thereby avoiding possible use of conventional devices like monostable multivibrators with unstable external components such as resistances and capacitances. The proposed receiver circuit, in particular, uses a combinational logic block yielding an output which changes its state as soon as the start bit of a new frame is detected. This, in turn, helps in generating an efficient receiver sampling clock. A data latching circuit is also used in the receiver to latch the recovered data bits in any new frame. The proposed receiver structure is also extended from 4- bit information to any general n data bits within a frame with a common expression for the output of the combinational logic block. Performance of the proposed hardware design is evaluated in terms of time delay, reliability and robustness in comparison with the standard schemes using monostable multivibrators. It is observed from hardware implementation that the proposed circuit achieves almost 33 percent speed up over any conventional circuit.

Keywords: Asynchronous Communication, Digital Detector, Combinational logic output, Sampling clock generator, Hardwareimplementation.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2158

Authors: R. Manjith, C. Muthukumari

Abstract:

In this paper, a novel Linear Feedback Shift Register (LFSR) with Look Ahead Clock Gating (LACG) technique is presented to reduce the power consumption in modern processors and System-on-Chip. Clock gating is a predominant technique used to reduce unwanted switching of clock signals. Several clock gating techniques to reduce the dynamic power have been developed, of which LACG is predominant. LACG computes the clock enabling signals of each flip-flop (FF) one cycle ahead of time, based on the present cycle data of the flip-flops on which it depends. It overcomes the timing problems in the existing clock gating methods like datadriven clock gating and Auto-Gated flip-flops (AGFF) by allotting a full clock cycle for the determination of the clock enabling signals. Further to reduce the power consumption in LACG technique, FFs can be grouped so that they share a common clock enabling signal. Simulation results show that the novel grouped LFSR with LACG achieves 15.03% power savings than conventional LFSR with LACG and 44.87% than data-driven clock gating.

Keywords: AGFF, data-driven, LACG, LFSR.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1693

Authors: Il-Do Jeong, Hang-Geun Jeong

Abstract:

This paper describes the design and fabrication of a clock and data recovery circuit (CDR). We propose a new clock and data recovery which is based on a 1/4-rate frequency detector (QRFD). The proposed frequency detector helps reduce the VCO frequency and is thus advantageous for high speed application. The proposed frequency detector can achieve low jitter operation and extend the pull-in range without using the reference clock. The proposed CDR was implemented using a 1/4-rate bang-bang type phase detector (PD) and a ring voltage controlled oscillator (VCO). The CDR circuit has been fabricated in a standard 0.18 CMOS technology. It occupies an active area of 1 x 1 and consumes 90 mW from a single 1.8V supply.

Keywords: Clock and data recovery, 1/4-rate frequency detector, 1/4-rate phase detector.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2870

Authors: Semih Demir, Anil Celebi

Abstract:

Circuit switched networks widely used until the end of the 20^th century have been transformed into packages switched networks. Time Division Multiplexing over Internet Protocol (TDMoIP) is a system that enables Time Division Multiplexing (TDM) traffic to be carried over packet switched networks (PSN). In TDMoIP systems, devices that send TDM data to the PSN and receive it from the network must operate with the same clock frequency. In this study, it was aimed to implement clock synchronization process in Field Programmable Gate Array (FPGA) chips using time information attached to the packages received from PSN. The designed hardware is verified using the datasets obtained for the different carrier types and comparing the results with the software model. Field tests are also performed by using the real time TDMoIP system.

Keywords: Clock recovery on TDMoIP, FPGA, MATLAB reference model, clock synchronization.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1382

Authors: Jianping Hu, Xiaolei Sheng

Abstract:

This paper introduces an adiabatic register file based on two-phase CPAL (Complementary Pass-Transistor Adiabatic Logic circuits) with power-gating scheme, which can operate on a single-phase power clock. A 32×32 single-phase adiabatic register file with power-gating scheme has been implemented with TSMC 0.18μm CMOS technology. All the circuits except for the storage cells employ two-phase CPAL circuits, and the storage cell is based on the conventional memory one. The two-phase non-overlap power-clock generator with power-gating scheme is used to supply the proposed adiabatic register file. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. Compared with the traditional static CMOS register file, HSPICE simulations show that the proposed adiabatic register file can work very well, and it attains about 73% energy savings at 100 MHz.

Keywords: Low power, Register file, Complementarypass-transistor logic, Adiabatic logic, Single-phase power clock.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1910

Authors: M. J. Park, S. H. Lee, C. H. Lee, O. M. Kwon

Abstract:

This paper studies a secondary voltage control framework of the microgrids based on the consensus for a communication network of multiagent. The proposed control is designed by the communication network with one-way links. The communication network is modeled by a directed graph. At this time, the concept of sampling is considered as the communication constraint among each distributed generator in the microgrids. To analyze the sampling effects on the secondary voltage control of the microgrids, by using Lyapunov theory and some mathematical techniques, the sufficient condition for such problem will be established regarding linear matrix inequality (LMI). Finally, some simulation results are given to illustrate the necessity of the consideration of the sampling effects on the secondary voltage control of the microgrids.

Keywords: Microgrids, secondary control, multiagent, sampling, LMI.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1412

Authors: Chakkapong Supasri, Tanongkiat Kiatsiriroat, Atipoang Nuntaphan

Abstract:

 

This research studied the influence of delta wing and delta winglet vortex generators on air flow characteristic. Normally, the vortex generator has been used for enhancing the heat transfer performance by promote the helical flow of air stream. The vortex generator was setup in the wind tunnel and the flow pattern of air stream passing the vortex generator was observed by using smoke generator. The Reynolds number of air stream was between 30,000 and 80,000. It is found that the delta winglet having 20mm fin height and 30 degree of air stream contact angle generates the maximum helical flow of air stream.

Keywords: Vortex generator, Flow behavior, Visual study, Delta wing, Delta winglet, Smoke generator.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2179

Authors: Agata M. Kołodziejczyk, Mateusz Harasymczuk, Pierre-Yves Girardin, Lucie Davidová

Abstract:

Subjective time perception implies connection to cognitive functions, attention, memory and awareness, but a little is known about connections with homeostatic states of the body coordinated by circadian clock. In this paper, we present results from experimental study of subjective time perception in volunteers performing physical activity on treadmill in various phases of their circadian rhythms. Subjects were exposed to several time illusions simulated by programmed timing systems. This study brings better understanding for further improvement of of work quality in isolated areas. 

Keywords: Biological clock, light, time illusions, treadmill.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1472

Authors: Ahmed Elsebaay, Maged A. Abu Adma, Mahmoud Ramadan

Abstract:

This study presents a technique clarifying the effect of ambient air temperature and loads power factor changing from standard values on electric generator power rating. The study introduces an optimized technique for selecting the correct electric generator power rating for certain application and operating site ambient temperature. The de-rating factors due to the previous effects will be calculated to be applied on a generator to select its power rating accurately to avoid unsafe operation and save its lifetime. The information in this paper provides a simple, accurate, and general method for synchronous generator selection and eliminates common errors.

Keywords: Ambient temperature, de-rating factor, electric generator, power factor.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 3814

Authors: Chang-Hung Hsu, Chun-Yao Lee, Guan-Lin Liao, Yung-Tsan Jou, Jin-Maun Ho, Yu-Hua Hsieh, Yi-Xing Shen

Abstract:

This article simulates the wind generator set which has two fault bearing collar rail destruction and the gear box oil leak fault. The electric current signal which produced by the generator, We use Empirical Mode Decomposition (EMD) as well as Fast Fourier Transform (FFT) obtains the frequency range-s signal figure and characteristic value. The last step is use a kind of Artificial Neural Network (ANN) classifies which determination fault signal's type and reason. The ANN purpose of the automatic identification wind generator set fault..

Keywords: Wind-driven generator, Fast Fourier Transform, Neural network

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1710

Authors: Abdelghani Dendouga, Nour-Eddine Bouguechal, Souhil Kouda, Samir Barra

Abstract:

A behavioral model of a second order switchedcapacitor Sigma-Delta modulator is presented. The purpose of this work is the presentation of a behavioral model of a second order switched capacitor ΣΔ modulator considering (Error due to Clock Jitter, Thermal noise Amplifier Noise, Amplifier Slew-Rate, Non linearity of amplifiers, Gain error, Charge Injection, Clock Feedthrough, and Nonlinear on-resistance). A comparison between the use of MOS switches and the use transmission gate switches use is analyzed.

Keywords: Charge injection, clock feed through, Sigma Deltamodulators, Sigma Delta non-idealities, switched capacitor.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2960

Authors: Poopak Roshanfekr, Torbjörn Thiringer, Sonja Lundmark, Mikael Alatalo

Abstract:

This article presents a performance comparison of an interior mounted permanent magnet synchronous generator (IPMSG) with a synchronous reluctance generator (SynRG) with the same size for a wind application. It is found that using the same geometrical dimensions, a SynRG can convert 74 % of the power that an IPMSG can convert, while it has 80% of the IPMSG weight. Moreover it is found that the efficieny for the IMPSG is 99% at rated power compared to 98.7% for the SynRG.

Keywords: Interior mounted permanent magnet synchronous generator (IPMSG), synchronous reluctance generator (SynRG), wind energy, annual energy efficiency.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2429

Authors: Chathurika D. Abeyrathne, Malka N. Halgamuge, Peter M. Farrell

Abstract:

There is an ongoing controversy in the literature related to the biological effects of weak, low frequency electromagnetic fields. The physical arguments and interpretation of the experimental evidence are inconsistent, where some physical arguments and experimental demonstrations tend to reject the likelihood of any effect of the fields at extremely low level. The problem arises of explaining, how the low-energy influences of weak magnetic fields can compete with the thermal and electrical noise of cells at normal temperature using the theoretical studies. The magnetoreception in animals involve radical pair mechanism. The same mechanism has been shown to be involved in the circadian rhythm synchronization in mammals. These reactions can be influenced by the weak magnetic fields. Hence, it is postulated the biological clock can be affected by weak magnetic fields and these disruptions to the rhythm can cause adverse biological effects. In this paper, likelihood of altering the biological clock via the radical pair mechanism is analyzed to simplify these studies of controversy.

Keywords: Bio-effect, biological clock, magnetoreception, radical pair mechanism, weak magnetic field.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2278

Authors: Andi Pawawoi, Syafii

Abstract:

Instantaneous electromagnetic torque of simple reflectance generator can be positive at a time and negative at other time. It is utilized to design a permanent magnet reluctance generator specifically. Generator is designed by combining two simple reluctance generators, consists of two rotors mounted on the same shaft, two output-windings and a field source of the permanent magnet. By this design, the electromagnetic torque on both rotor will be eliminated each other, so the input torque generator can be smaller. Rotor is expected only to regulate the flux flow to both output windings alternately, until the magnetic energy is converted into electrical energy, such as occurs in the transformer energy conversion. ​​The prototype trials have been made to test this design. The test result show that the new design of permanent magnets reluctance generator able to convert energy from permanent magnets into electrical energy, this is proven by the existence 167% power output compared to the shaft input power.

Keywords: Energy, Magnet permanent, Reluctance generator.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2796

Authors: Moorthi S., Meganathan D., Janarthanan D., Praveen Kumar P., J. Raja paul perinbam

Abstract:

An efficient architecture for low jitter All Digital Phase Locked Loop (ADPLL) suitable for high speed SoC applications is presented in this paper. The ADPLL is designed using standard cells and described by Hardware Description Language (HDL). The ADPLL implemented in a 90 nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. The simulation result shows that PLL has cycle to cycle jitter of 164 ps and period jitter of 100 ps at 100MHz. Since the digitally controlled oscillator (DCO) can achieve both high resolution and wide frequency range, it can meet the demands of system-level integration. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for System-on-Chip (SoC) applications.

Keywords: All Digital Phase Locked Loop (ADPLL), Systemon-Chip (SoC), Phase Locked Loop (PLL), Very High speedIntegrated Circuit (VHSIC) Hardware Description Language(VHDL), Digitally Controlled Oscillator (DCO), Phase frequencydetector (PFD) and Voltage Controlled Oscillator (VCO).

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 3015

Authors: Jin-Lung Guan, Jyh-Cherng Gu, Ming-Ta Yang, Hsin-Hung Chang, Chun-Wei Huang, Shao-Yu Huang

Abstract:

One of the most important power quality issues is voltage flicker. Nowadays this issue also impacts the power system all over the world. The fact of the matter is that the more and the larger capacity of wind generator has been installed. Under unstable wind power situation, the variation of output current and voltage have caused trouble to voltage flicker. Hence, the major purpose of this study is to analyze the impact of wind generator on voltage flicker of power system. First of all, digital simulation and analysis are carried out based on wind generator operating under various system short circuit capacity, impedance angle, loading, and power factor of load. The simulation results have been confirmed by field measurements.

Keywords: Wind Generator, Voltage Flicker

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1967

Authors: Deepthi P.P., P.S. Sathidevi

Abstract:

Proposal for a secure stream cipher based on Linear Feedback Shift Registers (LFSR) is presented here. In this method, shift register structure used for polynomial modular division is combined with LFSR keystream generator to yield a new keystream generator with much higher periodicity. Security is brought into this structure by using the Boolean function to combine state bits of the LFSR keystream generator and taking the output through the Boolean function. This introduces non-linearity and security into the structure in a way similar to the Non-linear filter generator. The security and throughput of the suggested stream cipher is found to be much greater than the known LFSR based structures for the same key length.

Keywords: Linear Feedback Shift Register, Stream Cipher, Filter generator, Keystream generator, Modular division circuit

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2677

Authors: Zhou Yingkun, Xu Guorui, Wei Siming, Huang Yongzhang

Abstract:

With the increasing of the penetration of renewable energy in power system, the whole inertia of the power system is declining, which will endanger the frequency stability of the power system. In order to enhance the inertia, virtual synchronous generator (VSG) has been proposed. In addition, the motor-generator pair (MGP) system is proposed to enhance grid inertia. Both of them need additional equipment to provide instantaneous energy, so the economic problem should be considered. In this paper, the basic working principle of MGP system and VSG are introduced firstly. Then, the technical characteristics and economic investment of MGP/VSG are compared by calculation and simulation. The results show that the MGP system can provide same inertia with less cost than VSG.

Keywords: High renewable energy penetration, inertia of power system, virtual synchronous generator, motor-generator pair system, techno-economic analysis.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1195

Authors: A. Hassannia, S. Ramezani

Abstract:

The technology of superconductivity has developed in many power system devices such as transmission cable, transformer, current limiter, motor and generator. Superconducting wires can carry high density current without loss, which is the capability that is used to design the compact, lightweight and more efficient electrical machines. Superconducting motors have found applications in marine and air propulsion systems as well as superconducting generators are considered in low power hydraulic and wind generators. This paper presents a rim-driven superconducting synchronous generator for hydraulic power plant. The rim-driven concept improves the performance of hydro turbine. Furthermore, high magnetic field that is produced by superconducting windings allows replacing the rotor core. As a consequent, the volume and weight of the machine is decreased significantly. In this paper, a 1 MW coreless rim-driven superconducting synchronous generator is designed. Main performance characteristics of the proposed machine are then evaluated using finite elements method and compared to an ordinary similar size synchronous generator.

Keywords: Coreless machine, electrical machine design, hydraulic generator, rim-driven machine, superconducting generator.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 896

Authors: Tsunwai Gary Yip

Abstract:

Phase locked loops for data links operating at 10 Gb/s or faster are low phase noise devices designed to operate with a low jitter reference clock. Characterization of their jitter transfer function is difficult because the intrinsic noise of the device is comparable to the random noise level in the reference clock signal. A linear model is proposed to account for the intrinsic noise of a PLL. The intrinsic noise data of a PLL for 10 Gb/s links is presented. The jitter transfer function of a PLL in a test chip for 12.8 Gb/s data links was determined in experiments using the 400 MHz reference clock as the source of simultaneous excitations over a wide range of frequency. The result shows that the PLL jitter transfer function can be approximated by a second order linear model.

Keywords: Intrinsic phase noise, jitter in data link, PLL jitter transfer function, high speed clocking in electronic circuit

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1890

Authors: M. Ouassaid, A. Nejmi, M. Cherkaoui, M. Maaroufi

Abstract:

The very nonlinear nature of the generator and system behaviour following a severe disturbance precludes the use of classical linear control technique. In this paper, a new approach of nonlinear control is proposed for transient and steady state stability analysis of a synchronous generator. The control law of the generator excitation is derived from the basis of Lyapunov stability criterion. The overall stability of the system is shown using Lyapunov technique. The application of the proposed controller to simulated generator excitation control under a large sudden fault and wide range of operating conditions demonstrates that the new control strategy is superior to conventional automatic voltage regulator (AVR), and show very promising results.

Keywords: Excitation control, Lyapunov technique, non linearcontrol, synchronous generator, transient stability, voltage regulation.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2568

Authors: Tsunwai Gary Yip

Abstract:

Phase locked loops in 10 Gb/s and faster data links are low phase noise devices. Characterization of their phase jitter transfer functions is difficult because the intrinsic noise of the PLLs is comparable to the phase noise of the reference clock signal. The problem is solved by using a linear model to account for the intrinsic noise. This study also introduces a novel technique for measuring the transfer function. It involves the use of the reference clock as a source of wideband excitation, in contrast to the commonly used sinusoidal excitations at discrete frequencies. The data reported here include the intrinsic noise of a PLL for 10 Gb/s links and the jitter transfer function of a PLL for 12.8 Gb/s links. The measured transfer function suggests that the PLL responded like a second order linear system to a low noise reference clock.

Keywords: Intrinsic phase noise, jitter in data link, PLL jitter transfer function, high speed clocking in electronic circuit

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1552

Authors: Kamran Yousefpour, Mojtaba Rostaghi-Chalaki, Jason Warden, David Wallace, Chanyeop Park

Abstract:

There has been a rising trend in using impulse current generators to investigate the lightning strike protection of materials including aluminum and composites in structures such as wind turbine blade and aircraft body. The focus of this research is to present an impulse current generator built in the High Voltage Lab at Mississippi State University. The generator is capable of producing component A and D of the natural lightning discharges in accordance with the Society of Automotive Engineers (SAE) standard, which is widely used in the aerospace industry. The generator can supply lightning impulse energy up to 400 kJ with the capability of producing impulse currents with magnitudes greater than 200 kA. The electrical circuit and physical components of an improved impulse current generator are described and several lightning strike waveforms with different amplitudes is presented for comparing with the standard waveform. The results of this study contribute to the fundamental understanding the functionality of the impulse current generators and present an impulse current generator developed at the High Voltage Lab of Mississippi State University.

Keywords: impulse current generator, lightning, society of automotive engineers, capacitor

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 678

Authors: Jingjing Lan, Jun Yu, Muthukumaraswamy Annamalai Arasu

Abstract:

This paper presents a digital non-linear pulse-width modulation (PWM) controller in a high-voltage (HV) buck-boost DC-DC converter for the piezoelectric transducer of the down-hole acoustic telemetry system. The proposed design controls the generation of output signal with voltage higher than the supply voltage and is targeted to work under high temperature. To minimize the power consumption and silicon area, a simple and efficient design scheme is employed to develop the PWM controller. The proposed PWM controller consists of serial to parallel (S2P) converter, data assign block, a mode and duty cycle controller (MDC), linearly PWM (LPWM) and noise shaper, pulse generator and clock generator. To improve the reliability of circuit operation at higher temperature, this design is fabricated with the 1.0-μm silicon-on-insulator (SOI) CMOS process. The implementation results validated that the proposed design has the advantages of smaller size, lower power consumption and robust thermal stability.

Keywords: DC-DC power conversion, digital control, high temperatures, pulse-width modulation.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1658

Authors: A. A. Penin

Abstract:

Requirements that should be met when determining the regimes of circuits with variable elements are formulated. The interpretation of the variations in the regimes, based on projective geometry, enables adequate expressions for determining and comparing the regimes to be derived. It is proposed to use as the parameters of a generalized equivalent generator of an active two-pole with changeable resistor such load current and voltage which provide the current through this resistor equal to zero.

Keywords: Equivalent generator, geometric circuits theory, circuits regimes, load characteristics, variable elements.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1348

Authors: Santanu Santra, Utpal Roy

Abstract:

Quantum-dot Cellular Automata (QCA) is one of the most substitute emerging nanotechnologies for electronic circuits, because of lower power consumption, higher speed and smaller size in comparison with CMOS technology. The basic devices, a Quantum-dot cell can be used to implement logic gates and wires. As it is the fundamental building block on nanotechnology circuits. By applying XOR gate the hardware requirements for a QCA circuit can be decrease and circuits can be simpler in terms of level, delay and cell count. This article present a modest approach for implementing novel optimized XOR gate, which can be applied to design many variants of complex QCA circuits. Proposed XOR gate is simple in structure and powerful in terms of implementing any digital circuits. In order to verify the functionality of the proposed design some complex implementation of parity generator and parity checker circuits are proposed and simulating by QCA Designer tool and compare with some most recent design. Simulation results and physical relations confirm its usefulness in implementing every digital circuit.

Keywords: Clock, CMOS technology, Logic gates, QCA Designer, Quantum-dot Cellular Automata (QCA).

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 7769

Authors: Hafiz ul Azad, Dragan V.Lazic, Waqar Shahid

Abstract:

This paper presents implementation of attitude controller for a small UAV using field programmable gate array (FPGA). Due to the small size constrain a miniature more compact and computationally extensive; autopilot platform is needed for such systems. More over UAV autopilot has to deal with extremely adverse situations in the shortest possible time, while accomplishing its mission. FPGAs in the recent past have rendered themselves as fast, parallel, real time, processing devices in a compact size. This work utilizes this fact and implements different attitude controllers for a small UAV in FPGA, using its parallel processing capabilities. Attitude controller is designed in MATLAB/Simulink environment. The discrete version of this controller is implemented using pipelining followed by retiming, to reduce the critical path and thereby clock period of the controller datapath. Pipelined, retimed, parallel PID controller implementation is done using rapidprototyping and testing efficient development tool of “system generator", which has been developed by Xilinx for FPGA implementation. The improved timing performance enables the controller to react abruptly to any changes made to the attitudes of UAV.

Keywords: Field Programmable gate array (FPGA), Hardwaredescriptive Language (HDL), PID, Pipelining, Retiming, XilinxSystem Generator.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 3129

Authors: Gilberto Gonzalez-A, Noe Barrera-G

Abstract:

An analysis of a synchronous generator in a bond graph approach is proposed. This bond graph allows to determine the simplified models of the system by using singular perturbations. Firstly, the nonlinear bond graph of the generator is linearized. Then, the slow and fast state equations by applying singular perturbations are obtained. Also, a bond graph to get the quasi-steady state of the slow dynamic is proposed. In order to verify the effectiveness of the singularly perturbed models, simulation results of the complete system and reduced models are shown.

Keywords: Bond graph modelling, synchronous generator, singular perturbations

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1653

Authors: Jinkyu Park, Yungjin Kim, Byungdeok In, Sangki Park, Kihyung Lee

Abstract:

Internal combustion engines rejects 30-40% of the energy supplied by fuel to the environment through exhaust gas. thus, there is a possibility for further significant improvement of efficiency with the utilization of exhaust gas energy and its conversion to mechanical energy or electrical energy. The Thermo-Electric Generator (TEG) will be located in the exhaust system and will make use of an energy flow between the warmer exhaust gas and the external environment. Predict to th optimum position of temperature distribution and the performance of TEG through numerical analysis. The experimental results obtained show that the power output significantly increases with the temperature difference between cold and hot sides of a thermoelectric generator.

Keywords: Thermoelectric generator, Numerical analysis, Seebeck coefficient, Figure of merit

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2231