Search results for: CTU – Clock and Test Unit

Authors: Se-Jin Ko, Deok-Min Kim, Seok-Yoon Kim

Abstract:

The trend of growing density on chips has increases not only the temperature in chips but also the gradient of the temperature depending on locations. In this paper, we propose the balanced skew tree generation technique for minimizing the clock skew that is affected by the temperature gradients on chips. We calculate the interconnect delay using Elmore delay equation, and find out the optimal balanced clock tree by modifying the clock trees generated through the Deferred Merge Embedding(DME) algorithm. The experimental results show that the distance variance of clock insertion points with and without considering the temperature gradient can be lowered below 54% and we confirm that the skew is remarkably decreased after applying the proposed technique.

Keywords: clock, clock-skew, temperature, thermal.

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Authors: R. Manjith, C. Muthukumari

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In this paper, a novel Linear Feedback Shift Register (LFSR) with Look Ahead Clock Gating (LACG) technique is presented to reduce the power consumption in modern processors and System-on-Chip. Clock gating is a predominant technique used to reduce unwanted switching of clock signals. Several clock gating techniques to reduce the dynamic power have been developed, of which LACG is predominant. LACG computes the clock enabling signals of each flip-flop (FF) one cycle ahead of time, based on the present cycle data of the flip-flops on which it depends. It overcomes the timing problems in the existing clock gating methods like datadriven clock gating and Auto-Gated flip-flops (AGFF) by allotting a full clock cycle for the determination of the clock enabling signals. Further to reduce the power consumption in LACG technique, FFs can be grouped so that they share a common clock enabling signal. Simulation results show that the novel grouped LFSR with LACG achieves 15.03% power savings than conventional LFSR with LACG and 44.87% than data-driven clock gating.

Keywords: AGFF, data-driven, LACG, LFSR.

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Authors: Sharareh Afsharian, Andrea Bei, Marco Bianchi

Abstract:

In this paper we introduce a new unit test technique called déjà-vu object. Déjà-vu objects replace real objects used by classes under test, allowing the execution of isolated unit tests. A déjà-vu object is able to observe and record the behaviour of a real object during real sessions, and to replace it during unit tests, returning previously recorded results. Consequently déjà-vu object technique can be useful when a bottom-up development and testing strategy is adopted. In this case déjà-vu objects can increase test portability and test source code readability. At the same time they can reduce the time spent by programmers to develop test code and the risk of incompatibility during the switching between déjà-vu and production code.

Keywords: Bottom-up testing approach, integration test, testportability, unit test.

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Authors: Il-Do Jeong, Hang-Geun Jeong

Abstract:

This paper describes the design and fabrication of a clock and data recovery circuit (CDR). We propose a new clock and data recovery which is based on a 1/4-rate frequency detector (QRFD). The proposed frequency detector helps reduce the VCO frequency and is thus advantageous for high speed application. The proposed frequency detector can achieve low jitter operation and extend the pull-in range without using the reference clock. The proposed CDR was implemented using a 1/4-rate bang-bang type phase detector (PD) and a ring voltage controlled oscillator (VCO). The CDR circuit has been fabricated in a standard 0.18 CMOS technology. It occupies an active area of 1 x 1 and consumes 90 mW from a single 1.8V supply.

Keywords: Clock and data recovery, 1/4-rate frequency detector, 1/4-rate phase detector.

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Authors: Semih Demir, Anil Celebi

Abstract:

Circuit switched networks widely used until the end of the 20^th century have been transformed into packages switched networks. Time Division Multiplexing over Internet Protocol (TDMoIP) is a system that enables Time Division Multiplexing (TDM) traffic to be carried over packet switched networks (PSN). In TDMoIP systems, devices that send TDM data to the PSN and receive it from the network must operate with the same clock frequency. In this study, it was aimed to implement clock synchronization process in Field Programmable Gate Array (FPGA) chips using time information attached to the packages received from PSN. The designed hardware is verified using the datasets obtained for the different carrier types and comparing the results with the software model. Field tests are also performed by using the real time TDMoIP system.

Keywords: Clock recovery on TDMoIP, FPGA, MATLAB reference model, clock synchronization.

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Authors: Ahmed Madian, Muaz Aljarhi

Abstract:

Coordinate Rotation Digital Computer (CORDIC) is a unique digital computing unit intended for the computation of mathematical operations and functions. This paper presents A multi CORDIC processor that integrates different CORDIC architectures on a single FPGA chip and allows the user to select the CORDIC architecture to proceed with based on what he wants to calculate and his needs. Synthesis show that radix 2 CORDIC has the lowest clock delay, radix 8 CORDIC has the highest LUT usage and lowest register usage while Hybrid Radix 4 CORDIC had the highest clock delay.

Keywords: Multi, CORDIC, FPGA, Processor.

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Authors: Wararit Panichkitkosolkul

Abstract:

The unit root tests based on the robust estimator for the first-order autoregressive process are proposed and compared with the unit root tests based on the ordinary least squares (OLS) estimator. The percentiles of the null distributions of the unit root test are also reported. The empirical probabilities of Type I error and powers of the unit root tests are estimated via Monte Carlo simulation. Simulation results show that all unit root tests can control the probability of Type I error for all situations. The empirical power of the unit root tests based on the robust estimator are higher than the unit root tests based on the OLS estimator.

Keywords: Autoregressive, Ordinary least squares, Type I error, Power of the test, Monte Carlo simulation.

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Authors: Tsunwai Gary Yip

Abstract:

Phase locked loops for data links operating at 10 Gb/s or faster are low phase noise devices designed to operate with a low jitter reference clock. Characterization of their jitter transfer function is difficult because the intrinsic noise of the device is comparable to the random noise level in the reference clock signal. A linear model is proposed to account for the intrinsic noise of a PLL. The intrinsic noise data of a PLL for 10 Gb/s links is presented. The jitter transfer function of a PLL in a test chip for 12.8 Gb/s data links was determined in experiments using the 400 MHz reference clock as the source of simultaneous excitations over a wide range of frequency. The result shows that the PLL jitter transfer function can be approximated by a second order linear model.

Keywords: Intrinsic phase noise, jitter in data link, PLL jitter transfer function, high speed clocking in electronic circuit

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Authors: Petr Šimek, Kamil Kostruk

Abstract:

This paper deals with the problem of testing the Electronic Control Unit (ECU) for the specified function validation. Modern ECUs have many functions which need to be tested. This process requires tracking between the test and the specification. The technique discussed in this paper explores the system for automating this process. The paper focuses on the introduction to the problem in general, then it describes the proposed test system concept and its principle. It looks at how the process of the ECU interface specification file for automated interface testing and test tracking works. In the end, the future possible development of the project is discussed.

Keywords: Electronic control unit testing, embedded system, test generate, test automation, process automation, CAN bus, Ethernet.

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Authors: C Hisham, K Komal, Amit K Mishra

Abstract:

Full search block matching algorithm is widely used for hardware implementation of motion estimators in video compression algorithms. In this paper we are proposing a new architecture, which consists of a 2D parallel processing unit and a 1D unit both working in parallel. The proposed architecture reduces both data access power and computational power which are the main causes of power consumption in integer motion estimation. It also completes the operations with nearly the same number of clock cycles as compared to a 2D systolic array architecture. In this work sum of absolute difference (SAD)-the most repeated operation in block matching, is calculated in two steps. The first step is to calculate the SAD for alternate rows by a 2D parallel unit. If the SAD calculated by the parallel unit is less than the stored minimum SAD, the SAD of the remaining rows is calculated by the 1D unit. Early termination, which stops avoidable computations has been achieved with the help of alternate rows method proposed in this paper and by finding a low initial SAD value based on motion vector prediction. Data reuse has been applied to the reference blocks in the same search area which significantly reduced the memory access.

Keywords: Sum of absolute difference, high speed DSP.

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Authors: Agata M. Kołodziejczyk, Mateusz Harasymczuk, Pierre-Yves Girardin, Lucie Davidová

Abstract:

Subjective time perception implies connection to cognitive functions, attention, memory and awareness, but a little is known about connections with homeostatic states of the body coordinated by circadian clock. In this paper, we present results from experimental study of subjective time perception in volunteers performing physical activity on treadmill in various phases of their circadian rhythms. Subjects were exposed to several time illusions simulated by programmed timing systems. This study brings better understanding for further improvement of of work quality in isolated areas. 

Keywords: Biological clock, light, time illusions, treadmill.

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Authors: Abdelghani Dendouga, Nour-Eddine Bouguechal, Souhil Kouda, Samir Barra

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A behavioral model of a second order switchedcapacitor Sigma-Delta modulator is presented. The purpose of this work is the presentation of a behavioral model of a second order switched capacitor ΣΔ modulator considering (Error due to Clock Jitter, Thermal noise Amplifier Noise, Amplifier Slew-Rate, Non linearity of amplifiers, Gain error, Charge Injection, Clock Feedthrough, and Nonlinear on-resistance). A comparison between the use of MOS switches and the use transmission gate switches use is analyzed.

Keywords: Charge injection, clock feed through, Sigma Deltamodulators, Sigma Delta non-idealities, switched capacitor.

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Authors: Chathurika D. Abeyrathne, Malka N. Halgamuge, Peter M. Farrell

Abstract:

There is an ongoing controversy in the literature related to the biological effects of weak, low frequency electromagnetic fields. The physical arguments and interpretation of the experimental evidence are inconsistent, where some physical arguments and experimental demonstrations tend to reject the likelihood of any effect of the fields at extremely low level. The problem arises of explaining, how the low-energy influences of weak magnetic fields can compete with the thermal and electrical noise of cells at normal temperature using the theoretical studies. The magnetoreception in animals involve radical pair mechanism. The same mechanism has been shown to be involved in the circadian rhythm synchronization in mammals. These reactions can be influenced by the weak magnetic fields. Hence, it is postulated the biological clock can be affected by weak magnetic fields and these disruptions to the rhythm can cause adverse biological effects. In this paper, likelihood of altering the biological clock via the radical pair mechanism is analyzed to simplify these studies of controversy.

Keywords: Bio-effect, biological clock, magnetoreception, radical pair mechanism, weak magnetic field.

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Authors: Dong He Nam, Eric C. Mousset, David C. Levy

Abstract:

The evolution of current modeling specifications gives rise to the problem of generating automated test cases from a variety of application tools. Past endeavours on behavioural testing of UML statecharts have not systematically leveraged the potential of existing graph theory for testing of objects. Therefore there exists a need for a simple, tool-independent, and effective method for automatic test generation. An architecture, codenamed ACUTE-J (Automated stateChart Unit Testing Engine for Java), for automating the unit test generation process is presented. A sequential approach for converting UML statechart diagrams to JUnit test classes is described, with the application of existing graph theory. Research byproducts such as a universal XML Schema and API for statechart-driven testing are also proposed. The result from a Java implementation of ACUTE-J is discussed in brief. The Chinese Postman algorithm is utilised as an illustration for a run-through of the ACUTE-J architecture.

Keywords: Automated testing, model based testing, statechart testing, UML, unit testing.

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Authors: Thanawat Chuleekiat

Abstract:

Socketing of bored piles in rock is always seen as a matter of debate on construction sites between consultants and contractors. The socketing depth normally depends on the type of rock, depth at which the rock is available below the pile cap and load carrying capacity of the pile. In this paper, the review of field load test data of drilled shaft socketed in weathered limestone conducted using conventional static pile load test and dynamic pile load test was made to evaluate a unit shaft friction for the bored piles socketed in weathered limestone (weak rock). The borehole drilling data were also reviewed in conjunction with the pile test result. In addition, the back-calculated unit shaft friction was reviewed against various empirical methods for bored piles socketed in weak rock. The paper concludes with an estimated ultimate unit shaft friction from the case study in Qatar for preliminary design.

Keywords: Piled foundation, weathered limestone, shaft friction, rock socket, pile load test.

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Authors: Niveditha Domse, Kris Kumar, K. N. Balasubramanya Murthy

Abstract:

The more recent satellite projects/programs makes extensive usage of real – time embedded systems. 16 bit processors which meet the Mil-Std-1750 standard architecture have been used in on-board systems. Most of the Space Applications have been written in ADA. From a futuristic point of view, 32 bit/ 64 bit processors are needed in the area of spacecraft computing and therefore an effort is desirable in the study and survey of 64 bit architectures for space applications. This will also result in significant technology development in terms of VLSI and software tools for ADA (as the legacy code is in ADA). There are several basic requirements for a special processor for this purpose. They include Radiation Hardened (RadHard) devices, very low power dissipation, compatibility with existing operational systems, scalable architectures for higher computational needs, reliability, higher memory and I/O bandwidth, predictability, realtime operating system and manufacturability of such processors. Further on, these may include selection of FPGA devices, selection of EDA tool chains, design flow, partitioning of the design, pin count, performance evaluation, timing analysis etc. This project deals with a brief study of 32 and 64 bit processors readily available in the market and designing/ fabricating a 64 bit RISC processor named RISC MicroProcessor with added functionalities of an extended double precision floating point unit and a 32 bit signal processing unit acting as co-processors. In this paper, we emphasize the ease and importance of using Open Core (OpenSparc T1 Verilog RTL) and Open “Source" EDA tools such as Icarus to develop FPGA based prototypes quickly. Commercial tools such as Xilinx ISE for Synthesis are also used when appropriate.

Keywords: RISC MicroProcessor, RPC – RISC Processor Core, PBX – Processor to Block Interface part of the Interconnection Network, BPX – Block to Processor Interface part of the Interconnection Network, FPU – Floating Point Unit, SPU – Signal Processing Unit, WB – Wishbone Interface, CTU – Clock and Test Unit

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Authors: Anwar Hasan Abdullah Othman, Ahamed Kameel, Hasanuddeen Abdul Aziz

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In this study, attempt has been made to investigate the relationship specifically the causal relation between fund unit prices of Islamic equity unit trust fund which measure by fund NAV and the selected macro-economic variables of Malaysian economy by using VECM causality test and Granger causality test. Monthly data has been used from Jan, 2006 to Dec, 2012 for all the variables. The findings of the study showed that industrial production index, political election and financial crisis are the only variables having unidirectional causal relationship with fund unit price. However the global oil price is having bidirectional causality with fund NAV. Thus, it is concluded that the equity unit trust fund industry in Malaysia is an inefficient market with respect to the industrial production index, global oil prices, political election and financial crisis. However the market is approaching towards informational efficiency at least with respect to four macroeconomic variables, treasury bill rate, money supply, foreign exchange rate, and corruption index.

Keywords: Fund unit price, unit trust industry, Malaysia, macroeconomic variables, causality.

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Authors: Tsunwai Gary Yip

Abstract:

Phase locked loops in 10 Gb/s and faster data links are low phase noise devices. Characterization of their phase jitter transfer functions is difficult because the intrinsic noise of the PLLs is comparable to the phase noise of the reference clock signal. The problem is solved by using a linear model to account for the intrinsic noise. This study also introduces a novel technique for measuring the transfer function. It involves the use of the reference clock as a source of wideband excitation, in contrast to the commonly used sinusoidal excitations at discrete frequencies. The data reported here include the intrinsic noise of a PLL for 10 Gb/s links and the jitter transfer function of a PLL for 12.8 Gb/s links. The measured transfer function suggests that the PLL responded like a second order linear system to a low noise reference clock.

Keywords: Intrinsic phase noise, jitter in data link, PLL jitter transfer function, high speed clocking in electronic circuit

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Authors: Wen-Chi Liu

Abstract:

This study applies a simple and powerful nonlinear unit root test to test the validity of long-run purchasing power parity (PPP)  in a sample of 10 East-Asian countries (i.e., China, Hong Kong,  Indonesia, Japan, Korea, Malaysia, Philippines, Singapore, Taiwan  and Thailand) over the period of March 1985 to September 2008. The empirical results indicate that PPP holds true for half of these 10  East-Asian countries under study, and the adjustment toward PPP is found to be nonlinear and in an asymmetric way. 

 

Keywords: Purchasing Power Parity, East-Asian Countries, Nonlinear Unit Root Test, Asymmetry.

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Authors: Nooshin Salari, Viliam Makis, Jane Doe

Abstract:

This paper presents a maintenance policy for a system consisting of two units. Unit 1 is gradually deteriorating and is subject to soft failure. Unit 2 has a general lifetime distribution and is subject to hard failure. Condition of unit 1 of the system is monitored periodically and it is considered as failed when its deterioration level reaches or exceeds a critical level N. At the failure time of unit 2 system is considered as failed, and unit 2 will be correctively replaced by the next inspection epoch. Unit 1 or 2 are preventively replaced when deterioration level of unit 1 or age of unit 2 exceeds the related preventive maintenance (PM) levels. At the time of corrective or preventive replacement of unit 2, there is an opportunity to replace unit 1 if its deterioration level reaches the opportunistic maintenance (OM) level. If unit 2 fails in an inspection interval, system stops operating although unit 1 has not failed. A mathematical model is derived to find the preventive and opportunistic replacement levels for unit 1 and preventive replacement age for unit 2, that minimize the long run expected average cost per unit time. The problem is formulated and solved in the semi-Markov decision process (SMDP) framework. Numerical example is provided to illustrate the performance of the proposed model and the comparison of the proposed model with an optimal policy without opportunistic maintenance level for unit 1 is carried out.

Keywords: Condition-based maintenance, opportunistic maintenance, preventive maintenance, two-unit system.

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Authors: Fotis N. Koumboulis, Maria P. Tzamtzi

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A supervisory scheme is proposed that implements Stepwise Safe Switching Logic. The functionality of the supervisory scheme is organized in the following eight functional units: Step- Wise Safe Switching unit, Common controllers design unit, Experimentation unit, Simulation unit, Identification unit, Trajectory cruise unit, Operating points unit and Expert system unit. The supervisory scheme orchestrates both the off-line preparative actions, as well as the on-line actions that implement the Stepwise Safe Switching Logic. The proposed scheme is a generic tool, that may be easily applied for a variety of industrial control processes and may be implemented as an automation software system, with the use of a high level programming environment, like Matlab.

Keywords: Supervisory systems, safe switching, nonlinear systems.

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Authors: Wen-Chi Liu

Abstract:

This paper aims to examine whether a bubble is present in the housing market of China. Thus, we use the housing  price-to-income ratios and housing price-to-rent ratios of 35 cities from 1998 to 2010. The methods of the panel KSS unit root test with a  Fourier function and the SPSM process are likewise used. The panel  KSS unit root test with a Fourier function considers the problem of  non-linearity and structural changes, and the SPSM process can avoid  the stationary time series from dominating the result-generated bias.  Through a rigorous empirical study, we determine that the housing  price-to-income ratios are stationary in 34 of the 35 cities in China.  Only Xining is non-stationary. The housing price-to-rent ratios are  stationary in 32 of the 35 cities in China. Chengdu, Fuzhou, and  Zhengzhou are non-stationary. Overall, the housing bubbles are not a  serious problem in China at the time.

 

Keywords: Housing Price-to-Income Ratio, Housing Price-to-Rent Ratio, Housing Bubbles, Panel Unit-Root Test.

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Authors: Michal Spilacek, Marian Brazdil, Otakar Stelcl, Jiri Pospisil

Abstract:

This paper shows an experimental testing of a small unit for combustion of solid fuels, such as charcoal and wood logs, that can provide electricity. One of the concepts is that the unit does not require qualified personnel for its operation. The unit itself is composed of two main parts. The design requires a heat producing stove and electricity producing thermoelectric generator. After the construction the unit was tested and the results show that the emission release is within the legislative requirements for emission production and environmental protection. That qualifies such unit for indoor application.

Keywords: Micro-cogeneration, thermoelectric generator, biomass combustion, wood stove.

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Authors: Mansi Jhamb, R. K. Sharma, A. K. Gupta

Abstract:

In the current scenario, with the increasing integration densities, most system-on-chip designs are partitioned into multiple clock domains. In this paper, an asynchronous FIFO (First-in First-out pipeline) design is employed as a data transfer interface between two independent clock domains. Since the clocks on the either sides of the FIFO run at a different speed, the task to ensure the correct data transmission through this FIFO is manually performed. Firstly an existing asynchronous FIFO design is discussed and simulated. Gate-level simulation results depicted the flaw in existing design. In order to solve this problem, a novel modified asynchronous FIFO design is proposed. The results obtained from proposed design are in perfect accordance with theoretical expectations. The proposed asynchronous FIFO design outperforms the existing design in terms of accuracy and speed. In order to evaluate the performance of the FIFO designs presented in this paper, the circuits were implemented in 0.24µ TSMC CMOS technology and simulated at 2.5V using HSpice (© Avant! Corporation). The layout design of the proposed FIFO is also presented.

Keywords: Asynchronous, Clock, CMOS, C-element, FIFO, Globally Asynchronous Locally Synchronous (GALS), HSpice.

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Authors: Jianping Hu, Xiaolei Sheng

Abstract:

This paper introduces an adiabatic register file based on two-phase CPAL (Complementary Pass-Transistor Adiabatic Logic circuits) with power-gating scheme, which can operate on a single-phase power clock. A 32×32 single-phase adiabatic register file with power-gating scheme has been implemented with TSMC 0.18μm CMOS technology. All the circuits except for the storage cells employ two-phase CPAL circuits, and the storage cell is based on the conventional memory one. The two-phase non-overlap power-clock generator with power-gating scheme is used to supply the proposed adiabatic register file. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. Compared with the traditional static CMOS register file, HSPICE simulations show that the proposed adiabatic register file can work very well, and it attains about 73% energy savings at 100 MHz.

Keywords: Low power, Register file, Complementarypass-transistor logic, Adiabatic logic, Single-phase power clock.

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Authors: Zainudin Arsad, Norul Baine Mat Johor

Abstract:

Tourism industry is an important sector in Malaysia economy and this motivates the examination of long-run relationships between tourist arrivals from three selected European countries in Malaysia and four possible determinants; relative prices, exchange rates, transportation cost and relative prices of substitute destination. The study utilizes data from January 1999 to September 2008 and employs standard econometric techniques that include unit root test and cointegration test. The estimated demand model indicates that depreciation of local currency and increases in prices at substitute destination have positive impact on tourist arrivals while increase in transportation cost has negative impact on tourist arrivals. In addition, the model suggests that higher rate of increase in local prices relative to prices at tourist country of origin may not deter tourists from coming to Malaysia

Keywords: origin country, unit root test, cointegration test

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Authors: Shiang-Hwua Yu, Po-Hsun Wu

Abstract:

This study introduces two types of self-oscillating circuits that are frequently found in power electronics applications. Special effort is made to relate the circuits to the analogous mechanical systems of some important scientific inventions: Galileo’s pendulum clock and Coulomb’s friction model. A little touch of related history and philosophy of science will hopefully encourage curiosity, advance the understanding of self-oscillating systems and satisfy the aspiration of some students for scientific literacy. Finally, the two self-oscillating circuits are applied to design a simple class-D audio amplifier.

Keywords: Self-oscillation, sigma-delta modulator, pendulum clock, Coulomb friction, class-D amplifier.

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Authors: Yi-Haur Shiau, Sun-In Lin, Shi-Wei Lo, Hsiu-Mei Chou, Yi-Hsuan Chen

Abstract:

This paper proposes a novel multi-format stream grid architecture for real-time image monitoring system. The system, based on a three-tier architecture, includes stream receiving unit, stream processor unit, and presentation unit. It is a distributed computing and a loose coupling architecture. The benefit is the amount of required servers can be adjusted depending on the loading of the image monitoring system. The stream receive unit supports multi capture source devices and multi-format stream compress encoder. Stream processor unit includes three modules; they are stream clipping module, image processing module and image management module. Presentation unit can display image data on several different platforms. We verified the proposed grid architecture with an actual test of image monitoring. We used a fast image matching method with the adjustable parameters for different monitoring situations. Background subtraction method is also implemented in the system. Experimental results showed that the proposed architecture is robust, adaptive, and powerful in the image monitoring system.

Keywords: Motion detection, grid architecture, image monitoring system, and background subtraction.

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Authors: Loke Mun Sei

Abstract:

Software testing has become a mandatory process in assuring the software product quality. Hence, test management is needed in order to manage the test activities conducted in the software test life cycle. This paper discusses on the challenges faced in the software test life cycle, and how the test processes and test activities, mainly on test cases creation, test execution, and test reporting is being managed and automated using several test automation tools, i.e. Jira, Robot Framework, and Jenkins.

Keywords: Test automation tools, test case, test execution, test reporting.

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Authors: Jehad Al Dallal, Paul Sorenson

Abstract:

An application framework provides a reusable design and implementation for a family of software systems. Frameworks are introduced to reduce the cost of a product line (i.e., family of products that share the common features). Software testing is a time consuming and costly ongoing activity during the application software development process. Generating reusable test cases for the framework applications at the framework development stage, and providing and using the test cases to test part of the framework application whenever the framework is used reduces the application development time and cost considerably. Framework Interface Classes (FICs) are classes introduced by the framework hooks to be implemented at the application development stage. They can have reusable test cases generated at the framework development stage and provided with the framework to test the implementations of the FICs at the application development stage. In this paper, we conduct a case study using thirteen applications developed using three frameworks; one domain oriented and two application oriented. The results show that, in general, the percentage of the number of FICs in the applications developed using domain frameworks is, on average, greater than the percentage of the number of FICs in the applications developed using application frameworks. Consequently, the reduction of the application unit testing time using the reusable test cases generated for domain frameworks is, in general, greater than the reduction of the application unit testing time using the reusable test cases generated for application frameworks.

Keywords: FICs, object-oriented framework, object-orientedframework application, software testing.

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