Search results for: CMOS LC-based oscillator

Authors: Shilpi Lavania

Abstract:

As the frequency of operation has attained a range of GHz and signal rise time continues to increase interconnect technology is suffering due to various high frequency effects as well as ground bounce problem. In some recent studies a high frequency effect i.e. skin effect has been modeled and its drawbacks have been discussed. This paper strives to make an impression on the advantage side of modeling skin effect for interconnect line. The proposed method has considered a CMOS with RC interconnect. Delay and noise considering ground bounce problem and with skin effect are discussed. The simulation results reveal an advantage of considering skin effect for minimization of ground bounce problem during the working of the model. Noise and delay variations with temperature are also presented.

Keywords: Interconnect, Skin effect, Ground Bounce, Delay, Noise.

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Authors: Ki-Jin Kim, Sanghoon Park, K. H. Ahn

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A way of generating millimeter wave I/Q signal using inductive resonator matched poly-phase filter is suggested. Normally the poly-phase filter generates quite accurate I/Q phase and magnitude but the loss of the filter is considerable due to series connection of passive RC components. This loss term directly increases system noise figure when the poly-phase filter is used in RF Front-end. The proposed matching method eliminates above mentioned loss and in addition provides gain on the passive filter. The working algorithm is illustrated by mathematical analysis. The generated I/Q signal is used in implementing millimeter wave phase shifter for the 60 GHz communication system to verify its effectiveness. The circuit is fabricated in 90 nm TSMC RF CMOS process under 1.2 V supply voltage. The measurement results showed that the suggested method improved gain by 6.5 dB and noise by 2.3 dB. The summary of the proposed I/Q generation is compared with previous works.

Keywords: Millimeter Wave Circuits, Local Distribution, I/Q Generator.

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Authors: Khalil Monfaredi, Hassan Faraji Baghtash, Majid Abbasi

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In this paper a novel high output impedance, low input impedance, wide bandwidth, very simple current mirror with input and output voltage requirements less than that of a simple current mirror is presented. These features are achieved with very simple structure avoiding extra large node impedances to ensure high bandwidth operation. The circuit's principle of operation is discussed and compared to simple and low voltage cascode (LVC) current mirrors. Such outstanding features of this current mirror as high output impedance ~384K, low input impedance~6.4, wide bandwidth~178MHz, low input voltage ~ 362mV, low output voltage ~ 38mV and low current transfer error ~4% (all at 50μA) makes it an outstanding choice for high performance applications. Simulation results in BSIM 0.35μm CMOS technology with HSPICE are given in comparison with simple, and LVC current mirrors to verify and validate the performance of the proposed current mirror.

Keywords: Analog circuits, Current mirror, high frequency, Low power, Low voltage.

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Authors: P.Ramanathan, P.T.Vanathi

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Parallel Prefix addition is a technique for improving the speed of binary addition. Due to continuing integrating intensity and the growing needs of portable devices, low-power and highperformance designs are of prime importance. The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, fan-out and interconnect count of logic circuits. In this paper, a new architecture for performing 8-bit, 16-bit and 32-bit Parallel Prefix addition is proposed. The proposed prefix adder structures is compared with several classical adders of same bit width in terms of power, delay and number of computational nodes. The results reveal that the proposed structures have the least power delay product when compared with its peer existing Prefix adder structures. Tanner EDA tool was used for simulating the adder designs in the TSMC 180 nm and TSMC 130 nm technologies.

Keywords: Parallel Prefix Adder (PPA), Dot operator, Semi-Dotoperator, Complementary Metal Oxide Semiconductor (CMOS), Odd-dot operator, Even-dot operator, Odd-semi-dot operator andEven-semi-dot operator.

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Authors: Guo-Ming Sung, Naga Raju Naik R.

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Paper presents a low power, high speed, sense-amplifier based flip-flop (SAFF). The flip-flop’s power con-sumption and delay are greatly reduced by employing a new conditionally precharge sense-amplifier stage and a single-ended latch stage. Glitch-free and contention-free latch operation is achieved by using a conditional cut-off strategy. The design uses fewer transistors, has a lower clock load, and has a simple structure, all of which contribute to a near-zero setup time. When compared to previous flip-flop structures proposed for similar input/output conditions, this design’s performance and overall PDP have improved. The post layout simulation of the circuit uses 2.91µW of power and has a delay of 65.82 ps. Overall, the power-delay product has seen some enhancements. Cadence Virtuoso Designing tool with CMOS 90nm technology are used for all designs.

Keywords: high-speed, low-power, flip-flop, sense-amplifier

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Authors: M. Fadlallah, G. Ghibaudo, C. G. Theodorou

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The dynamic variation in memory devices such as the Static Random Access Memory can give errors in read or write operations. In this paper, the effect of low-frequency and random telegraph noise on the dynamic variation of one SRAM cell is detailed. The effect on circuit noise, speed, and length of time of processing is examined, using the Supply Read Retention Voltage and the Read Static Noise Margin. New test run methods are also developed. The obtained results simulation shows the importance of noise caused by dynamic variation, and the impact of Random Telegraph noise on SRAM variability is examined by evaluating the statistical distributions of Random Telegraph noise amplitude in the pull-up, pull-down. The threshold voltage mismatch between neighboring cell transistors due to intrinsic fluctuations typically contributes to larger reductions in static noise margin. Also the contribution of each of the SRAM transistor to total dynamic variation has been identified.

Keywords: Low-frequency noise, Random Telegraph Noise, Dynamic Variation, SRRV.

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Authors: Wei Yi Lim, M. Annamalai Arasu, M. Kumarasamy Raja, Minkyu Je

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In this paper, the design of wide-swing constant transconductance (g_m) bias circuit that generates bias voltage for low-noise amplifier (LNA) circuit design by using an off-chip resistor is demonstrated. The overall transconductance (G_m) generated by the constant g_m bias circuit is important to maintain the overall gain and noise figure of the LNA circuit. Therefore, investigation is performed to study the variation in G_m with process, temperature and supply voltage (PVT).  Temperature and supply voltage are swept from -10 °C to 85 °C and 1.425 V to 1.575 V respectively, while the process conditions are also varied to the extreme and the g_m variation is eventually concluded at between -3 % to 7 %. With the slight variation in the g_m value, through simulation, at worst condition of state SS, we are able to attain a conversion gain (S₂₁) variation of -3.10 % and a noise figure (NF) variation of 18.71 %. The whole constant g_m circuit draws approximately 100 µA from a 1.5V supply and is designed based on 0.13 µm CMOS process. 

Keywords: Transconductance, LNA, temperature, process.

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Authors: Jun Sung Go, Jong Kang Park, Jong Tae Kim

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As semi-conductor manufacturing technology evolves; the single event transient problem becomes more significant issue. Single event transient has a critical impact on both combinational and sequential logic circuits, so it is important to evaluate the soft error tolerance of the circuits at the design stage. In this paper, we present a soft error detecting simulation using scan chain. The simulation model generates a single event transient randomly in the circuit, and detects the soft error during the execution of the test patterns. We verified this model by inserting a scan chain in an 8051 microprocessor using 65 nm CMOS technology. While the test patterns generated by ATPG program are passing through the scan chain, we insert a single event transient and detect the number of soft errors per sub-module. The experiments show that the soft error rates per cell area of the SFR module is 277% larger than other modules.

Keywords: Scan chain, single event transient, soft error, 8051 processor.

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Authors: Kittipong Tripetch, Nobuhiko Nakano

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Two types of floating active resistors based on a complementary regulated cascode topology with cross-coupled regulated transistors are presented in this paper. The first topology is a high swing complementary regulated cascode active resistor. The second topology is a complementary common gate with a regulated cross coupled transistor. The small-signal input resistances of the floating resistors are derived. Three graphs of the input current versus the input voltage for different aspect ratios are designed and plotted using the Cadence Spectre 0.18-µm Rohm Semiconductor process. The total harmonic distortion graphs are plotted for three different aspect ratios with different input-voltage amplitudes and different input frequencies. From the simulation results, it is observed that a resistance of approximately 8.52 MΩ can be obtained from supply voltage at  ±0.9 V.

Keywords: Complementary common gate, complementary regulated cascode, current mirror, floating active resistors.

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Authors: Chang Soo Kang, In Ho Im, Sergey Churayev, Timour Paltashev

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This paper describes the design of new method of propagation delay measurement in micro and nanostructures during characterization of ASIC standard library cell. Providing more accuracy timing information about library cell to the design team we can improve a quality of timing analysis inside of ASIC design flow process. Also, this information could be very useful for semiconductor foundry team to make correction in technology process. By comparison of the propagation delay in the CMOS element and result of analog SPICE simulation. It was implemented as digital IP core for semiconductor manufacturing process. Specialized method helps to observe the propagation time delay in one element of the standard-cell library with up-to picoseconds accuracy and less. Thus, the special useful solutions for VLSI schematic to parameters extraction, basic cell layout verification, design simulation and verification are announced.

Keywords: phase error accumulation methodology, gatepropagation delay, Processor Testing, MEMS Testing

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Authors: Ahmed Shariful Alam, Abu Hena M. Mustafa Kamal, M. Abdul Rahman, M. Nasmus Sakib Khan Shabbir, Atiqul Islam

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According to the rules of quantum mechanics there is a non-vanishing probability of for an electron to tunnel through a thin insulating barrier or a thin capacitor which is not possible according to the laws of classical physics. Tunneling of electron through a thin insulating barrier or tunnel junction is a random event and the magnitude of current flowing due to the tunneling of electron is very low. As the current flowing through a Single Electron Transistor (SET) is the result of electron tunneling through tunnel junctions of its source and drain the supply voltage requirement is also very low. As a result, the power consumption across a Single Electron Transistor is ultra-low in comparison to that of a MOSFET. In this paper simulations have been done with PSPICE for an inverter built with both SETs and MOSFETs. 35mV supply voltage was used for a SET built inverter circuit and the supply voltage used for a CMOS inverter was 3.5V.

Keywords: ITRS, enhancement type MOSFET, island, DC analysis, transient analysis, power consumption, background charge co-tunneling.

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Authors: Somaye Abdollahi Pour, Mohsen Saneei

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This paper describes a novel monitoring scheme to minimize total active power in digital circuits depend on the demand frequency, by adjusting automatically both supply voltage and threshold voltages based on circuit operating conditions such as temperature, process variations, and desirable frequency. The delay monitoring results, will be control and apply so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. Design details of power monitor are examined using simulation framework in 32nm BTPM model CMOS process. Experimental results show the overhead of proposed circuit in terms of its power consumption is about 40 μW for 32nm technology; moreover the results show that our proposed circuit design is not far sensitive to the temperature variations and also process variations. Besides, uses the simple blocks which offer good sensitivity, high speed, the continuously feedback loop. This design provides up to 40% reduction in power consumption in active mode.

Keywords: active mode, delay monitor, body biasing, VDD scaling, low power.

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Authors: Jingjing Lan, Jun Yu, Muthukumaraswamy Annamalai Arasu

Abstract:

This paper presents a digital non-linear pulse-width modulation (PWM) controller in a high-voltage (HV) buck-boost DC-DC converter for the piezoelectric transducer of the down-hole acoustic telemetry system. The proposed design controls the generation of output signal with voltage higher than the supply voltage and is targeted to work under high temperature. To minimize the power consumption and silicon area, a simple and efficient design scheme is employed to develop the PWM controller. The proposed PWM controller consists of serial to parallel (S2P) converter, data assign block, a mode and duty cycle controller (MDC), linearly PWM (LPWM) and noise shaper, pulse generator and clock generator. To improve the reliability of circuit operation at higher temperature, this design is fabricated with the 1.0-μm silicon-on-insulator (SOI) CMOS process. The implementation results validated that the proposed design has the advantages of smaller size, lower power consumption and robust thermal stability.

Keywords: DC-DC power conversion, digital control, high temperatures, pulse-width modulation.

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Authors: Vijay Kumar Sharma, Manisha Pattanaik, Balwinder Raj

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Minimizations of power dissipation, chip area with higher circuit performance are the necessary and key parameters in deep submicron regime. The leakage current increases sharply in deep submicron regime and directly affected the power dissipation of the logic circuits. In deep submicron region the power dissipation as well as high performance is the crucial concern since increasing importance of portable systems. Number of leakage reduction techniques employed to reduce the leakage current in deep submicron region but they have some trade-off to control the leakage current. ONOFIC approach gives an excellent agreement between power dissipation and propagation delay for designing the efficient CMOS logic circuits. In this article ONOFIC approach is compared with LECTOR technique and output results show that ONOFIC approach significantly reduces the power dissipation and enhance the speed of the logic circuits. The lower power delay product is the big outcome of this approach and makes it an influential leakage reduction technique.

Keywords: Deep submicron, Leakage Current, LECTOR, ONOFIC, Power Delay Product

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Authors: Arash Azizi Mazreah, Mohammad T. Manzuri Shalmani, Hamid Barati, Ali Barati, Ali Sarchami

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This paper proposes a low power SRAM based on five transistor SRAM cell. Proposed SRAM uses novel word-line decoding such that, during read/write operation, only selected cell connected to bit-line whereas, in conventional SRAM (CV-SRAM), all cells in selected row connected to their bit-lines, which in turn develops differential voltages across all bit-lines, and this makes energy consumption on unselected bit-lines. In proposed SRAM memory array divided into two halves and this causes data-line capacitance to reduce. Also proposed SRAM uses one bit-line and thus has lower bit-line leakage compared to CV-SRAM. Furthermore, the proposed SRAM incurs no area overhead, and has comparable read/write performance versus the CV-SRAM. Simulation results in standard 0.25μm CMOS technology shows in worst case proposed SRAM has 80% smaller dynamic energy consumption in each cycle compared to CV-SRAM. Besides, energy consumption in each cycle of proposed SRAM and CV-SRAM investigated analytically, the results of which are in good agreement with the simulation results.

Keywords: SRAM, write Operation, read Operation, capacitances, dynamic energy consumption.

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Authors: A. Thomas, B. John Oommen

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Although the field of parametric Pattern Recognition (PR) has been thoroughly studied for over five decades, the use of the Order Statistics (OS) of the distributions to achieve this has not been reported. The pioneering work on using OS for classification was presented in [1] for the Uniform distribution, where it was shown that optimal PR can be achieved in a counter-intuitive manner, diametrically opposed to the Bayesian paradigm, i.e., by comparing the testing sample to a few samples distant from the mean. This must be contrasted with the Bayesian paradigm in which, if we are allowed to compare the testing sample with only a single point in the feature space from each class, the optimal strategy would be to achieve this based on the (Mahalanobis) distance from the corresponding central points, for example, the means. In [2], we showed that the results could be extended for a few symmetric distributions within the exponential family. In this paper, we attempt to extend these results significantly by considering asymmetric distributions within the exponential family, for some of which even the closed form expressions of the cumulative distribution functions are not available. These distributions include the Rayleigh, Gamma and certain Beta distributions. As in [1] and [2], the new scheme, referred to as Classification by Moments of Order Statistics (CMOS), attains an accuracy very close to the optimal Bayes’ bound, as has been shown both theoretically and by rigorous experimental testing.

Keywords: Classification using Order Statistics (OS), Exponential family, Moments of OS

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Authors: Li Long, Thomas Ortlepp

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A theoretical model for the optimization of thermopile sensor performance is developed for thermoelectric-based infrared radiation detection. It is shown that the performance of polycrystalline silicon film thermopile sensor can be optimized according to the thermoelectric quality factor, sensor layer structure factor and sensor layout shape factor. Based on the properties of electrons, phonons, grain boundaries and their interactions, the thermoelectric quality factor of polycrystalline silicon is analyzed with the relaxation time approximation of Boltzmann transport equation. The model includes the effects of grain structure, grain boundary trap properties and doping concentration. The layer structure factor of sensor is analyzed with respect to infrared absorption coefficient. The effect of layout design is characterized with the shape factor, which is calculated for different sensor designs. Double layer polycrystalline silicon thermopile infrared sensors on suspended support membrane have been designed and fabricated with a CMOS-compatible process. The theoretical approach is confirmed with measurement results.

Keywords: Polycrystalline silicon film, relaxation time approximation, specific detectivity, thermal conductivity, thermopile infrared sensor.

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Authors: Syed Iftekhar Ali, M. S. Islam

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In this paper we present an energy efficient match-line (ML) sensing scheme for high-speed ternary content-addressable memory (TCAM). The proposed scheme isolates the sensing unit of the sense amplifier from the large and variable ML capacitance. It employs feedback in the sense amplifier to successfully detect a match while keeping the ML voltage swing low. This reduced voltage swing results in large energy saving. Simulation performed using 130nm 1.2V CMOS logic shows at least 30% total energy saving in our scheme compared to popular current race (CR) scheme for similar search speed. In terms of speed, dynamic energy, peak power consumption and transistor count our scheme also shows better performance than mismatch-dependant (MD) power allocation technique which also employs feedback in the sense amplifier. Additionally, the implementation of our scheme is simpler than CR or MD scheme because of absence of analog control voltage and programmable delay circuit as have been used in those schemes.

Keywords: content-addressable memory, energy consumption, feedback, peak power, sensing scheme, sense amplifier, ternary.

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Authors: Maurizio Dapor, Isabel Abril, Pablo de Vera, Rafael Garcia-Molina

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The ionization yield of ion tracks in polymers and bio-molecular systems reaches a maximum, known as the Bragg peak, close to the end of the ion trajectories. Along the path of the ions through the materials, many electrons are generated, which produce a cascade of further ionizations and, consequently, a shower of secondary electrons. Among these, very low energy secondary electrons can produce damage in the biomolecules by dissociative electron attachment. This work deals with the calculation of the energy distribution of electrons produced by protons in a sample of polymethylmethacrylate (PMMA), a material that is used as a phantom for living tissues in hadron therapy. PMMA is also of relevance for microelectronics in CMOS technologies and as a photoresist mask in electron beam lithography. We present a Monte Carlo code that, starting from a realistic description of the energy distribution of the electrons ejected by protons moving through PMMA, simulates the entire cascade of generated secondary electrons. By following in detail the motion of all these electrons, we find the radial distribution of the energy that they deposit in PMMA for several initial proton energies characteristic of the Bragg peak.

Keywords: Monte Carlo method, secondary electrons, energetic ions, ion-beam cancer therapy, ionization cross section, polymethylmethacrylate, proton beams, secondary electrons, radial energy distribution.

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Authors: Faizal A. Samman, Thomas Hollstein, Manfred Glesner

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A synchronous network-on-chip using wormhole packet switching and supporting guaranteed-completion best-effort with low-priority (LP) and high-priority (HP) wormhole packet delivery service is presented in this paper. Both our proposed LP and HP message services deliver a good quality of service in term of lossless packet completion and in-order message data delivery. However, the LP message service does not guarantee minimal completion bound. The HP packets will absolutely use 100% bandwidth of their reserved links if the HP packets are injected from the source node with maximum injection. Hence, the service are suitable for small size messages (less than hundred bytes). Otherwise the other HP and LP messages, which require also the links, will experience relatively high latency depending on the size of the HP message. The LP packets are routed using a minimal adaptive routing, while the HP packets are routed using a non-minimal adaptive routing algorithm. Therefore, an additional 3-bit field, identifying the packet type, is introduced in their packet headers to classify and to determine the type of service committed to the packet. Our NoC prototypes have been also synthesized using a 180-nm CMOS standard-cell technology to evaluate the cost of implementing the combination of both services.

Keywords: Network-on-Chip, Parallel Pipeline Router Architecture, Wormhole Switching, Two-Level Priority Service.

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Authors: P. C. Boisteanu, M. G. Usturoi, Roxana Lazar, B. V. Avarvarei

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The paper is included within the framework of a complex research program, which was initiated from the hypothesis arguing on the existence of a correlation between pineal indolic and peptide hormones and the somatic development rhythm, including thus the epithalamium-epiphysis complex involvement. At birds, pineal gland contains a circadian oscillator, playing a main role in the temporal organization of the cerebral functions. The secretion of pineal indolic hormones is characterized by a high endogenous rhythmic alternation, modulated by the light/darkness (L/D) succession and by temperature as well. The research has been carried out using 100 chicken broilers - “Ross" commercial hybrid, randomly allocated in two experimental batches: Lc batch, reared under a 12L/12D lighting schedule and Lexp batch, which was photic pinealectomised through continuous exposition to light (150 lux, 24 hours, 56 days). Chemical and physical features of the meat issued from breast fillet and thighs muscles have been studied, determining the dry matter, proteins, fat, collagen, salt content and pH value, as well. Besides the variations of meat chemical composition in relation with lighting schedule, other parameters have been studied: live weight dynamics, feed intake and somatic development degree. The achieved results became significant since chickens have 7 days of age, some variations of the studied parameters being registered, revealing that the pineal gland physiologic activity, in relation with the lighting schedule, could be interpreted through the monitoring of the somatic development technological parameters, usually studied within the chicken broilers rearing aviculture practice.

Keywords: lighting schedule, physic-chemical characteristics ofmeat, pineal gland at birds.

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Authors: S. Y. Lin, C. H. Kuan, C. H. She, W. T. Wang

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In this study, ultrasonic assisted machining (UAM) technique is applied in side-surface milling experiment for glass-ceramic workpiece material. The tungsten carbide cutting-tool with diamond coating is used in conjunction with two kinds of cooling/lubrication mediums such as water-soluble (WS) cutting fluid and minimum quantity lubricant (MQL). Full factorial process parameter combinations on the milling experiments are planned to investigate the effect of process parameters on cutting performance. From the experimental results, it tries to search for the better process parameter combination which the edge-indentation and the surface roughness are acceptable. In the machining experiments, ultrasonic oscillator was used to excite a cutting-tool along the radial direction producing a very small amplitude of vibration frequency of 20KHz to assist the machining process. After processing, toolmaker microscope was used to detect the side-surface morphology, edge-indentation and cutting tool wear under different combination of cutting parameters, and analysis and discussion were also conducted for experimental results. The results show that the main leading parameters to edge-indentation of glass ceramic are cutting depth and feed rate. In order to reduce edge-indentation, it needs to use lower cutting depth and feed rate. Water-soluble cutting fluid provides a better cooling effect in the primary cutting area; it may effectively reduce the edge-indentation and improve the surface morphology of the glass ceramic. The use of ultrasonic assisted technique can effectively enhance the surface finish cleanness and reduce cutting tool wear and edge-indentation. 

Keywords: Glass-ceramic, ultrasonic assisted machining, cutting performance, edge-indentation

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Authors: Shobha Sharma, Amita Dev

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This research paper presents highly optimized barrel shifter at 22nm Hi K metal gate strained Si technology node. This barrel shifter is having a unique combination of static and dynamic body bias which gives lowest power delay product. This power delay product is compared with the same circuit at same technology node with static forward biasing at ‘supply/2’ and also with normal reverse substrate biasing and still found to be the lowest. The power delay product of this barrel sifter is .39362X10-17J and is lowered by approximately 78% to reference proposed barrel shifter at 32nm bulk CMOS technology. Power delay product of barrel shifter at 22nm Hi K Metal gate technology with normal reverse substrate bias is 2.97186933X10-17J and can be compared with this design’s PDP of .39362X10-17J. This design uses both static and dynamic substrate biasing and also has approximately 96% lower power delay product compared to only forward body biased at half of supply voltage. The NMOS model used are predictive technology models of Arizona state university and the simulations to be carried out using HSPICE simulator.

Keywords: Dynamic body biasing, highly optimized barrel shifter, PDP, Static body biasing.

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Authors: K. Machida, H. Yamada

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Displacement measurement was conducted on compact normal and shear specimens made of acrylic homogeneous material subjected to mixed-mode loading by digital image correlation. The intelligent hybrid method proposed by Nishioka et al. was applied to the stress-strain analysis near the crack tip. The accuracy of stress-intensity factor at the free surface was discussed from the viewpoint of both the experiment and 3-D finite element analysis. The surface images before and after deformation were taken by a CMOS camera, and we developed the system which enabled the real time stress analysis based on digital image correlation and inverse problem analysis. The great portion of processing time of this system was spent on displacement analysis. Then, we tried improvement in speed of this portion. In the case of cracked body, it is also possible to evaluate fracture mechanics parameters such as the J integral, the strain energy release rate, and the stress-intensity factor of mixed-mode. The 9-points elliptic paraboloid approximation could not analyze the displacement of submicron order with high accuracy. The analysis accuracy of displacement was improved considerably by introducing the Newton-Raphson method in consideration of deformation of a subset. The stress-intensity factor was evaluated with high accuracy of less than 1% of the error.

Keywords: Digital image correlation, mixed mode, Newton-Raphson method, stress intensity factor.

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Authors: R. M. Siddiqui, D. Z. Moghaddam, T. R. Turlapati, S. H. Khan, I. Ul Ahad

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Quality of 2D and 3D cross-sectional images produce by Computed Tomography primarily depend upon the degree of precision of primary and secondary X-Ray intensity detection. Traditional method of primary intensity detection is apt to errors. Recently the X-Ray intensity measurement system along with smart X-Ray sensors is developed by our group which is able to detect primary X-Ray intensity unerringly. In this study a new smart X-Ray sensor is developed using Light-to-Frequency converter TSL230 from Texas Instruments which has numerous advantages in terms of noiseless data acquisition and transmission. TSL230 construction is based on a silicon photodiode which converts incoming X-Ray radiation into the proportional current signal. A current to frequency converter is attached to this photodiode on a single monolithic CMOS integrated circuit which provides proportional frequency count to incoming current signal in the form of the pulse train. The frequency count is delivered to the center of PICDEM FS USB board with PIC18F4550 microcontroller mounted on it. With highly compact electronic hardware, this Demo Board efficiently read the smart sensor output data. The frequency output approaches overcome nonlinear behavior of sensors with analog output thus un-attenuated X-Ray intensities could be measured precisely and better normalization could be acquired in order to attain high resolution.

Keywords: Computed tomography, detector technology, X-Ray intensity measurement

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Authors: Faizal A. Samman, Thomas Hollstein, Manfred Glesner

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This paper presents design trade-off and performance impacts of the amount of pipeline phase of control path signals in a wormhole-switched network-on-chip (NoC). The numbers of the pipeline phase of the control path vary between two- and one-cycle pipeline phase. The control paths consist of the routing request paths for output selection and the arbitration paths for input selection. Data communications between on-chip routers are implemented synchronously and for quality of service, the inter-router data transports are controlled by using a link-level congestion control to avoid lose of data because of an overflow. The trade-off between the area (logic cell area) and the performance (bandwidth gain) of two proposed NoC router microarchitectures are presented in this paper. The performance evaluation is made by using a traffic scenario with different number of workloads under 2D mesh NoC topology using a static routing algorithm. By using a 130-nm CMOS standard-cell technology, our NoC routers can be clocked at 1 GHz, resulting in a high speed network link and high router bandwidth capacity of about 320 Gbit/s. Based on our experiments, the amount of control path pipeline stages gives more significant impact on the NoC performance than the impact on the logic area of the NoC router.

Keywords: Network-on-Chip, Synchronous Parallel Pipeline, Router Architecture, Wormhole Switching

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Authors: Yi-Feng Su, Chia-Tseng Chen, Hsueh-Lung Liao

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The objective of this research is to develop an advanced driver assistance system characterized with the functions of lane departure warning (LDW), forward collision warning (FCW) and adaptive front-lighting system (AFS). The system is mainly configured a CCD/CMOS camera to acquire the images of roadway ahead in association with the analysis made by an image-processing unit concerning the lane ahead and the preceding vehicles. The input image captured by a camera is used to recognize the lane and the preceding vehicle positions by image detection and DROI (Dynamic Range of Interesting) algorithms. Therefore, the system is able to issue real-time auditory and visual outputs of warning when a driver is departing the lane or driving too close to approach the preceding vehicle unwittingly so that the danger could be prevented from occurring. During the nighttime, in addition to the foregoing warning functions, the system is able to control the bending light of headlamp to provide an immediate light illumination when making a turn at a curved lane and adjust the level automatically to reduce the lighting interference against the oncoming vehicles driving in the opposite direction by the curvature of lane and the vanishing point estimations. The experimental results show that the integrated vehicle image system is robust to most environments such as the lane detection and preceding vehicle detection average accuracy performances are both above 90 %.

Keywords: Lane mark detection, lane departure warning (LDW), dynamic range of interesting (DROI), forward collision warning (FCW), adaptive front-lighting system (AFS).

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Authors: Hikari Ryu, Yuki Fukuda, Kento Oishi, Chiharu Igarashi, Shogo Kiryu

Abstract:

Recently, wireless power transfer has been developed in various fields. Magnetic coupling is popular for feeding power at a relatively short distance and at a lower frequency. Electro-magnetic wave coupling at a high frequency is used for long-distance power transfer. The wireless power transfer has attracted attention in e-textile fields. Rigid batteries are required for many body-worn electric systems at the present time. The technology enables such batteries to be removed from the systems. Coils with a high Q factor are required in the magnetic-coupling power transfer. Antennas with low return loss are needed for the electro-magnetic coupling. Litz wire is so flexible to fabricate coils and antennas sewn on fabric and has low resistivity. In this study, the electric characteristics of some coils and antennas fabricated with the Litz wire by using two sewing techniques are investigated. As examples, a coil and an antenna are described. Both were fabricated with 330/0.04 mm Litz wire. The coil was a planar coil with a square shape. The outer side was 150 mm, the number of turns was 15, and the pitch interval between each turn was 5 mm. The Litz wire of the coil was overstitched with a sewing machine. The coil was fabricated as a receiver coil for a magnetic coupled wireless power transfer. The Q factor was 200 at a frequency of 800 kHz. A wireless power system was constructed by using the coil. A power oscillator was used in the system. The resonant frequency of the circuit was set to 123 kHz, where the switching loss of power Field Effect Transistor (FET) was was small. The power efficiencies were 0.44-0.99, depending on the distance between the transmitter and receiver coils. As an example of an antenna with a sewing technique, a fractal pattern antenna was stitched on a 500 mm x 500 mm fabric by using a needle punch method. The pattern was the 2nd-oder Vicsec fractal. The return loss of the antenna was -28 dB at a frequency of 144 MHz.

Keywords: E-textile, flexible coils, flexible antennas, Litz wire, wireless power transfer.

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Authors: Padmanabhan Balasubramanian, Ryuta Arisaka

Abstract:

Factoring Boolean functions is one of the basic operations in algorithmic logic synthesis. A novel algebraic factorization heuristic for single-output combinatorial logic functions is presented in this paper and is developed based on the set theory paradigm. The impact of factoring is analyzed mainly from a low power design perspective for standard cell based digital designs in this paper. The physical implementation of a number of MCNC/IWLS combinational benchmark functions and sub-functions are compared before and after factoring, based on a simple technology mapping procedure utilizing only standard gate primitives (readily available as standard cells in a technology library) and not cells corresponding to optimized complex logic. The power results were obtained at the gate-level by means of an industry-standard power analysis tool from Synopsys, targeting a 130nm (0.13μm) UMC CMOS library, for the typical case. The wire-loads were inserted automatically and the simulations were performed with maximum input activity. The gate-level simulations demonstrate the advantage of the proposed factoring technique in comparison with other existing methods from a low power perspective, for arbitrary examples. Though the benchmarks experimentation reports mixed results, the mean savings in total power and dynamic power for the factored solution over a non-factored solution were 6.11% and 5.85% respectively. In terms of leakage power, the average savings for the factored forms was significant to the tune of 23.48%. The factored solution is expected to better its non-factored counterpart in terms of the power-delay product as it is well-known that factoring, in general, yields a delay-efficient multi-level solution.

Keywords: Factorization, Set theory, Logic function, Standardcell based design, Low power.

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Authors: Arafa A. Alholaisi, Jamal H. Madani, M. A. Alvi

Abstract:

The radial form of nuclear matter distribution, charge and the shape of nuclei are essential properties of nuclei, and hence, are of great attention for several areas of research in nuclear physics. More than last three decades have witnessed a range of experimental means employing leptonic probes (such as muons, electrons etc.) for exploring nuclear charge distributions, whereas the hadronic probes (for example alpha particles, protons, etc.) have been used to investigate the nuclear matter distributions. In this paper, p-^9,11Li elastic scattering differential cross sections in the energy range  to  MeV have been studied by means of Coulomb modified Glauber scattering formalism. By applying the semi-phenomenological Bhagwat-Gambhir-Patil [BGP] nuclear density for loosely bound neutron rich ¹¹Li nucleus, the estimated matter radius is found to be 3.446 fm which is quite large as compared to so known experimental value 3.12 fm. The results of microscopic optical model based calculation by applying Bethe-Brueckner–Hartree–Fock formalism (BHF) have also been compared. It should be noted that in most of phenomenological density model used to reproduce the p-¹¹Li differential elastic scattering cross sections data, the calculated matter radius lies between 2.964 and 3.55 fm. The calculated results with phenomenological BGP model density and with nucleon density calculated in the relativistic mean-field (RMF) reproduces p-⁹Li and p-¹¹Li experimental data quite nicely as compared to Gaussian- Gaussian or Gaussian-Oscillator densities at all energies under consideration. In the approach described here, no free/adjustable parameter has been employed to reproduce the elastic scattering data as against the well-known optical model based studies that involve at least four to six adjustable parameters to match the experimental data. Calculated reaction cross sections σ_R for p-¹¹Li at these energies are quite large as compared to estimated values reported by earlier works though so far no experimental studies have been performed to measure it.

Keywords: Bhagwat-Gambhir-Patil density, coulomb modified Glauber model, halo nucleus, optical limit approximation.

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