Search results for: 3D microfluidic chip

Authors: M. N. Islam, B. Boswell, Y. R. Ginting

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The influence of canned cycles and cutting parameters on hole quality in cryogenic drilling has been investigated experimentally and analytically. A three-level, three-parameter experiment was conducted by using the design-of-experiment methodology. The three levels of independent input parameters were the following: for canned cycles—a chip-breaking canned cycle (G73), a spot drilling canned cycle (G81), and a deep hole canned cycle (G83); for feed rates—0.2, 0.3, and 0.4 mm/rev; and for cutting speeds—60, 75, and 100 m/min. The selected work and tool materials were aluminum 6061-6T and high-speed steel (HSS), respectively. For cryogenic cooling, liquid nitrogen (LN2) was used and was applied externally. The measured output parameters were the three widely used quality characteristics of drilled holes—diameter error, circularity, and surface roughness. Pareto ANOVA was applied for analyzing the results. The findings revealed that the canned cycle has a significant effect on diameter error (contribution ratio 44.09%) and small effects on circularity and surface finish (contribution ratio 7.25% and 6.60%, respectively). The best results for the dimensional accuracy and surface roughness were achieved by G81. G73 produced the best circularity results; however, for dimensional accuracy, it was the worst level.

Keywords: Circularity, diameter error, drilling canned cycle, Pareto ANOVA, surface roughness.

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Authors: A. Muthuramalingam, S. Himavathi, E. Srinivasan

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.Hardware realization of a Neural Network (NN), to a large extent depends on the efficient implementation of a single neuron. FPGA-based reconfigurable computing architectures are suitable for hardware implementation of neural networks. FPGA realization of ANNs with a large number of neurons is still a challenging task. This paper discusses the issues involved in implementation of a multi-input neuron with linear/nonlinear excitation functions using FPGA. Implementation method with resource/speed tradeoff is proposed to handle signed decimal numbers. The VHDL coding developed is tested using Xilinx XC V50hq240 Chip. To improve the speed of operation a lookup table method is used. The problems involved in using a lookup table (LUT) for a nonlinear function is discussed. The percentage saving in resource and the improvement in speed with an LUT for a neuron is reported. An attempt is also made to derive a generalized formula for a multi-input neuron that facilitates to estimate approximately the total resource requirement and speed achievable for a given multilayer neural network. This facilitates the designer to choose the FPGA capacity for a given application. Using the proposed method of implementation a neural network based application, namely, a Space vector modulator for a vector-controlled drive is presented

Keywords: FPGA implementation, multi-input neuron, neural network, nn based space vector modulator.

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Authors: Hanaa T. El-Madany, Faten H. Fahmy, Ninet M. A. El-Rahman, Hassen T. Dorrah

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Designing and implementing intelligent systems has become a crucial factor for the innovation and development of better products of space technologies. A neural network is a parallel system, capable of resolving paradigms that linear computing cannot. Field programmable gate array (FPGA) is a digital device that owns reprogrammable properties and robust flexibility. For the neural network based instrument prototype in real time application, conventional specific VLSI neural chip design suffers the limitation in time and cost. With low precision artificial neural network design, FPGAs have higher speed and smaller size for real time application than the VLSI and DSP chips. So, many researchers have made great efforts on the realization of neural network (NN) using FPGA technique. In this paper, an introduction of ANN and FPGA technique are briefly shown. Also, Hardware Description Language (VHDL) code has been proposed to implement ANNs as well as to present simulation results with floating point arithmetic. Synthesis results for ANN controller are developed using Precision RTL. Proposed VHDL implementation creates a flexible, fast method and high degree of parallelism for implementing ANN. The implementation of multi-layer NN using lookup table LUT reduces the resource utilization for implementation and time for execution.

Keywords: Spacecraft, neural network, FPGA, VHDL.

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Authors: D. Geringswald, B. Hintze

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The miniaturization of circuits is advancing. During chip manufacturing, structures are filled for example by metal organic chemical vapor deposition (MOCVD). Since this process reaches its limits in case of very high aspect ratios, the use of alternatives such as the atomic layer deposition (ALD) is possible, requiring the extension of existing coating systems. However, it is an unsolved question to what extent MOCVD can achieve results similar as an ALD process. In this context, this work addresses the characterization of a metal organic vapor deposition of titanium nitride. Based on the current state of the art, the film properties coating thickness, sheet resistance, resistivity, stress and chemical composition are considered. The used setting parameters are temperature, plasma gas ratio, plasma power, plasma treatment time, deposition time, deposition pressure, number of cycles and TDMAT flow. The derived process instructions for unstructured wafers and inside a structure with high aspect ratio include lowering the process temperature and increasing the number of cycles, the deposition and the plasma treatment time as well as the plasma gas ratio of hydrogen to nitrogen (H₂:N₂). In contrast to the current process configuration, the deposited titanium nitride (TiN) layer is more uniform inside the entire test structure. Consequently, this paper provides approaches to employ the MOCVD for structures with increasing aspect ratios.

Keywords: ALD, high aspect ratio, PE-MOCVD, TiN.

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Authors: Ameni Mokni , Hatem Mhiri , Georges Le Palec , Philippe Bournot

Abstract:

In mechanical and environmental engineering, mixed convection is a frequently encountered thermal fluid phenomenon which exists in atmospheric environment, urban canopy flows, ocean currents, gas turbines, heat exchangers, and computer chip cooling systems etc... . This paper deals with a numerical investigation of mixed convection in a vertical heated channel. This flow results from the mixing of the up-going fluid along walls of the channel with the one issued from a flat nozzle located in its entry section. The fluiddynamic and heat-transfer characteristics of vented vertical channels are investigated for constant heat-flux boundary conditions, a Rayleigh number equal to 2.57 1010, for two jet Reynolds number Re=3 103 and 2104 and the aspect ratio in the 8-20 range. The system of governing equations is solved with a finite volumes method and an implicit scheme. The obtained results show that the turbulence and the jet-wall interaction activate the heat transfer, as does the drive of ambient air by the jet. For low Reynolds number Re=3 103, the increase of the aspect Ratio enhances the heat transfer of about 3%, however; for Re=2 104, the heat transfer enhancement is of about 12%. The numerical velocity, pressure and temperature fields are post-processed to compute the quantities of engineering interest such as the induced mass flow rate, and average Nusselt number, in terms of Rayleigh, Reynolds numbers and dimensionless geometric parameters are presented.

Keywords: Aspect Ratio, Channel, Jet, Mixed convection

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Authors: B. Arzhanov, A. Correia, P. Delgado, J. Meireles

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Due to the higher power loss levels in electronic components, the thermal design of PCBs (Printed Circuit Boards) of an assembled device becomes one of the most important quality factors in electronics. Nonetheless, some of leading causes of the microelectronic component failures are due to higher temperatures, the leakages or thermal-mechanical stress, which is a concern, is the reliability of microelectronic packages. This article presents an experimental approach to measure the junction temperature of exposed pad packages. The implemented solution is in a prototype phase, using a temperature-sensitive parameter (TSP) to measure temperature directly on the die, validating the numeric results provided by the Mechanical APDL (Ansys Parametric Design Language) under same conditions. The physical device-under-test is composed by a Thermal Test Chip (TTC-1002) and assembly in a QFN cavity, soldered to a test-board according to JEDEC Standards. Monitoring the voltage drop across a forward-biased diode, is an indirectly method but accurate to obtain the junction temperature of QFN component with an applied power range between 0,3W to 1.5W. The temperature distributions on the PCB test-board and QFN cavity surface were monitored by an infra-red thermal camera (Goby-384) controlled and images processed by the Xeneth software. The article provides a set-up to monitorize in real-time the junction temperature of ICs, namely devices with the exposed pad package (i.e. QFN). Presenting the PCB layout parameters that the designer should use to improve thermal performance, and evaluate the impact of voids in solder interface in the device junction temperature.

Keywords: Quad Flat No-Lead packages, exposed pads, junction temperature, thermal management, measurements.

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Authors: F. A. Gdhaidh, K. Hussain, H. S. Qi

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A numerical study of natural convection heat transfer in water filled cavity has been examined in 3-Dfor single phase liquid cooling system by using an array of parallel plate fins mounted to one wall of a cavity. The heat generated by a heat source represents a computer CPU with dimensions of 37.5∗37.5mm mounted on substrate. A cold plate is used as a heat sink installed on the opposite vertical end of the enclosure. The air flow inside the computer case is created by an exhaust fan. A turbulent air flow is assumed and k-ε model is applied. The fins are installed on the substrate to enhance the heat transfer. The applied power energy range used is between 15 - 40W. In order to determine the thermal behaviour of the cooling system, the effect of the heat input and the number of the parallel plate fins are investigated. The results illustrate that as the fin number increases the maximum heat source temperature decreases. However, when the fin number increases to critical value the temperature start to increase due to the fins are too closely spaced and that cause the obstruction of water flow. The introduction of parallel plate fins reduces the maximum heat source temperature by 10% compared to the case without fins. The cooling system maintains the maximum chip temperature at 64.68°C when the heat input was at 40W that is much lower than the recommended computer chips limit temperature of no more than 85°C and hence the performance of the CPU is enhanced.

Keywords: Chips limit temperature, closed enclosure, natural convection, parallel plate, single phase liquid.

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Authors: A. Almaneea, N. Kapur, J. L. Summers, H. M. Thompson

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Meeting the growth in demand for digital services such as social media, telecommunications, and business and cloud services requires large scale data centres, which has led to an increase in their end use energy demand. Generally, over 30% of data centre power is consumed by the necessary cooling overhead. Thus energy can be reduced by improving the cooling efficiency. Air and liquid can both be used as cooling media for the data centre. Traditional data centre cooling systems use air, however liquid is recognised as a promising method that can handle the more densely packed data centres. Liquid cooling can be classified into three methods; rack heat exchanger, on-chip heat exchanger and full immersion of the microelectronics. This study quantifies the improvements of heat transfer specifically for the case of immersed microelectronics by varying the CPU and heat sink location. Immersion of the server is achieved by filling the gap between the microelectronics and a water jacket with a dielectric liquid which convects the heat from the CPU to the water jacket on the opposite side. Heat transfer is governed by two physical mechanisms, which is natural convection for the fixed enclosure filled with dielectric liquid and forced convection for the water that is pumped through the water jacket. The model in this study is validated with published numerical and experimental work and shows good agreement with previous work. The results show that the heat transfer performance and Nusselt number (Nu) is improved by 89% by placing the CPU and heat sink on the bottom of the microelectronics enclosure.

Keywords: CPU location, data centre cooling, heat sink in enclosures, Immersed microelectronics, turbulent natural convection in enclosures.

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Authors: Satish Kumar, Arun Kumar Gupta, Pankaj Chandna

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In the modern manufacturing systems, the use of thermal cutting techniques using oxyfuel, plasma and laser have become indispensable for the shape forming of high quality complex components; however, the conventional chip removal production techniques still have its widespread space in the manufacturing industry. Both these types of machining operations require the positioning of end effector tool at the edge where the cutting process commences. This repositioning of the cutting tool in every machining operation is repeated several times and is termed as non-productive time or airtime motion. Minimization of this non-productive machining time plays an important role in mass production with high speed machining. As, the tool moves from one region to the other by rapid movement and visits a meticulous region once in the whole operation, hence the non-productive time can be minimized by synchronizing the tool movements. In this work, this problem is being formulated as a general travelling salesman problem (TSP) and a genetic algorithm approach has been applied to solve the same. For improving the efficiency of the algorithm, the GA has been hybridized with a noble special heuristic and simulating annealing (SA). In the present work a novel heuristic in the combination of GA has been developed for synchronization of toolpath movements during repositioning of the tool. A comparative analysis of new Meta heuristic techniques with simple genetic algorithm has been performed. The proposed metaheuristic approach shows better performance than simple genetic algorithm for minimization of nonproductive toolpath length. Also, the results obtained with the help of hybrid simulated annealing genetic algorithm (HSAGA) are also found better than the results using simple genetic algorithm only.

Keywords: Non-productive time, Airtime, 2.5 D milling, Laser cutting, Metaheuristic, Genetic Algorithm, Simulated Annealing.

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Authors: Ruth Lorivi, Jianzheng Li, John J. Ambuchi, Kaiwen Deng

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Nitrogen removal from wastewater is accomplished by nitrification and denitrification processes. Successful denitrification requires carbon, therefore, if placed after biochemical oxygen demand (BOD) and nitrification process, a carbon source has to be re-introduced into the water. To avoid adding a carbon source, denitrification is usually placed before BOD and nitrification processes. This process however involves recycling the nitrified effluent. In this study wood chips were used as internal carbon source which enabled placement of denitrification after BOD and nitrification process without effluent recycling. To investigate the efficiency of a wood packed aerobic-anaerobic baffled reactor on carbon and nutrients removal from domestic wastewater, a three compartment baffled reactor was presented. Each of the three compartments was packed with 329 g wood chips 1x1cm acting as an internal carbon source for denitrification. The proposed mode of operation was aerobic-anoxic-anaerobic (OAA) with no effluent recycling. The operating temperature, hydraulic retention time (HRT), dissolved oxygen (DO) and pH were 24 ± 2 ℃, 24 h, less than 4 mg/L and 7 ± 1 respectively. The removal efficiencies of chemical oxygen demand (COD), ammonia nitrogen (NH₄⁺-N) and total nitrogen (TN) attained was 99, 87 and 83% respectively. TN removal rate was limited by nitrification as 97% of ammonia converted into nitrate and nitrite was denitrified. These results show that application of wood chips in wastewater treatment processes is an efficient internal carbon source. 

Keywords: Aerobic-anaerobic baffled reactor, denitrification, nitrification, wood chip.

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Authors: Gaurav D. Sonawane, Vikas G. Sargade

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The present investigation is a study of the effect of advanced Physical Vapor Deposition (PVD) coatings on cutting temperature residual stresses and surface roughness during Duplex Stainless Steel (DSS) 2205 turning. Austenite stabilizers like nickel, manganese, and molybdenum reduced the cost of DSS. Surface Integrity (SI) plays an important role in determining corrosion resistance and fatigue life. Resistance to various types of corrosion makes DSS suitable for applications with critical environments like Heat exchangers, Desalination plants, Seawater pipes and Marine components. However, lower thermal conductivity, poor chip control and non-uniform tool wear make DSS very difficult to machine. Cemented carbide tools (M grade) were used to turn DSS in a dry environment. AlTiN and AlTiCrN coatings were deposited using advanced PVD High Pulse Impulse Magnetron Sputtering (HiPIMS) technique. Experiments were conducted with cutting speed of 100 m/min, 140 m/min and 180 m/min. A constant feed and depth of cut of 0.18 mm/rev and 0.8 mm were used, respectively. AlTiCrN coated tools followed by AlTiN coated tools outperformed uncoated tools due to properties like lower thermal conductivity, higher adhesion strength and hardness. Residual stresses were found to be compressive for all the tools used for dry turning, increasing the fatigue life of the machined component. Higher cutting temperatures were observed for coated tools due to its lower thermal conductivity, which results in very less tool wear than uncoated tools. Surface roughness with uncoated tools was found to be three times higher than coated tools due to lower coefficient of friction of coating used.

Keywords: Cutting temperatures, DSS2205, dry turning, HiPIMS, surface integrity.

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Authors: B. Arzhanov, A. Correia, P. Delgado, J. Meireles

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Quad Flat No-Lead (QFN) packages have become very popular for turners, converters and audio amplifiers, among others applications, needing efficient power dissipation in small footprints. Since semiconductor junction temperature (T_J) is a critical parameter in the product quality. And to ensure that die temperature does not exceed the maximum allowable T_J, a thermal analysis conducted in an earlier development phase is essential to avoid repeated re-designs process with huge losses in cost and time. A simulation tool capable to estimate die temperature of components with QFN package was developed. Allow establish a non-empirical way to define an acceptance criterion for amount of voids in solder interface between its exposed pad and Printed Circuit Board (PCB) to be applied during industrialization process, and evaluate the impact of PCB designs parameters. Targeting PCB layout designer as an end user for the application, a user-friendly interface (GUI) was implemented allowing user to introduce design parameters in a convenient and secure way and hiding all the complexity of finite element simulation process. This cost effective tool turns transparent a simulating process and provides useful outputs after acceptable time, which can be adopted by PCB designers, preventing potential risks during the design stage and make product economically efficient by not oversizing it. This article gathers relevant information related to the design and implementation of the developed tool, presenting a parametric study conducted with it. The simulation tool was experimentally validated using a Thermal-Test-Chip (TTC) in a QFN open-cavity, in order to measure junction temperature (T_J) directly on the die under controlled and knowing conditions. Providing a short overview about standard thermal solutions and impacts in exposed pad packages (i.e. QFN), accurately describe the methods and techniques that the system designer should use to achieve optimum thermal performance, and demonstrate the effect of system-level constraints on the thermal performance of the design.

Keywords: Quad Flat No-Lead packages, exposed pads, junction temperature, thermal management and measurements.

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