Search results for: Input Power Factor
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 5364

Search results for: Input Power Factor

5214 A Very High Speed, High Resolution Current Comparator Design

Authors: Neeraj K. Chasta

Abstract:

This paper presents an idea for analog current comparison which compares input signal and reference currents with high speed and accuracy. Proposed circuit utilizes amplification properties of common gate configuration, where voltage variations of input current are amplified and a compared output voltage is developed. Cascaded inverter stages are used to generate final CMOS compatible output voltage. Power consumption of circuit can be controlled by the applied gate bias voltage. The comparator is designed and studied at 180nm CMOS process technology for a supply voltage of 3V.

Keywords: Current Mode, Comparator, High Resolution, High Speed.

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5213 Power Allocation in User-Centric Cell-Free Massive MIMO Systems with Limited Fronthaul Capacity

Authors: Siminfar Samakoush Galougah

Abstract:

In this paper, we study two power allocation problems for an uplink user-centric (UC) cell-free massive multiple-input multiple-output (CF-mMIMO) system. Besides, we assume each access point (AP) is connected to a central processing unit (CPU) via fronthaul link with limited capacity. To efficiently use the fronthaul capacity, two strategies for transmitting signals from APs to the CPU are employed; namely: compress-forward-estimate (CFE), estimate-compress-forward (ECF). The capacity of the aforementioned strategies in user-centric CF-mMIMO are drived. Then, we solved the two power allocation problems with minimum Spectral Efficiency (SE) and sum-SE maximization objectives for ECF and CFE strategies.

Keywords: Cell-free massive MIMO, limited capacity fronthaul, spectral efficiency, power allocation problem.

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5212 Optimal Planning of Dispatchable Distributed Generators for Power Loss Reduction in Unbalanced Distribution Networks

Authors: Mahmoud M. Othman, Y. G. Hegazy, A. Y. Abdelaziz

Abstract:

This paper proposes a novel heuristic algorithm that aims to determine the best size and location of distributed generators in unbalanced distribution networks. The proposed heuristic algorithm can deal with the planning cases where power loss is to be optimized without violating the system practical constraints. The distributed generation units in the proposed algorithm is modeled as voltage controlled node with the flexibility to be converted to constant power factor node in case of reactive power limit violation. The proposed algorithm is implemented in MATLAB and tested on the IEEE 37 -node feeder. The results obtained show the effectiveness of the proposed algorithm. 

Keywords: Distributed generation, heuristic approach, Optimization, planning.

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5211 Analysis of Nonlinear Pulse Propagation Characteristics in Semiconductor Optical Amplifier for Different Input Pulse Shapes

Authors: Suchi Barua, Narottam Das, Sven Nordholm, Mohammad Razaghi

Abstract:

This paper presents nonlinear pulse propagation characteristics for different input optical pulse shapes with various input pulse energy levels in semiconductor optical amplifiers. For simulation of nonlinear pulse propagation, finite-difference beam propagation method is used to solve the nonlinear Schrödinger equation. In this equation, gain spectrum dynamics, gain saturation are taken into account which depends on carrier depletion, carrier heating, spectral-hole burning, group velocity dispersion, self-phase modulation and two photon absorption. From this analysis, we obtained the output waveforms and spectra for different input pulse shapes as well as for different input energies. It shows clearly that the peak position of the output waveforms are shifted toward the leading edge which due to the gain saturation of the SOA for higher input pulse energies. We also analyzed and compared the normalized difference of full-width at half maximum for different input pulse shapes in the SOA.

Keywords: Finite-difference beam propagation method, pulse shape, pulse propagation, semiconductor optical amplifier.

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5210 Neural Network Optimal Power Flow(NN-OPF) based on IPSO with Developed Load Cluster Method

Authors: Mat Syai'in, Adi Soeprijanto

Abstract:

An Optimal Power Flow based on Improved Particle Swarm Optimization (OPF-IPSO) with Generator Capability Curve Constraint is used by NN-OPF as a reference to get pattern of generator scheduling. There are three stages in Designing NN-OPF. The first stage is design of OPF-IPSO with generator capability curve constraint. The second stage is clustering load to specific range and calculating its index. The third stage is training NN-OPF using constructive back propagation method. In training process total load and load index used as input, and pattern of generator scheduling used as output. Data used in this paper is power system of Java-Bali. Software used in this simulation is MATLAB.

Keywords: Optimal Power Flow, Generator Capability Curve, Improved Particle Swarm Optimization, Neural Network

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5209 Star-Hexagon Transformer Supported UPQC

Authors: Yash Pal, A.Swarup, Bhim Singh

Abstract:

A new topology of unified power quality conditioner (UPQC) is proposed for different power quality (PQ) improvement in a three-phase four-wire (3P-4W) distribution system. For neutral current mitigation, a star-hexagon transformer is connected in shunt near the load along with three-leg voltage source inverters (VSIs) based UPQC. For the mitigation of source neutral current, the uses of passive elements are advantageous over the active compensation due to ruggedness and less complexity of control. In addition to this, by connecting a star-hexagon transformer for neutral current mitigation the over all rating of the UPQC is reduced. The performance of the proposed topology of 3P-4W UPQC is evaluated for power-factor correction, load balancing, neutral current mitigation and mitigation of voltage and currents harmonics. A simple control algorithm based on Unit Vector Template (UVT) technique is used as a control strategy of UPQC for mitigation of different PQ problems. In this control scheme, the current/voltage control is applied over the fundamental supply currents/voltages instead of fast changing APFs currents/voltages, thereby reducing the computational delay. Moreover, no extra control is required for neutral source current compensation; hence the numbers of current sensors are reduced. The performance of the proposed topology of UPQC is analyzed through simulations results using MATLAB software with its Simulink and Power System Block set toolboxes.

Keywords: Power-factor correction, Load balancing, UPQC, Voltage and Current harmonics, Neutral current mitigation, Starhexagon transformer.

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5208 Optimal Planning of Voltage Controlled Distributed Generators for Power Loss Reduction in Unbalanced Distribution Systems

Authors: Mahmoud M. Othman, Yasser G. Hegazy

Abstract:

This paper proposes a novel heuristic algorithm that aims to determine the best size and location of distributed generators in unbalanced distribution networks. The proposed heuristic algorithm can deal with the planning cases where power loss is to be optimized without violating the system practical constraints. The distributed generation units in the proposed algorithm is modeled as voltage controlled node with the flexibility to be converted to constant power factor node in case of reactive power limit violation. The proposed algorithm is implemented in MATLAB and tested on the IEEE 37 -node feeder. The results obtained show the effectiveness of the proposed algorithm.

Keywords: Distributed generation, heuristic approach, Optimization, planning.

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5207 An Improved Cooperative Communication Scheme for IoT System

Authors: Eui-Hak Lee, Jae-Hyun Ro, Hyoung-Kyu Song

Abstract:

In internet of things (IoT) system, the communication scheme with reliability and low power is required to connect a terminal. Cooperative communication can achieve reliability and lower power than multiple-input multiple-output (MIMO) system. Cooperative communication increases the reliability with low power, but decreases a throughput. It has a weak point that the communication throughput is decreased. In this paper, a novel scheme is proposed to increase the communication throughput. The novel scheme is a transmission structure that increases transmission rate. A decoding scheme according to the novel transmission structure is proposed. Simulation results show that the proposed scheme increases the throughput without bit error rate (BER) performance degradation.

Keywords: Cooperative communication, IoT, STBC, Transmission rate.

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5206 Experimental Investigation and Optimization of Nanoparticle Mass Concentration and Heat Input of Loop Heat Pipe

Authors: P. Gunnasegaran, M. Z. Abdullah, M. Z. Yusoff, Nur Irmawati

Abstract:

This study presents experimental and optimization of nanoparticle mass concentration and heat input based on the total thermal resistance (Rth) of loop heat pipe (LHP), employed for PCCPU cooling. In this study, silica nanoparticles (SiO2) in water with particle mass concentration ranged from 0% (pure water) to 1% is considered as the working fluid within the LHP. The experimental design and optimization is accomplished by the design of experimental tool, Response Surface Methodology (RSM). The results show that the nanoparticle mass concentration and the heat input have significant effect on the Rth of LHP. For a given heat input, the Rth is found to decrease with the increase of the nanoparticle mass concentration up to 0.5% and increased thereafter. It is also found that the Rth is decreased when the heat input is increased from 20W to 60W. The results are optimized with the objective of minimizing the Rth, using Design-Expert software, and the optimized nanoparticle mass concentration and heat input are 0.48% and 59.97W, respectively, the minimum thermal resistance being 2.66 (ºC/W).

Keywords: Loop heat pipe, nanofluid, optimization, thermal resistance.

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5205 A ZVS Flyback DC-DC Converter using Multilayered Coreless Printed-Circuit Board(PCB) Step-down Power Transformer

Authors: Hari Babu Kotte, Radhika Ambatipudi, Dr. Kent Bertilsson

Abstract:

The experimental and theoretical results of a ZVS (Zero Voltage Switching) isolated flyback DC-DC converter using multilayered coreless PCB step down 2:1 transformer are presented. The performance characteristics of the transformer are shown which are useful for the parameters extraction. The measured energy efficiency of the transformer is found to be more than 94% with the sinusoidal input voltage excitation. The designed flyback converter has been tested successfully upto the output power level of 10W, with a switching frequency in the range of 2.7MHz-4.3MHz. The input voltage of the converter is varied from 25V-40V DC. Frequency modulation technique is employed by maintaining constant off time to regulate the output voltage of the converter. The energy efficiency of the isolated flyback converter circuit under ZVS condition in the MHz frequency region is found to be approximately in the range of 72-84%. This paper gives the comparative results in terms of the energy efficiency of the hard switched and soft switched flyback converter in the MHz frequency region.

Keywords: Coreless PCB step down transformer, DC-DCconverter, Flyback, Hard Switched Converter, MHz frequencyregion, Multilayered PCB transformer, Zero Voltage Switching

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5204 Voltage Problem Location Classification Using Performance of Least Squares Support Vector Machine LS-SVM and Learning Vector Quantization LVQ

Authors: Khaled Abduesslam. M, Mohammed Ali, Basher H Alsdai, Muhammad Nizam, Inayati

Abstract:

This paper presents the voltage problem location classification using performance of Least Squares Support Vector Machine (LS-SVM) and Learning Vector Quantization (LVQ) in electrical power system for proper voltage problem location implemented by IEEE 39 bus New- England. The data was collected from the time domain simulation by using Power System Analysis Toolbox (PSAT). Outputs from simulation data such as voltage, phase angle, real power and reactive power were taken as input to estimate voltage stability at particular buses based on Power Transfer Stability Index (PTSI).The simulation data was carried out on the IEEE 39 bus test system by considering load bus increased on the system. To verify of the proposed LS-SVM its performance was compared to Learning Vector Quantization (LVQ). The results showed that LS-SVM is faster and better as compared to LVQ. The results also demonstrated that the LS-SVM was estimated by 0% misclassification whereas LVQ had 7.69% misclassification.

Keywords: IEEE 39 bus, Least Squares Support Vector Machine, Learning Vector Quantization, Voltage Collapse.

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5203 Harmonic Analysis and Performance Improvement of a Wind Energy Conversions System with Double Output Induction Generator

Authors: M. Sedighizadeh, A. Rezazadeh

Abstract:

Wind turbines with double output induction generators can operate at variable speed permitting conversion efficiency maximization over a wide range of wind velocities. This paper presents the performance analysis of a wind driven double output induction generator (DOIG) operating at varying shafts speed. A periodic transient state analysis of DOIG equipped with two converters is carried out using a hybrid induction machine model. This paper simulates the harmonic content of waveforms in various points of drive at different speeds, based on the hybrid model (dqabc). Then the sinusoidal and trapezoidal pulse-width–modulation control techniques are used in order to improve the power factor of the machine and to weaken the injected low order harmonics to the supply. Based on the frequency spectrum, total harmonics distortion, distortion factor and power factor. Finally advantages of sinusoidal and trapezoidal pulse width modulation techniques are compared.

Keywords: DOIG, Harmonic Analysis, Wind.

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5202 Technology Identification, Evaluation and Selection Methodology for Industrial Process Water and Waste Water Treatment Plant of 3x150 MWe Tufanbeyli Lignite-Fired Power Plant

Authors: Cigdem Safak Saglam

Abstract:

Most thermal power plants use steam as working fluid in their power cycle. Therefore, in addition to fuel, water is the other main input for thermal plants. Water and steam must be highly pure in order to protect the systems from corrosion, scaling and biofouling. Pure process water is produced in water treatment plants having many several treatment methods. Treatment plant design is selected depending on raw water source and required water quality. Although working principle of fossil-fuel fired thermal power plants are same, there is no standard design and equipment arrangement valid for all thermal power plant utility systems. Besides that, there are many other technology evaluation and selection criteria for designing the most optimal water systems meeting the requirements such as local conditions, environmental restrictions, electricity and other consumables availability and transport, process water sources and scarcity, land use constraints etc. Aim of this study is explaining the adopted methodology for technology selection for process water preparation and industrial waste water treatment plant in a thermal power plant project located in Tufanbeyli, Adana Province in Turkey. Thermal power plant is fired with indigenous lignite coal extracted from adjacent lignite reserves. This paper addresses all above-mentioned factors affecting the thermal power plant water treatment facilities (demineralization + waste water treatment) design and describes the ultimate design of Tufanbeyli Thermal Power Plant Water Treatment Plant.

Keywords: Thermal power plant, lignite coal, pre-treatment, demineralization, electrodialysis, recycling, waste water, process water.

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5201 Coreless Printed Circuit Board (PCB) Stepdown Transformers for DC-DC Converter Applications

Authors: Radhika Ambatipudi, Hari Babu Kotte, Dr. Kent Bertilsson

Abstract:

In this paper, multilayered coreless printed circuit board (PCB) step-down power transformers for DC-DC converter applications have been designed, manufactured and evaluated. A set of two different circular spiral step-down transformers were fabricated in the four layered PCB. These transformers have been modelled with the assistance of high frequency equivalent circuit and characterized with both sinusoidal and square wave excitation. This paper provides the comparative results of these two different transformers in terms of their resistances, self, leakage, mutual inductances, coupling coefficient and also their energy efficiencies. The operating regions for optimal performance of these transformers for power transfer applications are determined. These transformers were tested for the output power levels of about 30 Watts within the input voltage range of 12-50 Vrms. The energy efficiency for these step down transformers is observed to be in the range of 90%-97% in MHz frequency region.

Keywords: Coreless Step down Transformer, DC-DC Converterapplications, High frequency transformer, MHz operating frequency, Multilayered PCB transformers, Power Transfer Applications.

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5200 Modular Harmonic Cancellation in a Multiplier High Voltage Direct Current Generator

Authors: Ahmad Zahran, Ahmed Herzallah, Ahmad Ahmad, Mahran Quraan

Abstract:

Generation of high DC voltages is necessary for testing the insulation material of high voltage AC transmission lines with long lengths. The harmonic and ripple contents of the output DC voltage supplied by high voltage DC circuits require the use of costly capacitors to smooth the output voltage after rectification. This paper proposes a new modular multiplier high voltage DC generator with embedded Cockcroft-Walton circuits that achieve a negligible harmonic and ripple contents of the output DC voltage without the need for costly filters to produce a nearly constant output voltage. In this new topology, Cockcroft-Walton modules are connected in series to produce a high DC output voltage. The modules are supplied by low input AC voltage sources that have the same magnitude and frequency and shifted from each other by a certain angle to eliminate the harmonics from the output voltage. The small ripple factor is provided by the smoothing column capacitors and the phase shifted input voltages of the cascaded modules. The constituent harmonics within each module are determined using Fourier analysis. The viability of the proposed DC generator for testing purposes and the effectiveness of the cascaded connection are confirmed by numerical simulations using MATLAB/Simulink.

Keywords: Cockcroft-Walton circuit, Harmonics, Ripple factor, HVDC generator.

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5199 Artificial Neural Networks Application to Improve Shunt Active Power Filter

Authors: Rachid.Dehini, Abdesselam.Bassou, Brahim.Ferdi

Abstract:

Active Power Filters (APFs) are today the most widely used systems to eliminate harmonics compensate power factor and correct unbalanced problems in industrial power plants. We propose to improve the performances of conventional APFs by using artificial neural networks (ANNs) for harmonics estimation. This new method combines both the strategies for extracting the three-phase reference currents for active power filters and DC link voltage control method. The ANNs learning capabilities to adaptively choose the power system parameters for both to compute the reference currents and to recharge the capacitor value requested by VDC voltage in order to ensure suitable transit of powers to supply the inverter. To investigate the performance of this identification method, the study has been accomplished using simulation with the MATLAB Simulink Power System Toolbox. The simulation study results of the new (SAPF) identification technique compared to other similar methods are found quite satisfactory by assuring good filtering characteristics and high system stability.

Keywords: Artificial Neural Networks (ANN), p-q theory, (SAPF), Harmonics, Total Harmonic Distortion.

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5198 14-Bit 1MS/s Cyclic-Pipelined ADC

Authors: S. Saisundar, Shan Jiang, Kevin T. C. Chai, David Nuttman, Minkyu Je

Abstract:

This paper presents a 14-bit cyclic-pipelined Analog to digital converter (ADC) running at 1 MS/s. The architecture is based on a 1.5-bit per stage structure utilizing digital correction for each stage. The ADC consists of two 1.5-bit stages, one shift register delay line, and digital error correction logic. Inside each 1.5-bit stage, there is one gain-boosting op-amp and two comparators. The ADC was implemented in 0.18µm CMOS process and the design has an area of approximately 0.2 mm2. The ADC has a differential input range of 1.2 Vpp. The circuit has an average power consumption of 3.5mA with 10MHz sampling clocks. The post-layout simulations of the design satisfy 12-bit SNDR with a full-scale sinusoid input.


Keywords: Analog to digital converter, cyclic, gain-boosting, pipelined.

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5197 Learning Algorithms for Fuzzy Inference Systems Composed of Double- and Single-Input Rule Modules

Authors: Hirofumi Miyajima, Kazuya Kishida, Noritaka Shigei, Hiromi Miyajima

Abstract:

Most of self-tuning fuzzy systems, which are automatically constructed from learning data, are based on the steepest descent method (SDM). However, this approach often requires a large convergence time and gets stuck into a shallow local minimum. One of its solutions is to use fuzzy rule modules with a small number of inputs such as DIRMs (Double-Input Rule Modules) and SIRMs (Single-Input Rule Modules). In this paper, we consider a (generalized) DIRMs model composed of double and single-input rule modules. Further, in order to reduce the redundant modules for the (generalized) DIRMs model, pruning and generative learning algorithms for the model are suggested. In order to show the effectiveness of them, numerical simulations for function approximation, Box-Jenkins and obstacle avoidance problems are performed.

Keywords: Box-Jenkins’s problem, Double-input rule module, Fuzzy inference model, Obstacle avoidance, Single-input rule module.

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5196 Transient Analysis & Performance Estimation of Gate Inside Junctionless Transistor (GI-JLT)

Authors: Sangeeta Singh, Pankaj Kumar, P. N. Kondekar

Abstract:

In this paper, the transient device performance analysis of n-type Gate Inside JunctionLess Transistor (GI-JLT) has been evaluated. 3-D Bohm Quantum Potential (BQP) transport device simulation has been used to evaluate the delay and power dissipation performance. GI-JLT has a number of desirable device parameters such as reduced propagation delay, dynamic power dissipation, power and delay product, intrinsic gate delay and energy delay product as compared to Gate-all-around transistors GAA-JLT. In addition to this, various other device performance parameters namely, on/off current ratio, short channel effects (SCE), transconductance Generation Factor (TGF) and unity gain cut-off frequency (fT ) and subthreshold slope (SS) of the GI-JLT and GAA-JLT have been analyzed and compared. GI-JLT shows better device performance characteristics than GAA-JLT for low power and high frequency applications, because of its larger gate electrostatic control on the device operation.

Keywords: Gate-inside junctionless transistor GI-JLT, Gate-all-around junctionless transistor GAA-JLT, propagation delay, power delay product.

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5195 Thermal Analysis of a Transport Refrigeration Power Pack Unit Using a Coupled 1D/3D Simulation Approach

Authors: A. Kospach, A. Mladek, M. Waltenberger, F. Schilling

Abstract:

In this work, a coupled 1D/3D simulation approach for thermal protection and optimization of a trailer refrigeration power pack unit was developed. With the developed 1D/3D simulation approach thermal critical scenarios, such as summer, high-load scenarios are investigated. The 1D thermal model was built up consisting of the thermal network, which includes different point masses and associated heat transfers, the coolant and oil circuits, as well as the fan unit. The 3D computational fluid dynamics (CFD) model was developed to model the air flow through the power pack unit considering convective heat transfer effects. In the 1D thermal model the temperatures of the individual point masses were calculated, which served as input variables for the 3D CFD model. For the calculation of the point mass temperatures in the 1D thermal model, the convective heat transfer rates from the 3D CFD model were required as input variables. These two variables (point mass temperatures and convective heat transfer rates) were the main couple variables for the coupled 1D/3D simulation model. The coupled 1D/3D model was validated with measurements under normal operating conditions. Coupled simulations for summer high-load case were than performed and compared with a reference case under normal operation conditions. Hot temperature regions and components could be identified. Due to the detailed information about the flow field, temperatures and heat fluxes, it was possible to directly derive improvement suggestions for the cooling design of the transport refrigeration power pack unit.

Keywords: Coupled thermal simulation, thermal analysis, transport refrigeration unit, 3D computational fluid dynamics, 1D thermal modelling, thermal management systems.

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5194 Effect of Low Frequency Memory on High Power 12W LDMOS Transistors Intermodulation Distortion

Authors: A. Alghanim, J. Benedikt, P. J. Tasker

Abstract:

The increasing demand for higher data rates in wireless communication systems has led to the more effective and efficient use of all allocated frequency bands. In order to use the whole bandwidth at maximum efficiency, one needs to have RF power amplifiers with a higher linear level and memory-less performance. This is considered to be a major challenge to circuit designers. In this thesis the linearity and memory are studied and examined via the behavior of the intermodulation distortion (IMD). A major source of the in-band distortion can be shown to be influenced by the out-of-band impedances presented at either the input or the output of the device, especially those impedances terminated the low frequency (IF) components. Thus, in order to regulate the in-band distortion, the out of-band distortion must be controllable. These investigations are performed on a 12W LDMOS device characterised at 2.1 GHz within a purpose built, high-power measurement system.

Keywords: Low Frequency Memory, IntermodulationDistortion (IMD).

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5193 Impedance Matching of Axial Mode Helical Antennas

Authors: Hossein Mardani, Neil Buchanan, Robert Cahill, Vincent Fusco

Abstract:

In this paper, we study the input impedance characteristics of axial mode helical antennas to find an effective way for matching it to 50 Ω. The study is done on the important matching parameters such as like wire diameter and helix to the ground plane gap. It is intended that these parameters control the matching without detrimentally affecting the radiation pattern. Using transmission line theory, a simple broadband technique is proposed, which is applicable for perfect matching of antennas with similar design parameters. We provide design curves to help to choose the proper dimensions of the matching section based on the antenna’s unmatched input impedance. Finally, using the proposed technique, a 4-turn axial mode helix is designed at 2.5 GHz center frequency and the measurement results of the manufactured antenna will be included. This parametric study gives a good insight into the input impedance characteristics of axial mode helical antennas and the proposed impedance matching approach provides a simple, useful method for matching these types of antennas.

Keywords: Antenna, helix, helical, axial mode, wireless power transfer, impedance matching.

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5192 A Set Theory Based Factoring Technique and Its Use for Low Power Logic Design

Authors: Padmanabhan Balasubramanian, Ryuta Arisaka

Abstract:

Factoring Boolean functions is one of the basic operations in algorithmic logic synthesis. A novel algebraic factorization heuristic for single-output combinatorial logic functions is presented in this paper and is developed based on the set theory paradigm. The impact of factoring is analyzed mainly from a low power design perspective for standard cell based digital designs in this paper. The physical implementation of a number of MCNC/IWLS combinational benchmark functions and sub-functions are compared before and after factoring, based on a simple technology mapping procedure utilizing only standard gate primitives (readily available as standard cells in a technology library) and not cells corresponding to optimized complex logic. The power results were obtained at the gate-level by means of an industry-standard power analysis tool from Synopsys, targeting a 130nm (0.13μm) UMC CMOS library, for the typical case. The wire-loads were inserted automatically and the simulations were performed with maximum input activity. The gate-level simulations demonstrate the advantage of the proposed factoring technique in comparison with other existing methods from a low power perspective, for arbitrary examples. Though the benchmarks experimentation reports mixed results, the mean savings in total power and dynamic power for the factored solution over a non-factored solution were 6.11% and 5.85% respectively. In terms of leakage power, the average savings for the factored forms was significant to the tune of 23.48%. The factored solution is expected to better its non-factored counterpart in terms of the power-delay product as it is well-known that factoring, in general, yields a delay-efficient multi-level solution.

Keywords: Factorization, Set theory, Logic function, Standardcell based design, Low power.

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5191 LFC Design of a Deregulated Power System with TCPS Using PSO

Authors: H. Shayeghi, H.A. Shayanfar, A. Jalili

Abstract:

In the LFC problem, the interconnections among some areas are the input of disturbances, and therefore, it is important to suppress the disturbances by the coordination of governor systems. In contrast, tie-line power flow control by TCPS located between two areas makes it possible to stabilize the system frequency oscillations positively through interconnection, which is also expected to provide a new ancillary service for the further power systems. Thus, a control strategy using controlling the phase angle of TCPS is proposed for provide active control facility of system frequency in this paper. Also, the optimum adjustment of PID controller's parameters in a robust way under bilateral contracted scenario following the large step load demands and disturbances with and without TCPS are investigated by Particle Swarm Optimization (PSO), that has a strong ability to find the most optimistic results. This newly developed control strategy combines the advantage of PSO and TCPS and has simple stricture that is easy to implement and tune. To demonstrate the effectiveness of the proposed control strategy a three-area restructured power system is considered as a test system under different operating conditions and system nonlinearities. Analysis reveals that the TCPS is quite capable of suppressing the frequency and tie-line power oscillations effectively as compared to that obtained without TCPS for a wide range of plant parameter changes, area load demands and disturbances even in the presence of system nonlinearities.

Keywords: LFC, TCPS, Dregulated Power System, PowerSystem Control, PSO.

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5190 Suitability of Alternative Insulating Fluid for Power Transformer: A Laboratory Investigation

Authors: S. N. Deepa, A. D. Srinivasan, K. T. Veeramanju, R. Sandeep Kumar, Ashwini Mathapati

Abstract:

Power transformer is a vital element in a power system as it continuously regulates power flow, maintaining good voltage regulation. The working of transformer much depends on the oil insulation, the oil insulation also decides the aging of transformer and hence its reliability. The mineral oil based liquid insulation is globally accepted for power transformer insulation; however it is potentially hazardous due to its non-biodegradability. In this work efficient alternative biodegradable insulating fluid is presented as a replacement to conventional mineral oil. Dielectric tests are performed as distinct alternating fluid to evaluate the suitability for transformer insulation. The selection of the distinct natural esters for an insulation system is carried out by the laboratory investigation of Breakdown voltage, Oxidation stability, Dissipation factor, Permittivity, Viscosity, Flash and Fire point. It is proposed to study and characterize the properties of natural esters to be used in power transformer. Therefore for the investigation of the dielectric behavior rice bran oil, sesame oil, and sunflower oil are considered for the study. The investigated results have been compared with the mineral oil to validate the dielectric behavior of natural esters.

Keywords: Alternative insulating fluid, dielectric properties, natural esters, power transformers.

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5189 Optimal Simultaneous Sizing and Siting of DGs and Smart Meters Considering Voltage Profile Improvement in Active Distribution Networks

Authors: T. Sattarpour, D. Nazarpour

Abstract:

This paper investigates the effect of simultaneous placement of DGs and smart meters (SMs), on voltage profile improvement in active distribution networks (ADNs). A substantial center of attention has recently been on responsive loads initiated in power system problem studies such as distributed generations (DGs). Existence of responsive loads in active distribution networks (ADNs) would have undeniable effect on sizing and siting of DGs. For this reason, an optimal framework is proposed for sizing and siting of DGs and SMs in ADNs. SMs are taken into consideration for the sake of successful implementing of demand response programs (DRPs) such as direct load control (DLC) with end-side consumers. Looking for voltage profile improvement, the optimization procedure is solved by genetic algorithm (GA) and tested on IEEE 33-bus distribution test system. Different scenarios with variations in the number of DG units, individual or simultaneous placing of DGs and SMs, and adaptive power factor (APF) mode for DGs to support reactive power have been established. The obtained results confirm the significant effect of DRPs and APF mode in determining the optimal size and site of DGs to be connected in ADN resulting to the improvement of voltage profile as well.

Keywords: Active distribution network (ADN), distributed generations (DGs), smart meters (SMs), demand response programs (DRPs), adaptive power factor (APF).

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5188 Assessment of Solar Hydrogen Production in an Energetic Hybrid PV-PEMFC System

Authors: H. Rezzouk, M. Hatti, H. Rahmani, S. Atoui

Abstract:

This paper discusses the design and analysis of a hybrid PV-Fuel cell energy system destined to power a DC load. The system is composed of a photovoltaic array, a fuel cell, an electrolyzer and a hydrogen tank. HOMER software is used in this study to calculate the optimum capacities of the power system components that their combination allows an efficient use of solar resource to cover the hourly load needs. The optimal system sizing allows establishing the right balance between the daily electrical energy produced by the power system and the daily electrical energy consumed by the DC load using a 28 KW PV array, a 7.5 KW fuel cell, a 40KW electrolyzer and a 270 Kg hydrogen tank. The variation of powers involved into the DC bus of the hybrid PV-fuel cell system has been computed and analyzed for each hour over one year: the output powers of the PV array and the fuel cell, the input power of the elctrolyzer system and the DC primary load. Equally, the annual variation of stored hydrogen produced by the electrolyzer has been assessed. The PV array contributes in the power system with 82% whereas the fuel cell produces 18%. 38% of the total energy consumption belongs to the DC primary load while the rest goes to the electrolyzer.

Keywords: Electrolyzer, Hydrogen, Hydrogen Fueled Cell, Photovoltaic.

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5187 Modified Scaling-Free CORDIC Based Pipelined Parallel MDC FFT and IFFT Architecture for Radix 2^2 Algorithm

Authors: C. Paramasivam, K. B. Jayanthi

Abstract:

An innovative approach to develop modified scaling free CORDIC based two parallel pipelined Multipath Delay Commutator (MDC) FFT and IFFT architectures for radix 22 FFT algorithm is presented. Multipliers and adders are the most important data paths in FFT and IFFT architectures. Multipliers occupy high area and consume more power. In order to optimize the area and power overhead, modified scaling-free CORDIC based complex multiplier is utilized in the proposed design. In general twiddle factor values are stored in RAM block. In the proposed work, modified scaling-free CORDIC based twiddle factor generator unit is used to generate the twiddle factor and efficient switching units are used. In addition to this, four point FFT operations are performed without complex multiplication which helps to reduce area and power in the last two stages of the pipelined architectures. The design proposed in this paper is based on multipath delay commutator method. The proposed design can be extended to any radix 2n based FFT/IFFT algorithm to improve the throughput. The work is synthesized using Synopsys design Compiler using TSMC 90-nm library. The proposed method proves to be better compared to the reference design in terms of area, throughput and power consumption. The comparative analysis of the proposed design with Xilinx FPGA platform is also discussed in the paper.

Keywords: Coordinate Rotational Digital Computer(CORDIC), Complex multiplier, Fast Fourier transform (FFT), Inverse fast Fourier transform (IFFT), Multipath delay Commutator (MDC), modified scaling free CORDIC, complex multiplier, pipelining, parallel processing, radix-2^2.

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5186 Library Aware Power Conscious Realization of Complementary Boolean Functions

Authors: Padmanabhan Balasubramanian, C. Ardil

Abstract:

In this paper, we consider the problem of logic simplification for a special class of logic functions, namely complementary Boolean functions (CBF), targeting low power implementation using static CMOS logic style. The functions are uniquely characterized by the presence of terms, where for a canonical binary 2-tuple, D(mj) ∪ D(mk) = { } and therefore, we have | D(mj) ∪ D(mk) | = 0 [19]. Similarly, D(Mj) ∪ D(Mk) = { } and hence | D(Mj) ∪ D(Mk) | = 0. Here, 'mk' and 'Mk' represent a minterm and maxterm respectively. We compare the circuits minimized with our proposed method with those corresponding to factored Reed-Muller (f-RM) form, factored Pseudo Kronecker Reed-Muller (f-PKRM) form, and factored Generalized Reed-Muller (f-GRM) form. We have opted for algebraic factorization of the Reed-Muller (RM) form and its different variants, using the factorization rules of [1], as it is simple and requires much less CPU execution time compared to Boolean factorization operations. This technique has enabled us to greatly reduce the literal count as well as the gate count needed for such RM realizations, which are generally prone to consuming more cells and subsequently more power consumption. However, this leads to a drawback in terms of the design-for-test attribute associated with the various RM forms. Though we still preserve the definition of those forms viz. realizing such functionality with only select types of logic gates (AND gate and XOR gate), the structural integrity of the logic levels is not preserved. This would consequently alter the testability properties of such circuits i.e. it may increase/decrease/maintain the same number of test input vectors needed for their exhaustive testability, subsequently affecting their generalized test vector computation. We do not consider the issue of design-for-testability here, but, instead focus on the power consumption of the final logic implementation, after realization with a conventional CMOS process technology (0.35 micron TSMC process). The quality of the resulting circuits evaluated on the basis of an established cost metric viz., power consumption, demonstrate average savings by 26.79% for the samples considered in this work, besides reduction in number of gates and input literals by 39.66% and 12.98% respectively, in comparison with other factored RM forms.

Keywords: Reed-Muller forms, Logic function, Hammingdistance, Algebraic factorization, Low power design.

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5185 A Design of Electronically Tunable Voltagemode Universal Filter with High Input Impedance

Authors: Surapong Siripongdee, Witthaya Mekhum

Abstract:

This article presents a voltage-mode universal biquadratic filter performing simultaneous 3 standard functions: lowpass, high-pass and band-pass functions, employing differential different current conveyor (DDCC) and current controlled current conveyor (CCCII) as active element. The features of the circuit are that: the quality factor and pole frequency can be tuned independently via the input bias currents: the circuit description is very simple, consisting of 1 DDCC, 2 CCCIIs, 2 electronic resistors and 2 grounded capacitors. Without requiring component matching conditions, the proposed circuit is very appropriate to further develop into an integrated circuit. The PSPICE simulation results are depicted. The given results agree well with the theoretical anticipation.

Keywords: Filter, DDCC, CCCII, Analog circuit, Voltagemode, PSPICE

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