Search results for: Bus voltage and line current (BVLC)

Authors: Ali M. Eltamaly, A. I. Alolah, R. Hamouda, M. Y. Abdulghany

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In this paper a novel, simple and reliable digital firing scheme has been implemented for speed control of three-phase induction motor using ac voltage controller. The system consists of three-phase supply connected to the three-phase induction motor via three triacs and its control circuit. The ac voltage controller has three modes of operation depending on the shape of supply current. The performance of the induction motor differs in each mode where the speed is directly proportional with firing angle in two modes and inversely in the third one. So, the control system has to detect the current mode of operation to choose the correct firing angle of triacs. Three sensors are used to feed the line currents to control system to detect the mode of operation. The control strategy is implemented using a low cost Xilinx Spartan-3E field programmable gate array (FPGA) device. Three PI-controllers are designed on FPGA to control the system in the three-modes. Simulation of the system is carried out using PSIM computer program. The simulation results show stable operation for different loading conditions especially in mode 2/3. The simulation results have been compared with the experimental results from laboratory prototype.

Keywords: FPGA, Induction motor, PSIM, triac, Voltage controller.

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Authors: Suresh Alapati, Sreehari Rao Patri, K. S. R. Krishna Prasad

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Anultra-low power capacitor less low-dropout voltage regulator with improved transient response using gain enhanced feed forward path compensation is presented in this paper. It is based on a cascade of a voltage amplifier and a transconductor stage in the feed forward path with regular error amplifier to form a composite gainenhanced feed forward stage. It broadens the gain bandwidth and thus improves the transient response without substantial increase in power consumption. The proposed LDO, designed for a maximum output current of 100 mA in UMC 180 nm, requires a quiescent current of 69 )A. An undershot of 153.79mV for a load current changes from 0mA to 100mA and an overshoot of 196.24mV for current change of 100mA to 0mA. The settling time is approximately 1.1 )s for the output voltage undershooting case. The load regulation is of 2.77 )V/mA at load current of 100mA. Reference voltage is generated by using an accurate band gap reference circuit of 0.8V.The costly features of SOC such as total chip area and power consumption is drastically reduced by the use of only a total compensation capacitance of 6pF while consuming power consumption of 0.096 mW.

Keywords: Capacitor-less LDO, frequency compensation, Transient response, latch, self-biased differential amplifier.

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Authors: Jayendra Krishna, Laxmi Srivastava

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Power flow (PF) study, which is performed to determine the power system static states (voltage magnitudes and voltage angles) at each bus to find the steady state operating condition of a system, is very important and is the most frequently carried out study by power utilities for power system planning, operation and control. In this paper, a counterpropagation neural network (CPNN) is proposed to solve power flow problem under different loading/contingency conditions for computing bus voltage magnitudes and angles of the power system. The counterpropagation network uses a different mapping strategy namely counterpropagation and provides a practical approach for implementing a pattern mapping task, since learning is fast in this network. The composition of the input variables for the proposed neural network has been selected to emulate the solution process of a conventional power flow program. The effectiveness of the proposed CPNN based approach for solving power flow is demonstrated by computation of bus voltage magnitudes and voltage angles for different loading conditions and single line-outage contingencies in IEEE 14-bus system.

Keywords: Admittance matrix, counterpropagation neural network, line outage contingency, power flow

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Authors: Amany M. El-Zonkoly, Hussein Desouki

Abstract:

Distance protection of transmission lines including advanced flexible AC transmission system (FACTS) devices has been a very challenging task. FACTS devices of interest in this paper are static synchronous series compensators (SSSC) and unified power flow controller (UPFC). In this paper, a new algorithm is proposed to detect and classify the fault and identify the fault position in a transmission line with respect to a FACTS device placed in the midpoint of the transmission line. Discrete wavelet transformation and wavelet entropy calculations are used to analyze during fault current and voltage signals of the compensated transmission line. The proposed algorithm is very simple and accurate in fault detection and classification. A variety of fault cases and simulation results are introduced to show the effectiveness of such algorithm.

Keywords: Entropy calculation, FACTS, SSSC, UPFC, wavelet transform.

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Authors: A. S. Telang, P. P. Bedekar

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In today’s world, electrical energy has become an indispensable component of all aspects of modern human life. Reliability, security and stability are the key aspects of any power system. Failure to meet any of these three aspects results into a great impediment to modern life. Modern power systems are being subjected to heavily stressed conditions leading to voltage stability problems. If the voltage stability problems are not mitigated properly through proper voltage stability assessment methods, cascading events may occur which may lead to voltage collapse or blackout events. Modern FACTS devices like STATCOM are one of the measures to overcome the blackout problems. As these devices are very costly, they must be installed properly at suitable locations, mostly at weak bus. Line voltage stability indices such as FVSI, Lmn and LQP play important role for identification of a weak bus. This paper presents evaluation of these line stability indices for the assessment of reliable information about the closeness of the power system to voltage collapse. PSAT is a user-friendly MATLAB toolbox, of which CPF is an important feature which has been extensively used for the placement of STATCOM to assess the stability. Novelty of the present research work lies in that the active and reactive load has been changed simultaneously at all the load buses under consideration. MATLAB code has been developed for the same and tested successfully on various standard IEEE test systems. The results for standard IEEE14 bus test system, specifically, are presented in this paper.

Keywords: Voltage stability analysis, voltage collapse, PSAT, CPF, VSI, FVSI, Lmn, LQP.

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Authors: Syed Iftekhar Ali, M. S. Islam

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In this paper we present an energy efficient match-line (ML) sensing scheme for high-speed ternary content-addressable memory (TCAM). The proposed scheme isolates the sensing unit of the sense amplifier from the large and variable ML capacitance. It employs feedback in the sense amplifier to successfully detect a match while keeping the ML voltage swing low. This reduced voltage swing results in large energy saving. Simulation performed using 130nm 1.2V CMOS logic shows at least 30% total energy saving in our scheme compared to popular current race (CR) scheme for similar search speed. In terms of speed, dynamic energy, peak power consumption and transistor count our scheme also shows better performance than mismatch-dependant (MD) power allocation technique which also employs feedback in the sense amplifier. Additionally, the implementation of our scheme is simpler than CR or MD scheme because of absence of analog control voltage and programmable delay circuit as have been used in those schemes.

Keywords: content-addressable memory, energy consumption, feedback, peak power, sensing scheme, sense amplifier, ternary.

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Authors: M. Marsadek, A. Mohamed

Abstract:

Power system security analysis is the most time demanding process due to large number of possible contingencies that need to be analyzed.  In a power system, any contingency resulting in security violation such as line overload or low voltage may occur for a number of reasons at any time.  To efficiently rank a contingency, both probability and the extent of security violation must be considered so as not to underestimate the risk associated with the contingency. This paper proposed a contingency ranking method that take into account the probabilistic nature of power system and the severity of contingency by using a newly developed method based on risk factor.  The proposed technique is implemented on IEEE 24-bus system.

Keywords: Line overload, low voltage, probability, risk factor, severity.

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Authors: T. Taufik, R. Prasetyo, D. Dolan, D. Garinto

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Today-s Voltage Regulator Modules (VRMs) face increasing design challenges as the number of transistors in microprocessors increases per Moore-s Law. These challenges have recently become even more demanding as microprocessors operate at sub voltage range at significantly high current. This paper presents a new multiphase topology with cell configuration for improved performance in low voltage and high current applications. A lab scale hardware prototype of the new topology was design and constructed. Laboratory tests were performed on the proposed converter and compared with a commercially available VRM. Results from the proposed topology exhibit improved performance compared to the commercially available counterpart.

Keywords: Voltage Regulator Modules, dc-dc converters, powerelectronics.

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Authors: Houda Bdiri Gabbouj, Néjib Hassen, Kamel Besbes

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This paper presents a low-voltage low-power differential linear transconductor with near rail-to-rail input swing. Based on the current-mirror OTA topology, the proposed transconductor combines the Flipped Voltage Follower (FVF) technique to linearize the transconductor behavior that leads to class- AB linear operation and the virtual transistor technique to lower the effective threshold voltages of the transistors which offers an advantage in terms of low supply requirement. Design of the OTA has been discussed. It operates at supply voltages of about ±0.8V. Simulation results for 0.18μm TSMC CMOS technology show a good input range of 1Vpp with a high DC gain of 81.53dB and a total harmonic distortion of -40dB at 1MHz for an input of 1Vpp. The main aim of this paper is to present and compare new OTA design with high transconductance, which has a potential to be used in low voltage applications.

Keywords: Amplifier class AB, current mirror, flipped voltage follower, low voltage.

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Authors: Gulshan Sharma

Abstract:

This article presents the design of optimal automatic generation control (AGC) based on full state feedback control for a multi-area interconnected power system. An extra high voltage AC transmission line in parallel with a high voltage DC link is considered as an area interconnection between the areas. The optimal AGC are designed and implemented in the wake of 1% load perturbation in one of the areas and the system dynamic response plots for various system states are obtained to investigate the system dynamic performance. The pattern of closed-loop eigenvalues are also determined to analyze the system stability. From the investigations carried out in the work, it is revealed that the dynamic performance of the system under consideration has an appreciable improvement when a high voltage DC line is paralleled with an extra high voltage AC line as an interconnection between the areas. The investigation of closed-loop eigenvalues reveals that the system stability is ensured in all case studies carried out with the designed optimal AGC.

Keywords: Automatic generation control, area control error, DC link, optimal AGC regulator, closed-loop eigenvalues.

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Authors: Ravit Gautam, Dipen A. Mistry, Manmohan Singh Meena, Bhupelly Dheeraj, Suresh Mikkili

Abstract:

Due to the increased use of the power electronic equipment, harmonics in the power system has increased to a greater extent. These harmonics results a poor power quality causing a major effect on the customers. Shunt active filters (SHAF) are used for the mitigations of the current harmonics and to maintain constant DC link voltage. PI and Fuzzy logic controllers (FLC) were used to control the performance of the shunt active filter under both balance and unbalance source voltage condition. The results found were not satisfying the IEEE-519 standards of THD to be less than 5%. Hysteresis band current control was used to obtain the gating signals for SHAF, though it has some drawbacks and thus to obtain a better performance of the SHAF to mitigate the harmonics, adaptive hysteresis band current control scheme is implemented. Adaptive hysteresis based SHAF is used to obtain better compensation of current harmonics and to regulate the DC link voltage in a better way.

Keywords: DC Link Voltage, Fuzzy Logic Controller, Adaptive Hysteresis, Harmonics, Shunt Active Filter.

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Authors: Jae-Kyung Lee, Nam-Joon Jung, Byung-Hak Cho

Abstract:

The line sleeves on power transmission line connects two conductors while the transmission line is constructing. However, the line sleeves sometimes cause transmission line break down, because the line sleeves are deteriorated and decayed by acid rain. When the transmission line is broken, the economical loss is huge. Therefore the line sleeves on power transmission lines should be inspected periodically to prevent power failure. In this paper, Korea Electric Power Research Institute reviewed several robots to inspect line status and proposes a robot to inspect line sleeve by measuring magnetic field on line sleeve. The developed inspection tool can reliable to move along transmission line and overcome several obstacles on transmission line. The developed system is also applied on power transmission line and verified the efficiency of the robot.

Keywords: Transmission line inspection, line sleeve, transmission line inspection robot, line sleeve inspection

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Authors: Justinian Anatory, Nelson Theethayi, M. M. Kissaka, N. H. Mvungi

Abstract:

Power line channel is proposed as an alternative for broadband data transmission especially in developing countries like Tanzania [1]. However the channel is affected by stochastic attenuation and deep notches which can lead to the limitation of channel capacity and achievable data rate. Various studies have characterized the channel without giving exactly the maximum performance and limitation in data transfer rate may be this is due to complexity of channel modeling being used. In this paper the channel performance of medium voltage, low voltage and indoor power line channel is presented. In the investigations orthogonal frequency division multiplexing (OFDM) with phase shift keying (PSK) as carrier modulation schemes is considered, for indoor, medium and low voltage channels with typical ten branches and also Golay coding is applied for medium voltage channel. From channels, frequency response deep notches are observed in various frequencies which can lead to reduce the achievable data rate. However, is observed that data rate up to 240Mbps is realized for a signal to noise ratio of about 50dB for indoor and low voltage channels, however for medium voltage a typical link with ten branches is affected by strong multipath and coding is required for feasible broadband data transfer.

Keywords: Powerline Communications, branched network, channel model, modulation, channel performance, OFDM.

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Authors: H. Abaali, M. T. Lamchich, M. Raoufi

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There are a variety of reference current identification methods, for the shunt active power filter (SAPF), such as the instantaneous active and reactive power, the instantaneous active and reactive current and the synchronous detection method are evaluated and compared under ideal, non sinusoidal and unbalanced voltage conditions. The SAPF performances, for the investigated identification methods, are tested for a non linear load. The simulation results, using Matlab Power System Blockset Toolbox from a complete structure, are presented and discussed.

Keywords: Shunt active power filter, Current perturbation, Non sinusoidal and unbalanced voltage conditions.

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Authors: Jin-Lung Guan, Jyh-Cherng Gu, Ming-Ta Yang, Hsin-Hung Chang, Chun-Wei Huang, Shao-Yu Huang

Abstract:

One of the most important power quality issues is voltage flicker. Nowadays this issue also impacts the power system all over the world. The fact of the matter is that the more and the larger capacity of wind generator has been installed. Under unstable wind power situation, the variation of output current and voltage have caused trouble to voltage flicker. Hence, the major purpose of this study is to analyze the impact of wind generator on voltage flicker of power system. First of all, digital simulation and analysis are carried out based on wind generator operating under various system short circuit capacity, impedance angle, loading, and power factor of load. The simulation results have been confirmed by field measurements.

Keywords: Wind Generator, Voltage Flicker

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Authors: Venkatesh C., K. Shanti Swarup

Abstract:

This paper investigates the impact on operating time delay and relay maloperation when 1st,2nd and 3rd order analog antialiasing filters are used in numerical distance protection. RC filter with cut-off frequency 90 Hz is used. Simulations are carried out for different SIR (Source to line Impedance Ratio), load, fault type and fault conditions using SIMULINK, where the voltage and current signals are fed online to the developed numerical distance relay model. Matlab is used for plotting the impedance trajectory. Investigation results shows that, about 75 % of the simulated cases, numerical distance relay operating time is not increased even-though there is a time delay when higher order filters are used. Relay maloperation (selectivity) also reduces (increases) when higher order filters are used in numerical distance protection.

Keywords: Antialiasing, capacitive voltage transformers, delay estimation, discrete Fourier transform (DFT), distance measurement, low-pass filters, source to line impedance ratio (SIR), protective relaying.

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Authors: Jae-Chang Kwak, Yong-Seo Koo

Abstract:

The high efficiency power management IC (PMIC) with switching device is presented in this paper. PMIC is controlled with PFM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS (DT-CMOS) with low on-resistance is designed to decrease conduction loss. The threshold voltage of DT-CMOS drops as the gate voltage increase, resulting in a much higher current handling capability than standard MOSFET. PFM control circuits consist of a generator, AND gate and comparator. The generator is made to have 1.2MHz oscillation voltage. The DC-DC converter based on PFM control circuit and low on-resistance switching device is presented in this paper.

Keywords: DT-CMOS, PMIC, PFM, DC-DC converter.

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Authors: Bu Seog Ju, Jae Sang Kim, Woo Young Jung

Abstract:

In recent year, with recent increase of interest towards leisure sports, increased number of Zip-Line or Zip-Wire facilities has built. Many researches have been actively conducted on the emphasis of the cable and the wire at the bridge. However, very limited researches have been conducted on the safety of the Zip-Line structure. In fact, fall accidents from Zip-Line have been reported frequently. Therefore, in this study, the structural safety of Zip-Line under dynamic impact loading condition were evaluated on the previously installed steel cable for leisure (Zip-Line), using 3-dimensional nonlinear Finite Element (FE) model. The result from current study would assist assurance of systematic stability of Zip-Line.

Keywords: Zip-Line, Wire, Cable, 3D FE Model, Safety.

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Authors: Mohammed Amroune, Hadi Sebaa, Tarek Bouktir

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Reactive power limit of power system is one of the major causes of voltage instability. The only way to save the system from voltage instability is to reduce the reactive power load or add additional reactive power to reaching the point of voltage collapse. In recent times, the application of FACTS devices is a very effective solution to prevent voltage instability due to their fast and very flexible control. In this paper, voltage stability assessment with SVC and TCSC devices is investigated and compared in the modified IEEE 30-bus test system. The fast voltage stability indicator (FVSI) is used to identify weakest bus and to assess the voltage stability of power system.

Keywords: SVC, TCSC, Voltage stability, Fast Voltage Stability Index (FVSI), Reactive power.

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Authors: Adrian T. Plesca

Abstract:

This paper describes a three-dimensional thermal model of the current path included in the low voltage power circuit breakers. The model can be used to analyse the thermal behaviour of the current path during both steady-state and transient conditions. The current path lengthwise temperature distribution and timecurrent characteristic of the terminal connections of the power circuit breaker have been obtained. The influence of the electric current and voltage drop on main electric contact of the circuit breaker has been investigated. To validate the three-dimensional thermal model, some experimental tests have been done. There is a good correlation between experimental and simulation results.

Keywords: Current path, power circuit breakers, temperature distribution, thermal analysis.

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Authors: Bence Kővári, ZSolt Kertész

Abstract:

This paper proposes a stroke extraction method for use in off-line signature verification. After giving a brief overview of the current ongoing researches an algorithm is introduced for detecting and following strokes in static images of signatures. Problems like the handling of junctions and variations in line width and line intensity are discussed in detail. Results are validated by both using an existing on-line signature database and by employing image registration methods.

Keywords: Stroke extraction, spline fitting, off-line signatureverification, image registration.

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Authors: K. Sontaya, B. Pitiyont, V. Punsuvon

Abstract:

The objective of this study is to investigate the performance of the electrocoagulation process for color and COD removal in palm oil wastewater using a 10 L batch reactor. Iron was used as electrodes and the distance between electrodes was 2 cm. The effects of operating parameters: current voltage (6, 12 and 18 volt), reaction time (5, 15, 30, 45 and 60 min) and initial pH (4 and 9) of treatment efficiency were examine. The result showed that decolorization and COD removal efficiency increased with the increase in current voltage and reaction time. The proper condition for decolorization achieved at initial pH 4 and 9 were current voltage of 12 volt, reaction time 30 min. The decolorization efficiency reached 90.4% and 88.9%, respectively. COD removal was achiveved at current voltage 12 volt, reaction time 15 min. COD removal efficiency was 89.2 % and 83.0%, respectively. From the results, to show electrocoagulation process can treat palm oil mill wastewater in both acidic and basic condition at high efficiency for color and COD removal. Consequently, electrocoagulation process can be used or applied as a post-treatment step to improve the quality of the final discharge in term of color and residual COD removal.

Keywords: COD removal, decolorizaton, electrocoagulation, iron electrode, palm oil mill wastewater.

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Authors: M. Nageswara Rao

Abstract:

In this paper, a topology for high voltage gain half-bridge z-source inverter with low voltage stress on capacitors is proposed. The proposed inverter has only one impedance network. It can generate symmetric and asymmetric voltages with different magnitudes during both half-cycles. By selecting the duty cycle it can also produce conventional half-bridge inverter characteristics. It is used in special applications like, electrochemical and electro plating applications. Calculations of voltage ripple of capacitors, capacitors voltage stress inductors current ripple are presented. The proposed topology is simulated using PSCAD software and the simulated values are compared with the theoretical values.

Keywords: Half-bridge inverter, impedance network-source inverter, high voltage gain inverter, power system computer aided design.

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Authors: P.K. Sharma, B. Bhargava, S. Akashe

Abstract:

Power dissipation due to leakage current in the digital circuits is a biggest factor which is considered specially while designing nanoscale circuits. This paper is exploring the ideas of reducing leakage current in static CMOS circuits by stacking the transistors in increasing numbers. Clearly it means that the stacking of OFF transistors in large numbers result a significant reduction in power dissipation. Increase in source voltage of NMOS transistor minimizes the leakage current. Thus stacking technique makes circuit with minimum power dissipation losses due to leakage current. Also some of digital circuits such as full adder, D flip flop and 6T SRAM have been simulated in this paper, with the application of reduction technique on ‘cadence virtuoso tool’ using specter at 45nm technology with supply voltage 0.7V.

Keywords: Stack, 6T SRAM cell, low power, threshold voltage

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Authors: M. Zellagui, A. Chaghi

Abstract:

This paper presents the impact study of GTO Controlled Series Capacitor (GCSC) parameters on measured impedance (Zseen) by MHO distance relays for single transmission line high voltage 220 kV in the presence of single phase to earth fault with fault resistance (RF). The study deals with a 220 kV single electrical transmission line of Eastern Algerian transmission networks at Group Sonelgaz (Algerian Company of Electrical and Gas) compensated by series Flexible AC Transmission System (FACTS) i.e. GCSC connected at midpoint of the transmission line. The transmitted active and reactive powers are controlled by three GCSC-s. The effects of maximum reactive power injected as well as injected maximum voltage by GCSC on distance relays measured impedance is treated. The simulations results investigate the effects of GCSC injected parameters: variable reactance (XGCSC), variable voltage (VGCSC) and reactive power injected (QGCSC) on measured resistance and reactance in the presence of earth fault with resistance fault varied between 5 to 50 Ω for three cases study.

Keywords: GCSC Parameters, Transmission line, Earth fault, Symmetrical components, Distance protection, Measured impedance.

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Authors: Saif Ullah, Guan Zailin, Xu Xianhao, He Zongdong, Wang Baoxi

Abstract:

Assembly line balancing problem is aimed to divide the tasks among the stations in assembly lines and optimize some objectives. In assembly lines the workload on stations is different from each other due to different tasks times and the difference in workloads between stations can cause blockage or starvation in some stations in assembly lines. Buffers are used to store the semi-finished parts between the stations and can help to smooth the assembly production. The assembly line balancing and buffer sizing problem can affect the throughput of the assembly lines. Assembly line balancing and buffer sizing problems have been studied separately in literature and due to their collective contribution in throughput rate of assembly lines, balancing and buffer sizing problem are desired to study simultaneously and therefore they are considered concurrently in current research. Current research is aimed to maximize throughput, minimize total size of buffers in assembly line and minimize workload variations in assembly line simultaneously. A multi objective optimization objective is designed which can give better Pareto solutions from the Pareto front and a simple example problem is solved for assembly line balancing and buffer sizing simultaneously. Current research is significant for assembly line balancing research and it can be significant to introduce optimization approaches which can optimize current multi objective problem in future.

Keywords: Assembly line balancing, Buffer sizing, Pareto solutions.

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Authors: O. Hashemipour, S. G. Nabavi

Abstract:

A high-linearity and high-speed current-mode sampleand- hold circuit is designed and simulated using a 0.25μm CMOS technology. This circuit design is based on low voltage and it utilizes a fully differential circuit. Due to the use of only two switches the switch related noise has been reduced. Signal - dependent -error is completely eliminated by a new zero voltage switching technique. The circuit has a linearity error equal to ±0.05μa, i.e. 12-bit accuracy with a ±160 μa differential output - input signal frequency of 5MHZ, and sampling frequency of 100 MHZ. Third harmonic is equal to –78dB.

Keywords: Zero-voltage-technique, MOS-resistor, OTA, Feedback-resistor.

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Authors: Yash Pal, A.Swarup, Bhim Singh

Abstract:

A new topology of unified power quality conditioner (UPQC) is proposed for different power quality (PQ) improvement in a three-phase four-wire (3P-4W) distribution system. For neutral current mitigation, a star-hexagon transformer is connected in shunt near the load along with three-leg voltage source inverters (VSIs) based UPQC. For the mitigation of source neutral current, the uses of passive elements are advantageous over the active compensation due to ruggedness and less complexity of control. In addition to this, by connecting a star-hexagon transformer for neutral current mitigation the over all rating of the UPQC is reduced. The performance of the proposed topology of 3P-4W UPQC is evaluated for power-factor correction, load balancing, neutral current mitigation and mitigation of voltage and currents harmonics. A simple control algorithm based on Unit Vector Template (UVT) technique is used as a control strategy of UPQC for mitigation of different PQ problems. In this control scheme, the current/voltage control is applied over the fundamental supply currents/voltages instead of fast changing APFs currents/voltages, thereby reducing the computational delay. Moreover, no extra control is required for neutral source current compensation; hence the numbers of current sensors are reduced. The performance of the proposed topology of UPQC is analyzed through simulations results using MATLAB software with its Simulink and Power System Block set toolboxes.

Keywords: Power-factor correction, Load balancing, UPQC, Voltage and Current harmonics, Neutral current mitigation, Starhexagon transformer.

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Authors: Marios N. Moschakis

Abstract:

The increasing penetration of Distributed Generation and storage connected to the distribution network via PWM converters increases the possibility of a DC-component (offset) in voltage or current flowing into the grid. This occurs when even harmonics are present in the network voltage. DC-components can affect the operation and safety of several grid components. Therefore, an investigation of the way they are produced is important in order to take appropriate measures for their elimination. Further research on DC-components that appear on output voltage of converters is performed for different parameters of PWM technique and characteristics of even harmonics.

Keywords: Asymmetric even harmonics, DC-offsets, distributed generation, electric machine drive systems, power quality.

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Authors: Bo Bae Song, Byung Seok Lee, Hyun Young Kim, Chung Kwang Lee, Yong Seo Koo

Abstract:

This paper proposed a silicon controller rectifier (SCR) based ESD protection device to protect low voltage ESD for integrated circuit. The proposed ESD protection device has low trigger voltage and high holding voltage compared with conventional SCR-based ESD protection devices. The proposed ESD protection circuit is verified and compared by TCAD simulation. This paper verified effective low voltage ESD characteristics with low trigger voltage of 5.79V and high holding voltage of 3.5V through optimization depending on design variables (D1, D2, D3 and D4).

Keywords: ESD, SCR, Holding voltage, Latch-up.

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