Search results for: Power semiconductor device

Authors: F. Salehuddin, I. Ahmad, F. A. Hamid, A. Zaharim, H. A. Elgomati, B. Y. Majlis, P. R. Apte

Abstract:

In this study, the Taguchi method was used to optimize the effect of HALO structure or halo implant variations on threshold voltage (VTH) and leakage current (ILeak) in 45nm p-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) device. Besides halo implant dose, the other process parameters which used were Source/Drain (S/D) implant dose, oxide growth temperature and silicide anneal temperature. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, the most effective process parameters with respect to VTH and ILeak are halo implant dose (40%) and S/D implant dose (52%) respectively. Whereas the second ranking factor affecting VTH and ILeak are oxide growth temperature (32%) and halo implant dose (34%) respectively. The results show that after optimizations approaches is -0.157V at ILeak=0.195mA/μm.

Keywords: Optimization, p-type MOSFETs device, HALO Structure, Taguchi Method.

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Authors: Sae-Rom Pak, Seung Hwan Park, Jeong Ho Cho, Daewoong An, Cheong-Sool Park, Jun Seok Kim, Jun-Geol Baek

Abstract:

It is important to predict yield in semiconductor test process in order to increase yield. In this study, yield prediction means finding out defective die, wafer or lot effectively. Semiconductor test process consists of some test steps and each test includes various test items. In other world, test data has a big and complicated characteristic. It also is disproportionably distributed as the number of data belonging to FAIL class is extremely low. For yield prediction, general data mining techniques have a limitation without any data preprocessing due to eigen properties of test data. Therefore, this study proposes an under-sampling method using support vector machine (SVM) to eliminate an imbalanced characteristic. For evaluating a performance, randomly under-sampling method is compared with the proposed method using actual semiconductor test data. As a result, sampling method using SVM is effective in generating robust model for yield prediction.

Keywords: Yield Prediction, Semiconductor Test Process, Support Vector Machine, Under Sampling

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Authors: Q. Zafar, R. Akram, Kh.S. Karimov, T.A. Khan, M. Farooq, M.M. Tahir

Abstract:

In this study we present the effect of elevated temperatures from 300K to 400K on the electrical properties of copper Phthalocyanine (CuPc) based organic field effect transistors (OFET). Thin films of organic semiconductor CuPc (40nm) and semitransparent Al (20nm) were deposited in sequence, by vacuum evaporation on a glass substrate with previously deposited Ag source and drain electrodes with a gap of 40 μm. Under resistive mode of operation, where gate was suspended it was observed that drain current of this organic field effect transistor (OFET) show an increase with temperature. While in grounded gate condition metal (aluminum) – semiconductor (Copper Phthalocyanine) Schottky junction dominated the output characteristics and device showed switching effect from low to high conduction states like Zener diode at higher bias voltages. This threshold voltage for switching effect has been found to be inversely proportional to temperature and shows an abrupt decrease after knee temperature of 360K. Change in dynamic resistance (Rd = dV/dI) with respect to temperature was observed to be -1%/K.

Keywords: Copper Phthalocyanine, Metal-Semiconductor Schottky Junction, Organic Field Effect Transistor, Switching effect, Temperature Sensor

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Authors: Ki-Young Kim, Jae-Ho Lim, Deok-Min Kim, Seok-Yoon Kim

Abstract:

Average current analysis checking the impact of current flow is very important to guarantee the reliability of semiconductor systems. As semiconductor process technologies improve, the coupling capacitance often become bigger than self capacitances. In this paper, we propose an analytic technique for analyzing average current on interconnects in multi-conductor structures. The proposed technique has shown to yield the acceptable errors compared to HSPICE results while providing computational efficiency.

Keywords: current moment, interconnect modeling, reliability analysis, worst-case switching

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Authors: T. P. Lu, B. N. Hwang, T. Z. Liou, Y. L. Lin

Abstract:

Developing a supply chain management (SCM) system is costly, but important. However, because of its complicated nature, not many of such projects are considered successful. Few research publications directly relate to key success factors (KSFs) for implementing a SCM system. Motivated by the above, this research proposes a hierarchy of KSFs for SCM system implementation in the semiconductor industry by using a two-step approach. First, the literature review indicates the initial hierarchy. The second step includes a focus group approach to finalize the proposed KSF hierarchy by extracting valuable experiences from executives and managers that actively participated in a project, which successfully establish a seamless SCM integration between the world's largest semiconductor foundry manufacturing company and the world's largest assembly and testing company. Future project executives may refer the resulting KSF hierarchy as a checklist for SCM system implementation in semiconductor or related industries.

Keywords: Focus group, key success factors, supply chain management, semiconductor industry.

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Authors: Ingy A. El-Khouly, Khaled S. El-Kilany, Aziz E. El-Sayed

Abstract:

The process of wafer fabrication is arguably the most technologically complex and capital intensive stage in semiconductor manufacturing. This large-scale discrete-event process is highly reentrant, and involves hundreds of machines, restrictions, and processing steps. Therefore, production control of wafer fabrication facilities (fab), specifically scheduling, is one of the most challenging problems that this industry faces. Dispatching rules have been extensively applied to the scheduling problems in semiconductor manufacturing. Moreover, lot release policies are commonly used in this manufacturing setting to further improve the performance of such systems and reduce its inherent variability. In this work, simulation is used in the scheduling of re-entrant flow shop manufacturing systems with an application in semiconductor wafer fabrication; where, a simulation model has been developed for the Intel Five-Machine Six Step Mini-Fab using the ExtendTM simulation environment. The Mini-Fab has been selected as it captures the challenges involved in scheduling the highly re-entrant semiconductor manufacturing lines. A number of scenarios have been developed and have been used to evaluate the effect of different dispatching rules and lot release policies on the selected performance measures. Results of simulation showed that the performance of the Mini-Fab can be drastically improved using a combination of dispatching rules and lot release policy.

Keywords: Dispatching rules, lot release policy, re-entrant flowshop, semiconductor manufacturing.

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Authors: Djilani Kobibi Youcef Islam, Hadjeri Samir, Djehaf Mohamed Abdeldjalil

Abstract:

The Flexible AC Transmission System (FACTS) technology is a new advanced solution that increases the reliability and provides more flexibility, controllability, and stability of a power system. The Unified Power Flow Controller (UPFC), as the most versatile FACTS device for regulating power flow, is able to control respectively transmission line real power, reactive power, and node voltage. The main purpose of this paper is to analyze the effect of the UPFC on the load flow, the power losses, and the voltage stability using NEPLAN software modules, Newton-Raphson load flow is used for the power flow analysis and the modal analysis is used for the study of the voltage stability. The simulation was carried out on the IEEE 14-bus test system.

Keywords: FACTS, load flow, modal analysis, UPFC, voltage stability.

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Authors: Won-Ho Kim, Chang-Ho Hyun, Moon-Jung Kim

Abstract:

In this paper, zigbee communication based wireless energy surveillance system is presented. The proposed system consists of multiple energy surveillance devices and an energy surveillance monitor. Each different standby power-off value of electric device is set automatically by using learning function of energy surveillance device. Thus adaptive standby power-off function provides user convenience and it maximizes the energy savings. Also, power consumption monitoring function is helpful to reduce inefficient energy consumption in home. The zigbee throughput simulator is designed to evaluate minimum transmission power and maximum allowable information quantity in the proposed system. The test result of prototype has been satisfied all the requirements. The proposed system has confirmed that can be used as an intelligent energy surveillance system for energy savings in home or office.

Keywords: Energy monitoring system, Energy surveillance system, Energy sensor network, Energy savings.

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Authors: Darshana Thomas, Edward Wilkie, James Irvine

Abstract:

The Internet of things (IoT) is currently a highly researched topic, especially within the context of the smart home. These are small sensors that are capable of gathering data and transmitting it to a server. The majority of smart home products use protocols such as ZigBee or Bluetooth Low Energy (BLE). As these small sensors are increasing in number, the need to implement these with much more capable and ubiquitous transmission technology is necessary. The high power consumption is the reason that holds these small sensors back from using other protocols such as the most ubiquitous form of communication, WiFi. Comparing the power consumption of existing transmission technologies to one with WiFi inbuilt, would provide a better understanding for choosing between these technologies. We have developed a small IoT device with WiFi capability and proven that it is much more efficient than the first protocol, 433 MHz. We extend our work in this paper and compare WiFi power consumption with the other most widely used protocol BLE. The experimental results in this paper would conclude whether the developed prototype is capable in terms of power consumption to replace the existing protocol BLE with WiFi.

Keywords: Bluetooth, internet of things, power consumption, WiFi.

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Authors: Jörg Lenhardt, Wolfram Schiffmann, Jörg Keller

Abstract:

While the feature sizes of recent Complementary Metal Oxid Semiconductor (CMOS) devices decrease the influence of static power prevails their energy consumption. Thus, power savings that benefit from Dynamic Frequency and Voltage Scaling (DVFS) are diminishing and temporal shutdown of cores or other microchip components become more worthwhile. A consequence of powering off unused parts of a chip is that the relative difference between idle and fully loaded power consumption is increased. That means, future chips and whole server systems gain more power saving potential through power-aware load balancing, whereas in former times this power saving approach had only limited effect, and thus, was not widely adopted. While powering off complete servers was used to save energy, it will be superfluous in many cases when cores can be powered down. An important advantage that comes with that is a largely reduced time to respond to increased computational demand. We include the above developments in a server power model and quantify the advantage. Our conclusion is that strategies from datacenters when to power off server systems might be used in the future on core level, while load balancing mechanisms previously used at core level might be used in the future at server level.

Keywords: Power efficiency, static power consumption, dynamic power consumption, CMOS.

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Authors: R. Rezaeipour

Abstract:

One of the key aspects of power quality improvement in power system is the mitigation of voltage sags/swells and flicker. Custom power devices have been known as the best tools for voltage disturbances mitigation as well as reactive power compensation. Dynamic Voltage Restorer (DVR) which is the most efficient and effective modern custom power device can provide the most commercial solution to solve several problems of power quality in distribution networks. This paper deals with analysis and simulation technique of DVR based on instantaneous power theory which is a quick control to detect signals. The main purpose of this work is to remove three important disturbances including voltage sags/swells and flicker. Simulation of the proposed method was carried out on two sample systems by using Matlab software environment and the results of simulation show that the proposed method is able to provide desirable power quality in the presence of wide range of disturbances.

Keywords: DVR, Power quality, Voltage sags, Voltage swells, Flicker.

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Authors: Batel Noureddine, Mehenni Mohamed, Kouadik Smain

Abstract:

In a transcutanious inductive coupling of a biomedical implant, a new formula is given for the study of the Radio Frequency power attenuation by the biological tissue. The loss of the signal power is related to its interaction with the biological tissue and the composition of this one. A confrontation with the practical measurements done with a synthetic muscle into a Faraday cage, allowed a checking of the obtained theoretical results. The supply/data transfer systems used in the case of biomedical implants, can be well dimensioned by taking in account this type of power attenuation.

Keywords: Biological tissue, coupled coils, implanted device, power attenuation.

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Authors: Samrat Vikramaditya Tiwari, Atul Sewaiwar, Yeon-Ho Chung

Abstract:

Device-to-device (D2D) communication is considered a promising technique to provide wireless peer-to-peer communication services. Due to increasing demand on mobile services, available spectrum for radio frequency (RF) based communications becomes scarce. Recently, visible light communications (VLC) has evolved as a high speed wireless data transmission technology for indoor environments with abundant available bandwidth. In this paper, a novel VLC based D2D communication that provides wireless peer-to-peer communication is proposed. Potential low operating power devices for an efficient D2D communication over increasing distance of separation between devices is analyzed. Optical repeaters (OR) are also proposed to enhance the performance in an environment where direct D2D communications yield degraded performance. Simulation results show that VLC plays an important role in providing efficient D2D communication up to a distance of 1 m between devices. It is also found that the OR significantly improves the coverage distance up to 3.5 m.

Keywords: Visible light communication, light emitting diode, device-to-device, optical repeater.

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Authors: Youngji Yoo, Seung Hwan Park, Daewoong An, Sung-Shick Kim, Jun-Geol Baek

Abstract:

The yield management system is very important to produce high-quality semiconductor chips in the semiconductor manufacturing process. In order to improve quality of semiconductors, various tests are conducted in the post fabrication (FAB) process. During the test process, large amount of data are collected and the data includes a lot of information about defect. In general, the defect on the wafer is the main causes of yield loss. Therefore, analyzing the defect data is necessary to improve performance of yield prediction. The wafer bin map (WBM) is one of the data collected in the test process and includes defect information such as the fail bit patterns. The fail bit has characteristics of spatial point patterns. Therefore, this paper proposes the feature extraction method using the spatial point pattern analysis. Actual data obtained from the semiconductor process is used for experiments and the experimental result shows that the proposed method is more accurately recognize the fail bit patterns.

Keywords: Semiconductor, wafer bin map (WBM), feature extraction, spatial point patterns, contour map.

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Authors: A. Alghanim, J. Benedikt, P. J. Tasker

Abstract:

The increasing demand for higher data rates in wireless communication systems has led to the more effective and efficient use of all allocated frequency bands. In order to use the whole bandwidth at maximum efficiency, one needs to have RF power amplifiers with a higher linear level and memory-less performance. This is considered to be a major challenge to circuit designers. In this thesis the linearity and memory are studied and examined via the behavior of the intermodulation distortion (IMD). A major source of the in-band distortion can be shown to be influenced by the out-of-band impedances presented at either the input or the output of the device, especially those impedances terminated the low frequency (IF) components. Thus, in order to regulate the in-band distortion, the out of-band distortion must be controllable. These investigations are performed on a 12W LDMOS device characterised at 2.1 GHz within a purpose built, high-power measurement system.

Keywords: Low Frequency Memory, IntermodulationDistortion (IMD).

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Authors: Venkata Reddy Kota

Abstract:

These days, the industrial trend is moving away from heavy and bulky passive components to power converter systems that use more and more semiconductor elements. Also, it is difficult to connect the traditional converters to the high and medium voltage. For these reasons, a new family of multilevel inverters has appeared as a solution for working with higher voltage levels. Different modulation topologies like Sinusoidal Pulse Width Modulation (SPWM), Selective Harmonic Elimination Pulse Width Modulation (SHE-PWM) are available for multilevel inverters. In this work, different hybrid modulation techniques which are combination of fundamental frequency modulation and multilevel sinusoidal-modulation are compared. The main characteristic of these modulations are reduction of switching losses with good harmonic performance and balanced power loss dissipation among the device. The proposed hybrid modulation schemes are developed and simulated in Matlab/Simulink for cascaded H-bridge inverter. The results validate the applicability of the proposed schemes for cascaded multilevel inverter.

Keywords: Hybrid PWM techniques, Cascaded Multilevel Inverters, Switching loss minimization.

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Authors: Shigenori Togashi, Yukako Asano

Abstract:

We developed an effective microfluidic device for photoreactions with low reflectance and good heat conductance. The performance of this microfluidic device was tested by carrying out a photoreactive synthesis of benzopinacol and acetone from benzophenone and 2-propanol. The yield reached 36% with an irradiation time of 469.2 s and was improved by more than 30% when compared to the values obtained by the batch method. Therefore, the microfluidic device was found to be effective for improving the yields of photoreactions.

Keywords: Microfluidic device, Photoreaction, Benzophenone, Black Aluminum Oxide, Detection, Yield Improvement.

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Authors: Hee-Guk Chae, Bo-Bae Song, Kyoung-Il Do, Jeong-Yun Seo, Yong-Seo Koo

Abstract:

In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage.

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Authors: Kyoung Kun Lee, Soongyu Kwon, Jong Tae Kim

Abstract:

An embedded system for SEU(single event upset) test needs to be designed to prevent system failure by high-energy particles during measuring SEU. SEU is a phenomenon in which the data is changed temporary in semiconductor device caused by high-energy particles. In this paper, we present an embedded system for SRAM(static random access memory) SEU test. SRAMs are on the DUT(device under test) and it is separated from control board which manages the DUT and measures the occurrence of SEU. It needs to have considerations for preventing system failure while managing the DUT and making an accurate measurement of SEUs. We measure the occurrence of SEUs from five different SRAMs at three different cyclotron beam energies 30, 35, and 40MeV. The number of SEUs of SRAMs ranges from 3.75 to 261.00 in average.

Keywords: embedded system, single event upset, SRAM

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Authors: W. Adi, Khaled E. A. Negm, A. Mabrouk, H. Ghraieb

Abstract:

In the current study we present a system that is capable to deliver proxy based differentiated service. It will help the carrier service node to sell a prepaid service to clients and limit the use to a particular mobile device or devices for a certain time. The system includes software and hardware architecture for a mobile device with moderate computational power, and a secure protocol for communication between it and its carrier service node. On the carrier service node a proxy runs on a centralized server to be capable of implementing cryptographic algorithms, while the mobile device contains a simple embedded processor capable of executing simple algorithms. One prerequisite is needed for the system to run efficiently that is a presence of Global Trusted Verification Authority (GTVA) which is equivalent to certifying authority in IP networks. This system appears to be of great interest for many commercial transactions, business to business electronic and mobile commerce, and military applications.

Keywords: Mobile Device Security, Identity Authentication, Mobile Commerce Security.

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Authors: Davit Mirzoyan, Ararat Khachatryan

Abstract:

A process corner monitoring circuit (PCMC) is presented in this work. The circuit generates a signal, the logical value of which depends on the process corner only. The signal can be used in both digital and analog circuits for testing and compensation of process variations (PV). The presented circuit uses only metal-oxide-semiconductor (MOS) transistors, which allow increasing its detection accuracy, decrease power consumption and area. Due to its simplicity the presented circuit can be easily modified to monitor parametrical variations of only n-type and p-type MOS (NMOS and PMOS, respectively) transistors, resistors, as well as their combinations. Post-layout simulation results prove correct functionality of the proposed circuit, i.e. ability to monitor the process corner (equivalently die-to-die variations) even in the presence of within-die variations.

Keywords: Detection, monitoring, process corner, process variation.

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Authors: N. Shen, Z. X. Chen, K.D. Buddharaju, H. M. Chua, X. Li, N. Singh, G.Q Lo, D.-L. Kwong

Abstract:

In this paper, we present a vertical wire NMOS device fabricated using CMOS compatible processes. The impact of temperature on various device parameters is investigated in view of usual increase in surrounding temperature with device density.

Keywords: Gate-all-around, temperature dependence, silicon nanowire

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Authors: R. K. Singh, P.K.Jain

Abstract:

Operating a device at high power and high frequency is a major problem because wall losses greatly reduce the efficiency of the device. In the present communication, authors analytically analyzed the dependence of ohmic/RF efficiency, the fraction of output power with respect to the total power generated, of gyrotron cavity structure on the conductivity of copper for the second harmonic TE0,6 mode. This study shows a rapid fall in the RF efficiency as the quality (conductivity) of copper degrades. Starting with an RF efficiency near 40% at the conductivity of ideal copper (5.8 x 107 S/m), the RF efficiency decreases (upto 8%) as the copper quality degrades. Assuming conductivity half that of ideal copper the RF efficiency as a function of diffractive quality factor, Qdiff, has been studied. Here the RF efficiency decreases rapidly with increasing diffractive Q. Ohmic wall losses as a function of frequency for 460 GHz gyrotron cavity excited in TE0,6 mode has also been analyzed. For 460 GHz cavity, the extracted power is reduced to 32% of the generated power due to ohmic losses in the walls of the cavity.

Keywords: Diffractive quality factor, Gyrotron, Ohmic wall losses, Open cavity resonator, RF Efficiency.

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Authors: F. Hadjaj, A. Belghachi, A. Halmaoui, M. Belhadj, H. Mazouz

Abstract:

A laser is essentially an optical oscillator consisting of a resonant cavity, an amplifying medium and a pumping source. In semiconductor diode lasers, the cavity is created by the boundary between the cleaved face of the semiconductor crystal and air, and has reflective properties as a result of the differing refractive indices of the two media. For a GaAs-air interface a reflectance of 0.3 is typical and therefore the length of the semiconductor junction forms the resonant cavity. To prevent light being emitted in unwanted directions from the junction, sides perpendicular to the required direction are roughened. The objective of this work is to simulate the optical resonator Fabry-Perot and explore its main characteristics, such as FSR, finesse, linewidth, transmission and so on, that describe the performance of resonator.

Keywords: Fabry-Perot Resonator, laser diode.

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Authors: Ali Safari, Pejman Hosseiniun, Iman Rahbari, Mohamad Reza Kalhor

Abstract:

The semiconductor industry is placing an increased emphasis on emerging materials and devices that may provide improved performance, or provide novel functionality for devices. Recently, graphene, as a true two-dimensional carbon material, has shown fascinating applications in electronics. In this paper detailed discussions are introduced for possible applications of grapheme Transistor in RF and digital devices.

Keywords: Graphene, GFET, RF, Digital.

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Authors: Vincent King Soon Wong, Hong Seng Ng, Florinna Sim

Abstract:

Negative Bias Temperature Instability (NBTI) is one of the critical degradation mechanisms in semiconductor device reliability that causes shift in the threshold voltage (Vth). However, thorough understanding of this reliability failure mechanism is still unachievable due to a recovery characteristic known as NBTI recovery. This paper will demonstrate the severity of NBTI recovery as well as one of the effective methods used to mitigate, which is the minimization of measurement system delays. Comparison was done in between two measurement systems that have significant differences in measurement delays to show how NBTI recovery causes result deviations and how fast measurement systems can mitigate NBTI recovery. Another method to minimize NBTI recovery without the influence of measurement system known as Fast Wafer Level Reliability (FWLR) NBTI was also done to be used as reference.

Keywords: Fast vs slow BTI, Fast wafer level reliability, Negative bias temperature instability, NBTI measurement system, metal-oxide-semiconductor field-effect transistor, MOSFET, NBTI recovery, reliability.

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Authors: Muhammad Tahir, Muhammad H. Sayyad, Dil N. Khan, Fazal Wahab

Abstract:

Herein, the organic semiconductor methyl orange (MO), is investigated for the first time for its electronic applications. For this purpose, Al/MO/n-Si heterojunction is fabricated through economical cheap and simple “drop casting” technique. The currentvoltage (I-V) measurements of the device are made at room temperature under dark conditions. The I-V characteristics of Al/MO/n-Si junction exhibits asymmetrical and rectifying behavior that confirms the formation of diode. The diode parameters such as rectification ratio (RR), turn on voltage (Vturn on), reverse saturation current (I0), ideality factor (n), barrier height ( b f ), series resistance (Rs) and shunt resistance (Rsh) are determined from I-V curves using Schottky equations. These values of these parameters are also extracted and verified by applying Cheung’s functions. The conduction mechanisms are explained from the forward bias I-V characteristics using the power law.

Keywords: Electrical properties, Organic/inorganic heterojunction diode, Methyl Orange, Cheungs Functions

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Authors: Seung Hwan Park, Cheng-Sool Park, Jun Seok Kim, Youngji Yoo, Daewoong An, Jun-Geol Baek

Abstract:

Depending on the big data analysis becomes important, yield prediction using data from the semiconductor process is essential. In general, yield prediction and analysis of the causes of the failure are closely related. The purpose of this study is to analyze pattern affects the final test results using a die map based clustering. Many researches have been conducted using die data from the semiconductor test process. However, analysis has limitation as the test data is less directly related to the final test results. Therefore, this study proposes a framework for analysis through clustering using more detailed data than existing die data. This study consists of three phases. In the first phase, die map is created through fail bit data in each sub-area of die. In the second phase, clustering using map data is performed. And the third stage is to find patterns that affect final test result. Finally, the proposed three steps are applied to actual industrial data and experimental results showed the potential field application.

Keywords: Die-Map Clustering, Feature Extraction, Pattern Recognition, Semiconductor Manufacturing Process.

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Authors: Muhibul Haque Bhuyan

Abstract:

Spintronic, also termed spin electronics or spin transport electronics, is a kind of new technology, which exploits the two fundamental degrees of freedom- spin-state and charge-state of electrons to enhance the operational speed for the data storage and transfer efficiency of the device. Thus, it seems an encouraging technology to combat most of the prevailing complications in orthodox electron-based devices. This novel technology possesses the capacity to mix the semiconductor microelectronics and magnetic devices’ functionalities into one integrated circuit. Traditional semiconductor microelectronic devices use only the electronic charge to process the information based on binary numbers, 0 and 1. Due to the incessant shrinking of the transistor size, we are reaching the final limit of 1 nm or so. At this stage, the fabrication and other device operational processes will become challenging as the quantum effect comes into play. In this situation, we should find an alternative future technology, and spintronic may be such technology to transfer and store information. This review article provides a detailed discussion of the spintronic technology: fundamentals, materials, devices, circuits, challenges, and current research trends. At first, the fundamentals of spintronics technology are discussed. Then types, properties, and other issues of the spintronic materials are presented. After that, fabrication and working principles, as well as application areas and advantages/disadvantages of spintronic devices and circuits, are explained. Finally, the current challenges, current research areas, and prospects of spintronic technology are highlighted. This is a new paradigm of electronic cum magnetic devices built on the charge and spin of the electrons. Modern engineering and technological advances in search of new materials for this technology give us hope that this would be a very optimistic technology in the upcoming days.

Keywords: Spintronic technology, spin, charge, magnetic devices, spintronic devices, spintronic materials.

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Authors: Abdulatif Abdusalam, Mohamed Shaban

Abstract:

This paper introduces Interfacing and Replication of electronic tools based on the MATLAB/ SIMULINK mock-up package. Mock-up components contain dc-dc converters, power issue rectifiers, motivation machines, dc gear, synchronous gear, and more entire systems. The power issue rectifier model includes solid state device models. The tools provide clear-cut structures and mock-up of complex energy systems, connecting with power electronic machines.

Keywords: Power electronics, Machine, Matlab/Simulink.

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