Mohamad Reza Kalhor

Publications

2 Graphene Based Electronic Device

Authors: Pejman Hosseiniun, Ali Safari, Iman Rahbari, Mohamad Reza Kalhor

Abstract:

The semiconductor industry is placing an increased emphasis on emerging materials and devices that may provide improved performance, or provide novel functionality for devices. Recently, graphene, as a true two-dimensional carbon material, has shown fascinating applications in electronics. In this paper detailed discussions are introduced for possible applications of grapheme Transistor in RF and digital devices.

Keywords: Graphene, Digital, GFET

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1 Low Power CNFET SRAM Design

Authors: Rose Shayeghi, Pejman Hosseiniun, Iman Rahbari, Mohamad Reza Kalhor

Abstract:

CNFET has emerged as an alternative material to silicon for high performance, high stability and low power SRAM design in recent years. SRAM functions as cache memory in computers and many portable devices. In this paper, a new SRAM cell design based on CNFET technology is proposed. The proposed SRAM cell design for CNFET is compared with SRAM cell designs implemented with the conventional CMOS and FinFET in terms of speed, power consumption, stability, and leakage current. The HSPICE simulation and analysis show that the dynamic power consumption of the proposed 8T CNFET SRAM cell’s is reduced about 48% and the SNM is widened up to 56% compared to the conventional CMOS SRAM structure at the expense of 2% leakage power and 3% write delay increase.

Keywords: low power, SRAM cell, CNFET, HSPICE

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Abstracts

1 Low Power CNFET SRAM Design

Authors: Rose Shayeghi, Pejman Hosseiniun, Iman Rahbari, Mohamad Reza Kalhor

Abstract:

CNFET has emerged as an alternative material to silicon for high performance, high stability and low power SRAM design in recent years. SRAM functions as cache memory in computers and many portable devices. In this paper, a new SRAM cell design based on CNFET technology is proposed. The proposed SRAM cell design for CNFET is compared with SRAM cell designs implemented with the conventional CMOS and FinFET in terms of speed, power consumption, stability, and leakage current. The HSPICE simulation and analysis show that the dynamic power consumption of the proposed 8T CNFET SRAM cell’s is reduced about 48% and the SNM is widened up to 56% compared to the conventional CMOS SRAM structure at the expense of 2% leakage power and 3% write delay increase.

Keywords: low power, SRAM cell, CNFET, HSPICE

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