Jeong-Yun Seo

Publications

2 PSRR Enhanced LDO Regulator Using Noise Sensing Circuit

Authors: Yong-Seo Koo, Hee-Guk Chae, Jeong-Yun Seo, Min-ju Kwon, Chae-won Kim

Abstract:

In this paper, we presented the LDO (low-dropout) regulator which enhanced the PSRR by applying the constant current source generation technique through the BGR (Band Gap Reference) to form the noise sensing circuit. The current source through the BGR has a constant current value even if the applied voltage varies. Then, the noise sensing circuit, which is composed of the current source through the BGR, operated between the error amplifier and the pass transistor gate of the LDO regulator. As a result, the LDO regulator has a PSRR of -68.2 dB at 1k Hz, -45.85 dB at 1 MHz and -45 dB at 10 MHz. the other performance of the proposed LDO was maintained at the same level of the conventional LDO regulator.

Keywords: LDO regulator, noise sensing circuit, current reference, pass transistor

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1 A Study on ESD Protection Circuit Applying Silicon Controlled Rectifier-Based Stack Technology with High Holding Voltage

Authors: Yong-Seo Koo, Hee-Guk Chae, Bo-Bae Song, Kyoung-Il Do, Jeong-Yun Seo

Abstract:

In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.

Keywords: holding voltage, ESD, SCR, latch-up, power clamp

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Abstracts

3 A Study on ESD Protection Circuit Applying Silicon Controlled Rectifier-Based Stack Technology with High Holding Voltage

Authors: Yong-Seo Koo, Hee-Guk Chae, Bo-Bae Song, Kyoung-Il Do, Jeong-Yun Seo

Abstract:

In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.

Keywords: holding voltage, ESD, SCR, latch-up, power clamp

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2 PSRR Enhanced LDO Regulator Using Noise Sensing Circuit

Authors: Yong-Seo Koo, Hee-Guk Chae, Jeong-Yun Seo, Min-ju Kwon, Chae-won Kim

Abstract:

In this paper, we presented the LDO (low-dropout) regulator which enhanced the PSRR by applying the constant current source generation technique through the BGR (Band Gap Reference) to form the noise sensing circuit. The current source through the BGR has a constant current value even if the applied voltage varies. Then, the noise sensing circuit, which is composed of the current source through the BGR, operated between the error amplifier and the pass transistor gate of the LDO regulator. As a result, the LDO regulator has a PSRR of -68.2 dB at 1k Hz, -45.85 dB at 1 MHz and -45 dB at 10 MHz. the other performance of the proposed LDO was maintained at the same level of the conventional LDO regulator.

Keywords: LDO regulator, noise sensing circuit, current reference, pass transistor

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1 Low Trigger Voltage Silicon Controlled Rectifier Stacking Structure with High Holding Voltage for High Voltage Applications

Authors: Yong-Seo Koo, Hee-Guk Chae, Kyoung-Il Do, Jeong-Yun Seo, Jun-Geol Park

Abstract:

A SCR stacking structure is proposed to have improved Latch-up immunity. In comparison with conventional SCR (Silicon Controlled Rectifier), the proposed Electrostatic Discharge (ESD) protection circuit has a lower trigger characteristic by using the LVTSCR (Low Voltage Trigger) structure. Also the proposed ESD protection circuit has improved Holding Voltage Characteristic by using N-stack technique. These characteristics enable to have latch-up immunity in operating conditions. The simulations are accomplished by using the Synopsys TCAD. It has a trigger voltage of 8.9V and a holding voltage of 1.8V in a single structure. And when applying the stack technique, 2-stack has the holding voltage of 3.8V and 3-stack has the holding voltage of 5.1 V.

Keywords: silicon controlled rectifier (SCR), latch-up, power clamp, electrostatic discharge (ESD), low voltage trigger silicon controlled rectifier (LVTSCR), MVTSCR

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