D. Mukhopadhyay


2 An Experimental Investigation on the Behavior of Pressure Tube under Symmetrical and Asymmetrical Heating Conditions in an Indian PHWR

Authors: Ashwini K. Yadav, Ravi Kumar, Akhilesh Gupta, P. Majumdar, B. Chatterjee, D. Mukhopadhyay


Thermal behavior of fuel channel under loss of coolant accident (LOCA) is a major concern for nuclear reactor safety. LOCA along with failure of emergency cooling water system (ECC) may leads to mechanical deformations like sagging and ballooning. In order to understand the phenomenon an experiment has been carried out using 19 pin fuel element simulator. Main purpose of the experiment was to trace temperature profiles over the pressure tube, calandria tube and clad tubes of Indian Pressurized Heavy Water Reactor (IPHWR) under symmetrical and asymmetrical heat-up conditions. For simulating the fully voided scenario, symmetrical heating of pressure was carried out by injecting 13.2 KW (2 % of nominal power) to all the 19 pins and the temperatures of pressure tube, calandria tube and clad tubes were measured. During symmetrical heating the sagging of fuel channel was initiated at 460 °C and the highest temperature attained by PT was 650 °C . The decay heat from clad tubes was dissipated to moderator mainly by radiation and natural convection. The highest temperature of 680 °C was observed over the outer ring of clad tubes of fuel simulator. Again, to simulate partially voided condition, asymmetrical heating of pressure was carried out by supplying 8.0 kW power to upper 8 pins of fuel simulator and temperature profiles were measured. Along the circumference of pressure tube (PT) the highest temperature difference of 320 °C was observed, which highlights the magnitude of thermal stresses under partially voided conditions.

Keywords: ballooning, LOCA, ECCS, PHWR, channel heat-up, pressure tube, calandria tube

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1 A 1.2-ns16×16-Bit Binary Multiplier Using High Speed Compressors

Authors: A. Dandapat, S. Ghosal, P. Sarkar, D. Mukhopadhyay


For higher order multiplications, a huge number of adders or compressors are to be used to perform the partial product addition. We have reduced the number of adders by introducing special kind of adders that are capable to add five/six/seven bits per decade. These adders are called compressors. Binary counter property has been merged with the compressor property to develop high order compressors. Uses of these compressors permit the reduction of the vertical critical paths. A 16×16 bit multiplier has been developed using these compressors. These compressors make the multipliers faster as compared to the conventional design that have been used 4-2 compressors and 3-2 compressors.

Keywords: low power, Binary multiplier, Compressors, Counter, Column adder

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