D. -L. Kwong

Publications

3 Switching Behaviors of HfO2/NiSix Based RRAM

Authors: Z. X. Chen, Z. Fang, X. P. Wang, G. -Q. Lo, D. -L. Kwong, Y. H. Wu

Abstract:

This paper presents a study of Ni-silicides as the bottom electrode of HfO2-based RRAM. Various silicidation conditions were used to obtain different Ni concentrations within the Ni-silicide bottom electrode, namely Ni2Si, NiSi, and NiSi2. A 10nm HfO2 switching material and 50nm TiN top electrode was then deposited and etched into 500nm by 500nm square RRAM cells. Cell performance of the Ni2Si and NiSi cells were good, while the NiSi2 cell could not switch reliably, indicating that the presence of Ni in the bottom electrode is important for good switching.

Keywords: NiSi, HfO2-based, Ni-silicide, resistive RAM (RRAM)

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2 Impact of Process Variations on the Vertical Silicon Nanowire Tunneling FET (TFET)

Authors: Z. X. Chen, T. S. Phua, X. P. Wang, G. -Q. Lo, D. -L. Kwong

Abstract:

This paper presents device simulations on the vertical silicon nanowire tunneling FET (VSiNW TFET). Simulations show that a narrow nanowire and thin gate oxide is required for good performance, which is expected even for conventional MOSFETs. The gate length also needs to be more than the nanowire diameter to prevent short channel effects. An effect more unique to TFET is the need for abrupt source to channel junction, which is shown to improve the performance. The ambipolar effect suppression by reducing drain doping concentration is also explored and shown to have little or no effect on performance.

Keywords: Device Simulation, MEDICI, tunneling FET (TFET), vertical silicon nanowire

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1 Fabrication and Characterization of Poly-Si Vertical Nanowire Thin Film Transistor

Authors: N. Shen, T. T. Le, H. Y. Yu, Z. X. Chen, K. T. Win, N. Singh, G. Q. Lo, D. -L. Kwong

Abstract:

In this paper, we present a vertical nanowire thin film transistor with gate-all-around architecture, fabricated using CMOS compatible processes. A novel method of fabricating polysilicon vertical nanowires of diameter as small as 30 nm using wet-etch is presented. Both n-type and p-type vertical poly-silicon nanowire transistors exhibit superior electrical characteristics as compared to planar devices. On a poly-crystalline nanowire of 30 nm diameter, high Ion/Ioff ratio of 106, low drain-induced barrier lowering (DIBL) of 50 mV/V, and low sub-threshold slope SS~100mV/dec are demonstrated for a device with channel length of 100 nm.

Keywords: thin-film transistor (TFT), Nanowire (NW), Gate-all-around (GAA), polysilicon (poly-Si)

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