Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 2

Encoder Related Publications

2 A High-Speed Multiplication Algorithm Using Modified Partial Product Reduction Tree

Authors: P. Asadee

Abstract:

Multiplication algorithms have considerable effect on processors performance. A new high-speed, low-power multiplication algorithm has been presented using modified Dadda tree structure. Three important modifications have been implemented in inner product generation step, inner product reduction step and final addition step. Optimized algorithms have to be used into basic computation components, such as multiplication algorithms. In this paper, we proposed a new algorithm to reduce power, delay, and transistor count of a multiplication algorithm implemented using low power modified counter. This work presents a novel design for Dadda multiplication algorithms. The proposed multiplication algorithm includes structured parts, which have important effect on inner product reduction tree. In this paper, a 1.3V, 64-bit carry hybrid adder is presented for fast, low voltage applications. The new 64-bit adder uses a new circuit to implement the proposed carry hybrid adder. The new adder using 80 nm CMOS technology has been implemented on 700 MHz clock frequency. The proposed multiplication algorithm has achieved 14 percent improvement in transistor count, 13 percent reduction in delay and 12 percent modification in power consumption in compared with conventional designs.

Keywords: CMOS, Encoder, Counter, adder, Dadda tree

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1 Development of Low-cost OCDMA Encoder Based On Arrayed Waveguide Gratings(AWGs) and Optical Switches

Authors: Mohammad Syuhaimi Ab-Rahman, Boon Chuan Ng, Norshilawati Mohamad Ibrahim, Sahbudin Shaari

Abstract:

This paper describes the development of a 16-ports optical code division multiple access (OCDMA) encoder prototype based on Arrayed Waveguide Grating (AWG) and optical switches. It is potentially to provide a high security for data transmission due to all data will be transmitted in binary code form. The output signals from AWG are coded with a binary code that given to an optical switch before it signal modulate with the carrier and transmitted to the receiver. The 16-ports encoder used 16 double pole double throw (DPDT) toggle switches to control the polarization of voltage source from +5 V to -5 V for 16 optical switches. When +5 V is given, the optical switch will give code '1' and vice versa. The experimental results showed the insertion loss, crosstalk, uniformity, and optical signal-noise-ratio (OSNR) for the developed prototype are <12 dB, 9.77 dB, <1.63dB, and ≥20dB.

Keywords: OCDMA, Encoder, Optical switch, AWG

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