Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 10

Publications

10 CMOS-Compatible Plasmonic Nanocircuits for On-Chip Integration

Authors: Shiyang Zhu, G. Q. Lo, D. L. Kwong

Abstract:

Silicon photonics is merging as a unified platform for driving photonic based telecommunications and for local photonic based interconnect but it suffers from large footprint as compared with the nanoelectronics. Plasmonics is an attractive alternative for nanophotonics. In this work, two CMOS compatible plasmonic waveguide platforms are compared. One is the horizontal metal-insulator-Si-insulator-metal nanoplasmonic waveguide and the other is metal-insulator-Si hybrid plasmonic waveguide. Various passive and active photonic devices have been experimentally demonstrated based on these two plasmonic waveguide platforms.

Keywords: Plasmonics, on-chip integration, Silicon photonics.

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9 ALD HfO2 Based RRAM with Ti Capping

Authors: B. B. Weng, Z. Fang, Z. X. Chen, X. P. Wang, G. Q. Lo, D. L. Kwong

Abstract:

HfOx based Resistive Random Access Memory (RRAM) is one of the most widely studied material stack due to its promising performances as an emerging memory technology. In this work, we systematically investigated the effect of metal capping layer by preparing sample devices with varying thickness of Ti cap and comparing their operating parameters with the help of an Agilent-B1500A analyzer.

Keywords: HfOx, resistive switching, RRAM, metal capping.

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8 Switching Behaviors of TiN/HfOx/Pt Based RRAM

Authors: B. B. Weng, Z. Fang, Z. X. Chen, X. P. Wang, G. Q. Lo, D. L. Kwong

Abstract:

Resistive Random Access Memory (RRAM) had received great amount of attention from various research efforts in recent years, owing to its promising performance as a next generation memory device. In this paper, samples based on TiN/HfOx/Pt stack were prepared and its electrical switching behaviors were characterized and discussed in brief.

Keywords: HfOx, resistive switching, RRAM.

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7 Low Frequency Noise Behavior of Independent Gate Junctionless FinFET

Authors: A. Kamath, Z. X. Chen, C. J. Gu, F. Zheng, X. P. Wang, N. Singh, G-Q. Lo

Abstract:

In this paper we use low frequency noise analysis to understand and map the current conduction path in a multi gate junctionless FinFET.  The device used in this study behaves as a gated resistor and shows excellent short channel effect suppression due to its multi gate structure. Generally for a bulk conduction device like the junctionless device studied in this work, the low frequency noise can be modelled using the mobility fluctuation model; however for this device we can also see the effect of carrier fluctuations on the LFN characteristic. The noise characteristic at different gate bias and also the possible location of the traps is explained.

Keywords: LFN analysis, junctionless, Current conduction path, FinFET.

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6 CMOS-Compatible Deposited Materials for Photonic Layers Integrated above Electronic Integrated Circuit

Authors: Shiyang Zhu, G. Q. Lo, D. L. Kwong

Abstract:

Silicon photonics has generated an increasing interest in recent years mainly for optical communications optical interconnects in microelectronic circuits or bio-sensing applications. The development of elementary passive and active components (including detectors and modulators), which are mainly fabricated on the silicon on insulator platform for CMOS-compatible fabrication, has reached such a performance level that the integration challenge of silicon photonics with microelectronic circuits should be addressed. Since crystalline silicon can only be grown from another silicon crystal, making it impossible to deposit in this state, the optical devices are typically limited to a single layer. An alternative approach is to integrate a photonic layer above the CMOS chip using back-end CMOS fabrication process. In this paper, various materials, including silicon nitride, amorphous silicon, and polycrystalline silicon, for this purpose are addressed.

Keywords: Silicon photonics, CMOS, Integration.

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5 Oxide Based Resistive Random Access Memory Device for High Density Non Volatile Memory Applications

Authors: Z. Fang, X. P. Wang, G. Q. Lo, D. L. Kwong

Abstract:

In this work, we demonstrated vertical RRAM device fabricated at the sidewall of contact hole structures for possible future 3-D stacking integrations. The fabricated devices exhibit polarity dependent bipolar resistive switching with small operation voltage of less than 1V for both set and reset process. A good retention of memory window ~50 times is maintained after 1000s voltage bias.

Keywords: Bipolar switching, non volatile memory, resistive random access memory, 3-D stacking.

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4 Raman Scattering and PL Studies on AlGaN/GaN HEMT Layers on 200 mm Si(111)

Authors: W. Z. Wang, S. Todd, S. B. Dolmanan, K. B. Lee, L. Yuan, H. F. Sun, S. L. Selvaraj, M.Krishnakumar, G. Q. Lo, S. Tripathy

Abstract:

The crystalline quality of the AlGaN/GaN high electron mobility transistor (HEMT) structure grown on a 200 mm silicon substrate has been investigated using UV-visible micro- Raman scattering and photoluminescence (PL). The visible Raman scattering probes the whole nitride stack with the Si substrate and shows the presence of a small component of residual in-plane stress in the thick GaN buffer resulting from a wafer bowing, while the UV micro-Raman indicates a tensile interfacial stress induced at the top GaN/AlGaN/AlN layers. PL shows a good crystal quality GaN channel where the yellow band intensity is very low compared to that of the near-band-edge transition. The uniformity of this sample is shown by measurements from several points across the epiwafer.

Keywords: Raman, photo luminescence, AlGaN/GaN, HEMT.

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3 Low resistivity Hf/Al/Ni/Au Ohmic Contact Scheme to n-Type GaN

Authors: Y. Liu, M. K. Bera, L. M. Kyaw, G. Q. Lo, E. F. Chor

Abstract:

The electrical and structural properties of Hf/Al/Ni/Au (20/100/25/50 nm) ohmic contact to n-GaN are reported in this study. Specific contact resistivities of Hf/Al/Ni/Au based contacts have been investigated as a function of annealing temperature and achieve the lowest value of 1.09´10-6 Ω·cm2 after annealing at 650 oC in vacuum. A detailed mechanism of ohmic contact formation is discussed. By using different chemical analyses, it is anticipated that the formation of Hf-Al-N alloy might be responsible to form low temperature ohmic contacts for the Hf-based scheme to n-GaN.

Keywords: Gallium nitride, ohmic contact, Hafnium

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2 Silicon Nanowire for Thermoelectric Applications: Effects of Contact Resistance

Authors: Y. Li, K. Buddharaju, N. Singh, G. Q. Lo, S. J. Lee

Abstract:

Silicon nanowire (SiNW) based thermoelectric device (TED) has potential applications in areas such as chip level cooling/ energy harvesting. It is a great challenge however, to assemble an efficient device with these SiNW. The presence of parasitic in the form of interfacial electrical resistance will have a significant impact on the performance of the TED. In this work, we explore the effect of the electrical contact resistance on the performance of a TED. Numerical simulations are performed on SiNW to investigate such effects on its cooling performance. Intrinsically, SiNW individually without the unwanted parasitic effect has excellent cooling power density. However, the cooling effect is undermined with the contribution of the electrical contact resistance.

Keywords: Thermoelectric, silicon, nanowire, electrical contact resistance, parasitics.

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1 Fabrication and Characterization of Poly-Si Vertical Nanowire Thin Film Transistor

Authors: N. Shen, T. T. Le, H. Y. Yu, Z. X. Chen, K. T. Win, N. Singh, G. Q. Lo, D. -L. Kwong

Abstract:

In this paper, we present a vertical nanowire thin film transistor with gate-all-around architecture, fabricated using CMOS compatible processes. A novel method of fabricating polysilicon vertical nanowires of diameter as small as 30 nm using wet-etch is presented. Both n-type and p-type vertical poly-silicon nanowire transistors exhibit superior electrical characteristics as compared to planar devices. On a poly-crystalline nanowire of 30 nm diameter, high Ion/Ioff ratio of 106, low drain-induced barrier lowering (DIBL) of 50 mV/V, and low sub-threshold slope SS~100mV/dec are demonstrated for a device with channel length of 100 nm.

Keywords: Nanowire (NW), Gate-all-around (GAA), polysilicon (poly-Si), thin-film transistor (TFT).

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