Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 4

AES Related Publications

4 Improved MARS Ciphering Using a Metamorphic-Enhanced Function

Authors: A. Baith Mohamed, Moataz M. Naguib, Hatem Khater

Abstract:

MARS is a shared-key (symmetric) block cipher algorithm supporting 128-bit block size and a variable key size of between 128 and 448 bits. MARS has a several rounds of cryptographic core that is designed to take advantage of the powerful results for improving security/performance tradeoff over existing ciphers. In this work, a new function added to improve the ciphering process it is called, Meta-Morphic function. This function use XOR, Rotating, Inverting and No-Operation logical operations before and after encryption process. The aim of these operations is to improve MARS cipher process and makes a high confusion criterion for the Ciphertext.

Keywords: Cryptography, Mars, AES, metamorphic, block cipher

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3 AES and ECC Mixed for ZigBee Wireless Sensor Security

Authors: Saif Al-alak, Zuriati Ahmed, Azizol Abdullah, Shamala Subramiam

Abstract:

In this paper, we argue the security protocols of ZigBee wireless sensor network in MAC layer. AES 128-bit encryption algorithm in CCM* mode is secure transferred data; however, AES-s secret key will be break within nearest future. Efficient public key algorithm, ECC has been mixed with AES to rescue the ZigBee wireless sensor from cipher text and replay attack. Also, the proposed protocol can parallelize the integrity function to increase system performance.

Keywords: ZigBee, AES, ECC, Multi-level security

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2 A Low-cost Reconfigurable Architecture for AES Algorithm

Authors: Yibo Fan, Takeshi Ikenaga, Yukiyasu Tsunoo, Satoshi Goto

Abstract:

This paper proposes a low-cost reconfigurable architecture for AES algorithm. The proposed architecture separates SubBytes and MixColumns into two parallel data path, and supports different bit-width operation for this two data path. As a result, different number of S-box can be supported in this architecture. The throughput and power consumption can be adjusted by changing the number of S-box running in this design. Using the TSMC 0.18μm CMOS standard cell library, a very low-cost implementation of 7K Gates is obtained under 182MHz frequency. The maximum throughput is 360Mbps while using 4 S-Box simultaneously, and the minimum throughput is 114Mbps while only using 1 S-Box

Keywords: AES, low cost, reconfigurable architecture

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1 Low Power Circuit Architecture of AES Crypto Module for Wireless Sensor Network

Authors: Juhan Kim, MooSeop Kim, Yongje Choi

Abstract:

Recently, much research has been conducted for security for wireless sensor networks and ubiquitous computing. Security issues such as authentication and data integrity are major requirements to construct sensor network systems. Advanced Encryption Standard (AES) is considered as one of candidate algorithms for data encryption in wireless sensor networks. In this paper, we will present the hardware architecture to implement low power AES crypto module. Our low power AES crypto module has optimized architecture of data encryption unit and key schedule unit which could be applicable to wireless sensor networks. We also details low power design methods used to design our low power AES crypto module.

Keywords: Security, Algorithm, AES, Low Power Crypto Circuit

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