Search results for: resistive random access memory (RRAM)

Authors: Nor Zaidi Haron, Fauziyah Salehuddin, Norsuhaidah Arshad, Sani Irwan Salim

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Resistive random access memories (RRAMs) are one of the main candidates for future computer memories. However, due to their tiny size and immature device technology, the quality of the outgoing RRAM chips is seen as a serious issue. Defective RRAM cells might behave differently than existing semiconductor memories (Dynamic RAM, Static RAM, and Flash), meaning that they are difficult to be detected using existing test schemes. This paper presents an enhanced test scheme, referred to as Programmable Short Write Time (PSWT) that is able to improve the detection of faulty RRAM cells. It is developed by applying multiple weak write operations, each with different time durations. The test circuit embedded in the RRAM chip is made programmable in order to supply different weak write times during testing. The RRAM electrical model is described using Verilog-AMS language and is simulated using HSPICE simulation tools. Simulation results show that the proposed test scheme offers better open-resistive fault detection compared to existing test schemes.

Keywords: memory fault, memory test, design-for-testability, resistive random access memory

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Authors: Chi-Yan Chu, Kai-Chi Chuang, Huang-Chung Cheng

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In this study, the RRAM devices with the TiN/Ti/HfO_x/TiN structure were fabricated, then the electrical characteristics of the devices without annealing and after 400 °C and 500 °C of the furnace annealing (FA) temperature processes were compared. The RRAM devices after the FA’s 400 °C showed the lower forming, set and reset voltages than the other devices without annealing. However, the RRAM devices after the FA’s 500 °C did not show any electrical characteristics because the TiN/Ti/HfO_x/TiN device was oxidized, as shown in the XPS analysis. From these results, the RRAM devices after the FA’s 400 °C showed the best electrical characteristics.

Keywords: RRAM, furnace annealing (FA), forming, set and reset voltages, XPS

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Authors: Peiyuan Guan, Tao Wan, Dewei Chu

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With the flash memory approaching its physical limit, the emerging resistive random-access memory (RRAM) has been considered as one of the most promising candidates for the next-generation non-volatile memory. One selector-one resistor configuration has shown the most promising way to resolve the crosstalk issue without affecting the scalability and high-density integration of the RRAM array. By comparison with other candidates of selectors (such as diodes and nonlinear devices), threshold switching selectors dominated by formation/spontaneous rupture of fragile conductive filaments have been proved to possess low voltages, high selectivity, and ultra-low current leakage. However, the flexibility and transparency of selectors are barely mentioned. Therefore, it is a matter of urgency to develop a selector with highly flexible and transparent properties to assist the application of RRAM for a diversity of memory devices. In this work, threshold switching selectors were designed using a facilely solution-processed fabrication on AgNWs@PDMS composite films, which show high flexibility, transparency and scratch resistance. As-fabricated threshold switching selectors also have revealed relatively high selectivity (~107), low operating voltages (Vth < 1 V) and good switching performance.

Keywords: flexible and transparent, resistive random-access memory, silver nanowires, threshold switching selector

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Authors: Min-Hao Wang, Shih-Chih Chen

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Recently, the merits such as simple structure, low power consumption, and compatibility with complementary metal oxide semiconductor (CMOS) process give an advantage of resistive random access memory (RRAM) as a promising candidate for the next generation memory， hafnium dioxide (HfO2) has been widely studied as an oxide layer material, but the use of copper (Cu) as both top and bottom electrodes has rarely been studied. In this study, radio frequency sputtering was used to deposit the intermediate layer HfO₂, and electron beam evaporation was used. For the upper and lower electrodes (cu), using different AR: O ratios, we found that the control of the metal filament will make the filament widely distributed, causing the current to rise to the limit current during Reset. However, if the flow ratio is controlled well, the ON/OFF ratio can reach 104, and the set voltage is controlled below 3v.

Keywords: RRAM, metal filament, HfO₂, Cu electrode

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Authors: Ke-Jing Lee, Cheng-Jung Lee, Yu-Chi Chang, Li-Wen Wang, Yeong-Her Wang

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To avoid the cross-talk issue of only resistive random access memory (RRAM) cell, one transistor and one resistor (1T1R) architecture with a TiO₂-based RRAM cell connected with solution barium zirconate nickelate (BZN) organic thin film transistor (OTFT) device is successfully demonstrated. The OTFT were fabricated on a glass substrate. Aluminum (Al) as the gate electrode was deposited via a radio-frequency (RF) magnetron sputtering system. The barium acetate, zirconium n-propoxide, and nickel II acetylacetone were synthesized by using the sol-gel method. After the BZN solution was completely prepared using the sol-gel process, it was spin-coated onto the Al/glass substrate as the gate dielectric. The BZN layer was baked at 100 °C for 10 minutes under ambient air conditions. The pentacene thin film was thermally evaporated on the BZN layer at a deposition rate of 0.08 to 0.15 nm/s. Finally, gold (Au) electrode was deposited using an RF magnetron sputtering system and defined through shadow masks as both the source and drain. The channel length and width of the transistors were 150 and 1500 μm, respectively. As for the manufacture of 1T1R configuration, the RRAM device was fabricated directly on drain electrodes of TFT device. A simple metal/insulator/metal structure, which consisting of Al/TiO₂/Au structures, was fabricated. First, Au was deposited to be a bottom electrode of RRAM device by RF magnetron sputtering system. Then, the TiO₂ layer was deposited on Au electrode by sputtering. Finally, Al was deposited as the top electrode. The electrical performance of the BZN OTFT was studied, showing superior transfer characteristics with the low threshold voltage of −1.1 V, good saturation mobility of 5 cm²/V s, and low subthreshold swing of 400 mV/decade. The integration of the BZN OTFT and TiO₂ RRAM devices was finally completed to form 1T1R configuration with low power consumption of 1.3 μW, the low operation current of 0.5 μA, and reliable data retention. Based on the I-V characteristics, the different polarities of bipolar switching are found to be determined by the compliance current with the different distribution of the internal oxygen vacancies used in the RRAM and 1T1R devices. Also, this phenomenon can be well explained by the proposed mechanism model. It is promising to make the 1T1R possible for practical applications of low-power active matrix flat-panel displays.

Keywords: one transistor and one resistor (1T1R), organic thin-film transistor (OTFT), resistive random access memory (RRAM), sol-gel

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Authors: Hsin-Ping Huang, Shyankay Jou

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Resistive switching of aluminum nitride (AlNx) thin film was demonstrated in a TaN/AlNx/TiN memory cell that was prepared by sputter deposition techniques. The memory cell showed bipolar switching of resistance between +3.5 V and –3.5 V. The resistance ratio of high resistance state (HRS) to low resistance state (HRS), RHRS/RLRS, was about 2 over 100 cycles of endurance test. Both the LRS and HRS of the memory cell exhibited ohmic conduction at low voltages and Poole-Frenkel emission at high voltages. The electrical conduction in the TaN/AlNx/TiN memory cell was possibly attributed to the interactions between charges and defects in the AlNx film.

Keywords: aluminum nitride, nonvolatile memory, resistive switching, thin films

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Authors: Zhemi Xu, Dewei Chu, Sean Li

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Well self-assembled pure and Mn-doped SnO2 nanocubes were synthesized by interface thermodynamic method, which is ideal for highly homogeneous large scale thin film deposition on flexible substrates for various electric devices. Mn-doped SnO2 shows very good resistive switching with high On/Off ratio (over 103), endurance and retention characteristics. More important, the resistive state can be tuned by multi-layer fabrication by alternate pure SnO2 and Mn-doped SnO2 nanocube layer, which improved the memory capacity of resistive switching effectively. Thus, such a method provides transparent, multi-level resistive switching for next generation non-volatile memory applications.

Keywords: metal oxides, self-assembly nanoparticles, multi-level resistive switching, multi-layer thin film

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Authors: Nawang Chhunid, Gagnesh Kumar

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On-chip memories consume a significant portion of the overall die space and power in modern microprocessors. On-chip caches depend on Static Random-Access Memory (SRAM) cells and scaling of technology occurring as per Moore’s law. Unfortunately, the scaling is affecting stability, performance, and leakage power which will become major problems for future SRAMs in aggressive nanoscale technologies due to increasing device mismatch and variations. 3T1D Dynamic Random-Access Memory (DRAM) cell is a non-destructive read DRAM cell with three transistors and a gated diode. In 3T1D DRAM cell gated diode (D1) acts as a storage device and also as an amplifier, which leads to fast read access. Due to its high tolerance to process variation, high density, and low cost of memory as compared to 6T SRAM cell, it is universally used by the advanced microprocessor for on chip data and program memory. In the present paper, it has been shown that 3T1D DRAM cell can perform better in terms of fast read access as compared to 6T, 4T, 3T SRAM cells, respectively.

Keywords: DRAM Cell, Read Access Time, Retention Time, Average Power dissipation

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Authors: Arpan Bera, Rini Ganguly, Raja Chakraborty, Amlan J. Pal

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To deal with the increasing demands for the high-density non-volatile memory devices, we need nano-sites with efficient and stable charge storage capabilities. We prepared nanocrystals (NCs) of inorganic perovskite, CsPbCl₃ coated with Cs₄PbCl₆, by colloidal synthesis. Due to the type-I band alignment at the junction, this core-shell composite is expected to behave as a charge trapping site. Using Scanning Tunneling Spectroscopy (STS), we investigated voltage-controlled resistive switching in this heterostructure by tracking the change in its current-voltage (I-V) characteristics. By applying voltage pulse of appropriate magnitude on the NCs through this non-invasive method, different resistive states of this system were systematically accessed. For suitable pulse-magnitude, the response jumped to a branch with enhanced current indicating a high-resistance state (HRS) to low-resistance state (LRS) switching in the core-shell NCs. We could reverse this process by using a pulse of opposite polarity. These two distinct resistive states can be considered as two logic states, 0 and 1, which are accessible by varying voltage magnitude and polarity. STS being a local probe in space enabled us to capture this switching at individual NC site. Hence, we claim a bright prospect of these core-shell NCs made of inorganic halide perovskites in future high density memory application.

Keywords: Core-shell perovskite, CsPbCl₃-Cs₄PbCl₆, resistive switching, Scanning Tunneling Spectroscopy

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Authors: Vladimir Smirnov, Roman Tominov, Vadim Avilov, Oleg Ageev

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The creation of a new generation micro- and nanoelectronics elements opens up unlimited possibilities for electronic devices parameters improving, as well as developing neuromorphic computing systems. Interest in the latter is growing up every year, which is explained by the need to solve problems related to the unstructured classification of data, the construction of self-adaptive systems, and pattern recognition. However, for its technical implementation, it is necessary to fulfill a number of conditions for the basic parameters of electronic memory, such as the presence of non-volatility, the presence of multi-bitness, high integration density, and low power consumption. Several types of memory are presented in the electronics industry (MRAM, FeRAM, PRAM, ReRAM), among which non-volatile resistive memory (ReRAM) is especially distinguished due to the presence of multi-bit property, which is necessary for neuromorphic systems manufacturing. ReRAM is based on the effect of resistive switching – a change in the resistance of the oxide film between low-resistance state (LRS) and high-resistance state (HRS) under an applied electric field. One of the methods for the technical implementation of neuromorphic systems is cross-bar structures, which are ReRAM cells, interconnected by cross data buses. Such a structure imitates the architecture of the biological brain, which contains a low power computing elements - neurons, connected by special channels - synapses. The choice of the ReRAM oxide film material is an important task that determines the characteristics of the future neuromorphic system. An analysis of literature showed that many metal oxides (TiO2, ZnO, NiO, ZrO2, HfO2) have a resistive switching effect. It is worth noting that the manufacture of nanocomposites based on these materials allows highlighting the advantages and hiding the disadvantages of each material. Therefore, as a basis for the neuromorphic structures manufacturing, it was decided to use ZnₓTiᵧHfzOᵢ nanocomposite. It is also worth noting that the ZnₓTiᵧHfzOᵢ nanocomposite does not need an electroforming, which degrades the parameters of the formed ReRAM elements. Currently, this material is not well studied, therefore, the study of the effect of resistive switching in forming-free ZnₓTiᵧHfzOᵢ nanocomposite is an important task and the goal of this work. Forming-free nanocomposite ZnₓTiᵧHfzOᵢ thin film was grown by pulsed laser deposition (Pioneer 180, Neocera Co., USA) on the SiO2/TiN (40 nm) substrate. Electrical measurements were carried out using a semiconductor characterization system (Keithley 4200-SCS, USA) with W probes. During measurements, TiN film was grounded. The analysis of the obtained current-voltage characteristics showed a resistive switching from HRS to LRS resistance states at +1.87±0.12 V, and from LRS to HRS at -2.71±0.28 V. Endurance test shown that HRS was 283.21±32.12 kΩ, LRS was 1.32±0.21 kΩ during 100 measurements. It was shown that HRS/LRS ratio was about 214.55 at reading voltage of 0.6 V. The results can be useful for forming-free nanocomposite ZnₓTiᵧHfzOᵢ films in neuromorphic systems manufacturing. This work was supported by RFBR, according to the research project № 19-29-03041 mk. The results were obtained using the equipment of the Research and Education Center «Nanotechnologies» of Southern Federal University.

Keywords: nanotechnology, nanocomposites, neuromorphic systems, RRAM, pulsed laser deposition, resistive switching effect

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Authors: Van Son Nguyen, Van Huy Mai, Alec Moradpour, Pascale Auban Senzier, Claude Pasquier, Kang Wang, Pierre-Antoine Albouy, Marcelo J. Rozenberg, John Giapintzakis, Christian N. Mihailescu, Charis M. Orfanidou, Thomas Maroutian, Philippe Lecoeur, Guillaume Agnus, Pascal Aubert, Sylvain Franger, Raphaël Salot, Nathalie Brun, Katia March, David Alamarguy, Pascal ChréTien, Olivier Schneegans

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In the field of Nanoelectronics, a major research activity is being developed towards non-volatile memories. To face the limitations of existing Flash memory cells (endurance, downscaling, rapidity…), new approaches are emerging, among them resistive switching memories (Re-RAM). In this work, we analysed the behaviour of LixCoO2 oxide thin films in electrode/film/electrode devices. Preliminary results have been obtained concerning the influence of bias pulses characteristics (duration, value) on some performance parameters, such as endurance and resistance ratio (ROFF/RON). Besides, Conducting Probe Atomic Force Microscopy (CP-AFM) characterizations of the devices have been carried out to better understand some causes of performance failure, and thus help optimizing the switching performance of such devices.

Keywords: non volatile resistive memories, resistive switching, thin films, endurance

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Authors: Eunae Lee, Oh-Kuen Kwon, Ki-Sub Kim, Jeong Won Kang

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We investigated the dynamic properties of graphene-nanoribbon (GNR) memory encapsulating graphene-nanoflake (GNF) shuttle in the potential to be applicable as a non-volatile random access memory via molecular dynamics simulations. This work explicitly demonstrates that the GNR encapsulating the GNF shuttle can be applied to nonvolatile memory. The potential well was originated by the increase of the attractive vdW energy between the GNRs when the GNF approached the edges of the GNRs. So the bistable positions were located near the edges of the GNRs. Such a nanoelectromechanical non-volatile memory based on graphene is also applicable to the development of switches, sensors, and quantum computing.

Keywords: graphene nanoribbon, graphene nanoflake, shuttle memory, molecular dynamics

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Authors: M. Fadlallah, G. Ghibaudo, C. G. Theodorou

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The dynamic variation in memory devices such as the Static Random Access Memory can give errors in read or write operations. In this paper, the effect of low-frequency and random telegraph noise on the dynamic variation of one SRAM cell is detailed. The effect on circuit noise, speed, and length of time of processing is examined, using the Supply Read Retention Voltage and the Read Static Noise Margin. New test run methods are also developed. The obtained results simulation shows the importance of noise caused by dynamic variation, and the impact of Random Telegraph noise on SRAM variability is examined by evaluating the statistical distributions of Random Telegraph noise amplitude in the pull-up, pull-down. The threshold voltage mismatch between neighboring cell transistors due to intrinsic fluctuations typically contributes to larger reductions in static noise margin. Also the contribution of each of the SRAM transistor to total dynamic variation has been identified.

Keywords: low-frequency noise, random telegraph noise, dynamic variation, SRRV

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Authors: Dengpan Wu, Dan Liu

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In view of the present cloud security problem has increasingly become one of the major obstacles hindering the development of the cloud computing, put forward a kind of memory based on Xen cloud environment security isolation technology implementation. And based on Xen virtual machine monitor system, analysis of the model of memory virtualization is implemented, using Xen memory virtualization system mechanism of super calls and grant table, based on the virtual machine manager internal implementation of access control module (ACM) to design the security isolation system memory. Experiments show that, the system can effectively isolate different customer domain OS between illegal access to memory data.

Keywords: cloud security, memory isolation, xen, virtual machine

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Authors: Khushalini N. Ulman, Samane Maroufi, Veena H. Sahajwalla

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Globally, electronic waste (e-waste) continues to grow at an alarming rate. Several technologies have been developed to recover valuable materials from e-waste, however, their efficiency can be increased with a better knowledge of the e-waste components. Random access memory cards (RAMs) are considered as high value scrap for the e-waste recyclers. Despite their high precious metal content, RAMs are still recycled in a conventional manner resulting in huge loss of resources. Our research work highlights the precious metal rich components of a RAM. Inductively coupled plasma (ICP) analysis of RAMs of six different generations have been carried out and the trends in their metal content have been investigated. Over the past decade, the copper content of RAMs has halved and their tin content has increased by 70 %. The stricter environmental laws have facilitated ~96 % drop in the lead content of RAMs. To comprehend the fundamentals of thermal transformation of RAMs, our research provides their detailed kinetic study. This can assist the e-waste recyclers in optimising their metal recovery processes. Thus, understanding the chemical and thermal behaviour of RAMs can open new avenues for efficient e-waste recycling.

Keywords: electronic waste, kinetic study, recycling, thermal transformation

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Authors: Nagi Mekhiel

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Many applications use vector operations by applying single instruction to multiple data that map to different locations in conventional memory. Transferring data from memory is limited by access latency and bandwidth affecting the performance gain of vector processing. We present a memory system that makes all of its content available to processors in time so that processors need not to access the memory, we force each location to be available to all processors at a specific time. The data move in different orbits to become available to other processors in higher orbits at different time. We use this memory to apply parallel vector operations to data streams at first orbit level. Data processed in the first level move to upper orbit one data element at a time, allowing a processor in that orbit to apply another vector operation to deal with serial code limitations inherited in all parallel applications and interleaved it with lower level vector operations.

Keywords: Memory Organization, Parallel Processors, Serial Code, Vector Processing

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Authors: Derssie Mebratu

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As a large variety of micro services, web services, social graphic applications, and media applications are continuously developed, it is substantially vital to design and build a reliable, efficient, and faster memory tiering system. Despite limited design, implementation, and deployment in the last few years, several techniques are currently developed to improve a memory tiering system in a cloud. Some of these techniques are to develop an optimal scanning frequency; improve and track pages movement; identify pages that recently accessed; store pages across each tiering, and then identify pages as a hot, warm, and cold so that hot pages can store in the first tiering Dynamic Random Access Memory (DRAM) and warm pages store in the second tiering Compute Express Link(CXL) and cold pages store in the third tiering Non-Volatile Memory (NVM). Apart from the current proposal and implementation, we also develop a new technique based on a machine learning algorithm in that the throughput produced 25% improved performance compared to the performance produced by the baseline as well as the latency produced 95% improved performance compared to the performance produced by the baseline.

Keywords: machine learning, bayesian optimization, memory tiering, CXL, DRAM

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Authors: Alhusein Almahjoub, Dongyu Qiu

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This paper deals with the random access procedure in next-generation networks and presents the solution to reduce total service time (TST) which is one of the most important performance metrics in current and future internet of things (IoT) based networks. The proposed solution focuses on the calculation of optimal transmission probability which maximizes the success probability and reduces TST. It uses the information of several idle preambles in every time slot, and based on it, it estimates the number of backlogged IoT devices using Naïve Bayes estimation which is a type of supervised learning in the machine learning domain. The estimation of backlogged devices is necessary since optimal transmission probability depends on it and the eNodeB does not have information about it. The simulations are carried out in MATLAB which verify that the proposed solution gives excellent performance.

Keywords: random access, LTE/LTE-A, 5G, machine learning, Naïve Bayes estimation

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Authors: H. C. Woo, F. Bouanis, C. S. Cojocaur

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Graphene, which consists of a single layer of carbon atoms in a honeycomb lattice, is an interesting potential optoelectronic material because of graphene’s high carrier mobility, zero bandgap, and electron–hole symmetry. Graphene can absorb light and convert it into a photocurrent over a wide range of the electromagnetic spectrum, from the ultraviolet to visible and infrared regimes. Over the last several years, a variety of graphene-based photodetectors have been reported, such as graphene transistors, graphene-semiconductor heterojunction photodetectors, graphene based bolometers. It is also reported that there are several physical mechanisms enabling photodetection: photovoltaic effect, photo-thermoelectric effect, bolometric effect, photogating effect, and so on. In this work, we report a simple approach for the realization of graphene based resistive photo-detection devices and the measurements of their photoelectrical response. The graphene were synthesized directly on the glass substrate by novel growth method patented in our lab. Then, the metal electrodes were deposited by thermal evaporation on it, with an electrode length and width of 1.5 mm and 300 μm respectively, using Co to fabricate simple graphene based resistive photosensor. The measurements show that the graphene resistive devices exhibit a photoresponse to the illumination of visible light. The observed re-sistance response was reproducible and similar after many cycles of on and off operations. This photoelectrical response may be attributed not only to the direct photocurrent process but also to the desorption of oxygen. Our work shows that the simple graphene resistive devices have potential in photodetection applications.

Keywords: graphene, resistive sensor, optoelectronics, photoresponse

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Authors: Samuel Kaspi, Sitalakshmi Venkatraman

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In-memory database systems are becoming popular due to the availability and affordability of sufficiently large RAM and processors in modern high-end servers with the capacity to manage large in-memory database transactions. While fast and reliable in-memory systems are still being developed to overcome cache misses, CPU/IO bottlenecks and distributed transaction costs, disk-based data stores still serve as the primary persistence. In addition, with the recent growth in multi-tenancy cloud applications and associated security concerns, many organisations consider the trade-offs and continue to require fast and reliable transaction processing of disk-based database systems as an available choice. For these organizations, the only way of increasing throughput is by improving the performance of disk-based concurrency control. This warrants a hybrid database system with the ability to selectively apply an enhanced disk-based data management within the context of in-memory systems that would help improve overall throughput. The general view is that in-memory systems substantially outperform disk-based systems. We question this assumption and examine how a modified variation of access invariance that we call enhanced memory access, (EMA) can be used to allow very high levels of concurrency in the pre-fetching of data in disk-based systems. We demonstrate how this prefetching in disk-based systems can yield close to in-memory performance, which paves the way for improved hybrid database systems. This paper proposes a novel EMA technique and presents a comparative study between disk-based EMA systems and in-memory systems running on hardware configurations of equivalent power in terms of the number of processors and their speeds. The results of the experiments conducted clearly substantiate that when used in conjunction with all concurrency control mechanisms, EMA can increase the throughput of disk-based systems to levels quite close to those achieved by in-memory system. The promising results of this work show that enhanced disk-based systems facilitate in improving hybrid data management within the broader context of in-memory systems.

Keywords: in-memory database, disk-based system, hybrid database, concurrency control

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Authors: Mahsa Mousavi, Hamid Reza Pourshaghaghi, Mohammad Tahghighi, Henk Corporaal

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Recently, Statistic Random-Access Memory-based (SRAM-based) Field-Programmable Gate Arrays (FPGAs) are widely used in aeronautics and space systems where high dependability is demanded and considered as a mandatory requirement. Since design’s circuit is stored in configuration memory in SRAM-based FPGAs; they are very sensitive to Single Event Upsets (SEUs). In addition, the adverse effects of SEUs on the electronics used in space are much higher than in the Earth. Thus, developing fault tolerant techniques play crucial roles for the use of SRAM-based FPGAs in space. However, fault tolerance techniques introduce additional penalties in system parameters, e.g., area, power, performance and design time. In this paper, an accurate estimation of configuration memory vulnerability to SEUs is proposed for approximate-tolerant applications. This vulnerability estimation is highly required for compromising between the overhead introduced by fault tolerance techniques and system robustness. In this paper, we study applications in which the exact final output value is not necessarily always a concern meaning that some of the SEU-induced changes in output values are negligible. We therefore define and propose Approximate-based Configuration Memory Vulnerability Factor (ACMVF) estimation to avoid overestimating configuration memory vulnerability to SEUs. In this paper, we assess the vulnerability of configuration memory by injecting SEUs in configuration memory bits and comparing the output values of a given circuit in presence of SEUs with expected correct output. In spite of conventional vulnerability factor calculation methods, which accounts any deviations from the expected value as failures, in our proposed method a threshold margin is considered depending on user-case applications. Given the proposed threshold margin in our model, a failure occurs only when the difference between the erroneous output value and the expected output value is more than this margin. The ACMVF is subsequently calculated by acquiring the ratio of failures with respect to the total number of SEU injections. In our paper, a test-bench for emulating SEUs and calculating ACMVF is implemented on Zynq-7000 FPGA platform. This system makes use of the Single Event Mitigation (SEM) IP core to inject SEUs into configuration memory bits of the target design implemented in Zynq-7000 FPGA. Experimental results for 32-bit adder show that, when 1% to 10% deviation from correct output is considered, the counted failures number is reduced 41% to 59% compared with the failures number counted by conventional vulnerability factor calculation. It means that estimation accuracy of the configuration memory vulnerability to SEUs is improved up to 58% in the case that 10% deviation is acceptable in output results. Note that less than 10% deviation in addition result is reasonably tolerable for many applications in approximate computing domain such as Convolutional Neural Network (CNN).

Keywords: fault tolerance, FPGA, single event upset, approximate computing

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Authors: Chun-Lin Chiang, Che-Yen Lee, Yu-Shan Yeh, Jiunn-Haur Shaw

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Wafer fabrication is a critical part of the semiconductor process, when the finest linewidth with the improvement of technology continues to decline and the structure development from 2D towards to 3D. The nanoparticles contained in the slurry or in the ultrapure water which used for cleaning have a large influence on the manufacturing process. Therefore, semiconductor industry is hoping to find a viable method for on-line detection the nanoparticles size and concentration. The resistive pulse sensing technology is one of the methods that may cover this question. As we know that nanoparticles properties of material differ significantly from their properties at larger length scales. So, we want to clear that the metal and non-metal nanoparticles translocation dynamic when we use the resistive pulse sensing technology. In this study we try to use the finite element method that contains three governing equations to do multiphysics coupling simulations. The Navier-Stokes equation describes the laminar motion, the Nernst-Planck equation describes the ion transport, and the Poisson equation describes the potential distribution in the flow channel. To explore that the metal nanoparticles and the non-metal nanoparticles in different concentration electrolytes, through the nanochannel caused by ion current changes. Then the reliability of the simulation results was verified by resistive pulse sensing test. The existing results show that the lower ion concentration, the greater effect of nanoparticles on the ion concentration in the nanochannel. The conductive spikes are correlated with nanoparticles surface charge. Then we can be concluded that in the resistive pulse sensing technique, the ion concentration in the nanochannel and nanoparticle properties are important for the translocation dynamic, and they have the interactions.

Keywords: multiphysics simulations, resistive pulse sensing, nanoparticles, nanochannel

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Authors: Marek Gancarz, Agnieszka Nawrocka, Robert Rusinek, Marcin Tadla

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Volatile organic compounds (VOCs) are the fungi metabolites in the gaseous form produced during improper storage of agricultural commodities (e.g. grain, food). The spoilt commodities produce a wide range of VOCs including alcohols, esters, aldehydes, ketones, alkanes, alkenes, furans, phenols etc. The characteristic VOCs and odours can be determined by using electronic nose (e-Nose) which contains a matrix of different kinds of sensors e.g. resistive sensors. The aim of the present studies was to determine relationship between response of the resistive sensors on the chosen volatiles and their concentration. According to the literature, it was chosen volatiles characteristic for the cereals: ethanol, 3-methyl-1-butanol and hexanal. Analysis of the sensor signals shows that a signal shape is different for the different substances. Moreover, each VOC signal gives information about a maximum of the normalized sensor response (R/Rmax), an impregnation time (tIM) and a cleaning time at half maximum of R/Rmax (tCL). These three parameters can be regarded as a ‘VOC fingerprint’. Seven resistive sensors (TGS2600-B00, TGS2602-B00, TGS2610-C00, TGS2611-C00, TGS2611-E00, TGS2612-D00, TGS2620-C00) produced by Figaro USA Inc., and one (AS-MLV-P2) produced by AMS AG, Austria were used. Two out of seven sensors (TGS2611-E00, TGS2612-D00) did not react to the chosen VOCs. The most responsive sensor was AS-MLV-P2. The research was supported by the National Centre for Research and Development (NCBR), Grant No. PBS2/A8/22/2013.

Keywords: agricultural commodities, organic compounds, resistive sensors, volatile

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Authors: Deon de Jager, Yahya Zweiri, Dimitrios Makris

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The three most important components in the cognitive architecture for cognitive robotics is memory representation, memory recall, and action-selection performed by the executive. In this paper, action selection, performed by the executive, is defined as a memory quantification and optimization process. The methodology describes the real-time construction of episodic memory through semantic memory optimization. The optimization is performed by set-based particle swarm optimization, using an adaptive entropy memory quantification approach for fitness evaluation. The performance of the approach is experimentally evaluated by simulation, where a UAV is tasked with the collection and delivery of a medical package. The experiments show that the UAV dynamically uses the episodic memory to autonomously control its velocity, while successfully completing its mission.

Keywords: cognitive robotics, semantic memory, episodic memory, maximum entropy principle, particle swarm optimization

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Authors: Dmitriy Kuptsov

Abstract:

Tree data structures, such as binary or in general k-ary trees, are essential in computer science. The applications of these data structures can range from data search and retrieval to sorting and ranking algorithms. Naive implementations of these data structures can consume prohibitively large volumes of random access memory limiting their applicability in certain solutions. Thus, in these cases, more advanced representation of these data structures is essential. In this paper we present the design of the compact version of ternary tree data structure and demonstrate the results for the experimental evaluation using static dictionary problem. We compare these results with the results for binary and regular ternary trees. The conducted evaluation study shows that our design, in the best case, consumes up to 12 times less memory (for the dictionary used in our experimental evaluation) than a regular ternary tree and in certain configuration shows performance comparable to regular ternary trees. We have evaluated the performance of the algorithms using both 32 and 64 bit operating systems.

Keywords: algorithms, data structures, succinct ternary tree, per- formance evaluation

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Authors: Merve Akca

Abstract:

Retrieval-induced forgetting (RIF) refers to the phenomenon that selective retrieval of some information impairs memory for related, but not previously retrieved information. Despite age differences in retrieval-induced forgetting regarding retrospective memory being documented, this research aimed to highlight age differences in RIF of the prospective memory tasks for the first time. By using retrieval-practice paradigm, this study comparatively examined RIF effects in retrospective memory and event-based prospective memory in young and old adults. In this experimental study, a mixed factorial design with age group (Young, Old) as a between-subject variable, and memory type (Prospective, Retrospective) and item type (Practiced, Non-practiced) as within-subject variables was employed. Retrieval-induced forgetting was observed in the retrospective but not in the prospective memory task. Therefore, the results indicated that selective retrieval of past events led to suppression of other related past events in both age groups but not the suppression of memory for future intentions.

Keywords: prospective memory, retrieval-induced forgetting, retrieval inhibition, retrospective memory

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Authors: Sorcha Bennett, Joe Sullivan

Abstract:

Triple-Level Cell (TLC) NAND Flash memory at, and below, 20nm (nanometer) is still largely unexplored by researchers, and with the ever more commonplace existence of Flash in consumer and enterprise applications there is a need for such gaps in knowledge to be filled. At the time of writing, there was little published data or literature on TLC, and more specifically reliability testing, with a further emphasis on both endurance and retention. This paper will give an introduction to NAND Flash memory, followed by an overview of the relevant current research on the reliability of Flash memory, along with the planned future work which will provide results to help characterise the reliability of TLC memory.

Keywords: endurance, patterns, raw flash, reliability, retention, TLC NAND flash memory, trade-off

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Authors: Abolfazl Alishahi Ghalehjoughi

Abstract:

Economic independence and security of Islamic world is the top priority. Economic dependence of Muslim countries on economies of non-Muslim imperialist countries results in political and cultural dependencies, and such dependencies will jeopardize the noble Islamic culture; because the will of a dependent country to implements the noble teachings of Islam would be faced with challenges. Solidarity of Muslim countries to achieve a uniformed and resistive economy-based Islamic economic system can improve ability of Islamic world to resist and counteract economic shocks produced by imperialists. Islam is the most complete religion in every aspect, from ideological and epistemological, to legislative and ethical, and economic aspect is no exception. Islam provides solutions to develop a flourishing economy for the whole Islamic nation. Knowledge of such solutions and identification of mechanisms to operationalise them in Islamic communities can highly contributed to establishment of the superior Islamic economy. Encourage of hard working, achievement and knowledge production, correction of consumption patterns, optimized management of import and export, avoiding Islamically prohibited income, economic discipline and equity, and promotion of interest free loan and the like are among the most important solutions to realize such resistive economy.

Keywords: resistive economy, cultural independence, Islam, solidarity

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Authors: Chhavi Saxena

Abstract:

FinFETs can be a replacement for bulk-CMOS transistors in many different designs. Its low leakage/standby power property makes FinFETs a desirable option for memory sub-systems. Memory modules are widely used in most digital and computer systems. Leakage power is very important in memory cells since most memory applications access only one or very few memory rows at a given time. As technology scales down, the importance of leakage current and power analysis for memory design is increasing. In this paper, we discover an option for low power interconnect synthesis at the 32nm node and beyond, using Fin-type Field-Effect Transistors (FinFETs) which are a promising substitute for bulk CMOS at the considered gate lengths. We consider a mechanism for improving FinFETs efficiency, called variable supply voltage schemes. In this paper, we’ve illustrated the design and implementation of FinFET based 4x4 SRAM cell array by means of one bit 7T SRAM. FinFET based 7T SRAM has been designed and analysis have been carried out for leakage current, dynamic power and delay. For the validation of our design approach, the output of FinFET SRAM array have been compared with standard CMOS SRAM and significant improvements are obtained in proposed model.

Keywords: FinFET, 7T SRAM cell, leakage current, delay

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Authors: Hasmayadi Abdul Majid, Yuzman Yusoff, Noor Shelida Salleh

Abstract:

This paper presents the development of a single-ended 38.5 kS/s 10-bit programmable reference SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and a SAR digital logic to create 10 effective bits ADC. A programmable reference circuitry allows the ADC to operate with different input range from 0.6 V to 2.1 V. A single ended 38.5 kS/s 10-bit programmable reference SAR ADC was proposed and implemented in a 0.35 µm CMOS technology and consumed less than 7.5 mW power with a 3 V supply.

Keywords: successive approximation register analog-to-digital converter, SAR ADC, resistive DAC, programmable reference

Procedia PDF Downloads 484