Search results for: one transistor and one resistor (1T1R)

Authors: Ke-Jing Lee, Cheng-Jung Lee, Yu-Chi Chang, Li-Wen Wang, Yeong-Her Wang

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To avoid the cross-talk issue of only resistive random access memory (RRAM) cell, one transistor and one resistor (1T1R) architecture with a TiO₂-based RRAM cell connected with solution barium zirconate nickelate (BZN) organic thin film transistor (OTFT) device is successfully demonstrated. The OTFT were fabricated on a glass substrate. Aluminum (Al) as the gate electrode was deposited via a radio-frequency (RF) magnetron sputtering system. The barium acetate, zirconium n-propoxide, and nickel II acetylacetone were synthesized by using the sol-gel method. After the BZN solution was completely prepared using the sol-gel process, it was spin-coated onto the Al/glass substrate as the gate dielectric. The BZN layer was baked at 100 °C for 10 minutes under ambient air conditions. The pentacene thin film was thermally evaporated on the BZN layer at a deposition rate of 0.08 to 0.15 nm/s. Finally, gold (Au) electrode was deposited using an RF magnetron sputtering system and defined through shadow masks as both the source and drain. The channel length and width of the transistors were 150 and 1500 μm, respectively. As for the manufacture of 1T1R configuration, the RRAM device was fabricated directly on drain electrodes of TFT device. A simple metal/insulator/metal structure, which consisting of Al/TiO₂/Au structures, was fabricated. First, Au was deposited to be a bottom electrode of RRAM device by RF magnetron sputtering system. Then, the TiO₂ layer was deposited on Au electrode by sputtering. Finally, Al was deposited as the top electrode. The electrical performance of the BZN OTFT was studied, showing superior transfer characteristics with the low threshold voltage of −1.1 V, good saturation mobility of 5 cm²/V s, and low subthreshold swing of 400 mV/decade. The integration of the BZN OTFT and TiO₂ RRAM devices was finally completed to form 1T1R configuration with low power consumption of 1.3 μW, the low operation current of 0.5 μA, and reliable data retention. Based on the I-V characteristics, the different polarities of bipolar switching are found to be determined by the compliance current with the different distribution of the internal oxygen vacancies used in the RRAM and 1T1R devices. Also, this phenomenon can be well explained by the proposed mechanism model. It is promising to make the 1T1R possible for practical applications of low-power active matrix flat-panel displays.

Keywords: one transistor and one resistor (1T1R), organic thin-film transistor (OTFT), resistive random access memory (RRAM), sol-gel

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Authors: Janpen Srijan, Nahathai Tanmang, Thanit Purathanang, Anun Dowchern, Saksit Summart, Seangduan Kampimpa

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This paper presents the resistance reader program based on image processing by using MATLAB. The proposed program is divided into six parts; the first part is the web camera; the second part is a watt selection before shooting the resistor; the third part is a part of finding the position of the color on the mid-point of resistor; the fourth part is a part of identifying color code of the resistor; the fifth part is a part of taking the number of values for each color for resistance calculation and the last part is a part of displaying result of resistance value. The experimental result of the resistance reader program based on image processing was able to display the resistance value of resistor. The accuracy of proposed program is 85 percent for 1 watt resistor. It has 15 percent of reading error because a problem with the color code of some resistor was too bright.

Keywords: resistance reader program, image processing, resistor, MATLAB

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Authors: Porag Jyoti Ligira, Gargi Khanna

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The paper presents a simulation study of the electrical characteristic of Bulk Planar Junctionless Transistor (BPJLT) using spacer. The BPJLT is a transistor without any PN junctions in the vertical direction. It is a gate controlled variable resistor. The characteristics of BPJLT are analyzed by varying the oxide material under the gate. It can be shown from the simulation that an ideal subthreshold slope of ~60 mV/decade can be achieved by using highk dielectric. The effects of variation of spacer length and material on the electrical characteristic of BPJLT are also investigated in the paper. The ION / IOFF ratio improvement is of the order of 107 and the OFF current reduction of 10-4 is obtained by using gate dielectric of HfO2 instead of SiO2.

Keywords: spacer, BPJLT, high-k, double gate

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Authors: Kittipong Tripetch, Nobuhiko Nakano

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Two types of floating active resistors based on a complementary regulated cascode topology with cross-coupled regulated transistors are presented in this paper. The first topology is a high swing complementary regulated cascode active resistor. The second topology is a complementary common gate with a regulated cross coupled transistor. The small-signal input resistances of the floating resistors are derived. Three graphs of the input current versus the input voltage for different aspect ratios are designed and plotted using the Cadence Spectre 0.18-µm Rohm Semiconductor process. The total harmonic distortion graphs are plotted for three different aspect ratios with different input-voltage amplitudes and different input frequencies. From the simulation results, it is observed that a resistance of approximately 8.52 MΩ can be obtained from supply voltage at  ±0.9 V.

Keywords: floating active resistor, complementary common gate, complementary regulated cascode, current mirror

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Authors: Abdelmonaem Ayachi, Belgacem Hamdi

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This paper presents a fault-tolerant implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to standard CMOS technology.

Keywords: digital electronics, integrated circuits, full adder, 32nm CMOS tehnology, double pass transistor technology, fault toleance, self-checking

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Authors: Mohammad Hosseini

Abstract:

Ultrafast transistor laser investigated here has the graded index separate confinement heterostructure (GRIN-SCH) in its base region. Resonance-free optical frequency response with -3dB bandwidth of more than 26 GHz has been achieved for a single quantum well transistor laser by using graded index layers of AlξGa1-ξAs (ξ: 0.1→0) on the left side of the quantum well and AlξGa1-ξAs (ξ: 0.05→0) in the right side of quantum well. All required parameters, including quantum well and base transit time, optical confinement factor and spontaneous recombination lifetime, have been calculated using a self-consistent charge control model.

Keywords: transistor laser, ultrafast, GRIN-SCH, -3db optical bandwidth, AlξGa1-ξAs

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Authors: Sangeeta Singh, Pankaj Kumar, P. N. Kondekar

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In this paper, the transient device performance analysis of n-type Gate Inside Junctionless Transistor (GIJLT)has been evaluated. 3-D Bohm Quantum Potential (BQP)transport device simulation has been used to evaluate the delay and power dissipation performance. GI-JLT has a number of desirable device parameters such as reduced propagation delay, dynamic power dissipation, power and delay product, intrinsic gate delay and energy delay product as compared to Gate-all-around transistors GAA-JLT. In addition to this, various other device performance parameters namely, on/off current ratio, short channel effects (SCE), transconductance Generation Factor(TGF) and unity gain cut-off frequency (fT) and subthreshold slope (SS) of the GI-JLT and Gate-all-around junctionless transistor(GAA-JLT) have been analyzed and compared. GI-JLT shows better device performance characteristics than GAA-JLT for low power and high frequency applications, because of its larger gate electrostatic control on the device operation.

Keywords: gate-inside junctionless transistor GI-JLT, gate-all-around junctionless transistor GAA-JLT, propagation delay, power delay product

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Authors: Spyridon Nikolaidis

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A modeling approach for CMOS gates is presented based on the use of the equivalent inverter. A new model for the inverter has been developed using a simplified transistor current model which incorporates the nanoscale effects for the planar technology. Parametric expressions for the output voltage are provided as well as the values of the output and supply current to be compatible with the CCS technology. The model is parametric according the input signal slew, output load, transistor widths, supply voltage, temperature and process. The transistor widths of the equivalent inverter are determined by HSPICE simulations and parametric expressions are developed for that using a fitting procedure. Results for the NAND gate shows that the proposed approach offers sufficient accuracy with an average error in propagation delay about 5%.

Keywords: CMOS gate modeling, inverter modeling, transistor current mode, timing model

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Authors: Fatima Zohra Rahou, A. Guen Bouazza, B. Bouazza

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Invention of transistor is the foundation of electronics industry. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been the key for the development of nanoelectronics technology. In the first part of this manuscript, we present a new generation of MOSFET transistors based on SOI (Silicon-On-Insulator) technology. It is a partially depleted Silicon-On-Insulator (PD SOI MOSFET) transistor simulated by using SILVACO software. This work was completed by the presentation of some results concerning the influence of parameters variation (channel length L and gate oxide thickness Tox) on our PDSOI n-MOSFET structure on its drain current and kink effect.

Keywords: SOI technology, PDSOI MOSFET, FDSOI MOSFET, kink effect

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Authors: Zina Saheb, Ezz El-Masry

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As CMOS technology scaling down, Silicon oxide thickness (SiO2) become very thin (few Nano meters). When SiO2 is less than 3nm, gate direct tunneling (DT) leakage current becomes a dormant problem that impacts the transistor performance. Floating gate MOSFET (FGMOSFET) has been used in many low-voltage and low-power applications. Most of the available simulation models of FGMOSFET for analog circuit design does not account for gate DT current and there is no accurate analysis for the gate DT. It is a crucial to use an accurate mode in order to get a realistic simulation result that account for that DT impact on FGMOSFET performance effectively.

Keywords: CMOS transistor, direct-tunneling current, floating-gate, gate-leakage current, simulation model

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Authors: Nur Syarafina Binti Othman, Tsubasa Jindo, Makato Yamada, Miho Tsuyama, Hitoshi Nakano

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A novel method to produce a fast high voltage solid states switch using Insulated Gate Bipolar Transistors (IGBTs) is presented for discharge-pumped gas lasers. The IGBTs are connected in series to achieve a high voltage rating. An avalanche transistor is used as the gate driver. The fast pulse generated by the avalanche transistor quickly charges the large input capacitance of the IGBT, resulting in a switch out of a fast high-voltage pulse. The switching characteristic of fast-high voltage solid state switch has been estimated in the multi-stage series-connected IGBT with the applied voltage of several tens of kV. Electrical circuit diagram and the mythology of fast-high voltage solid state switch as well as experimental results obtained are presented.

Keywords: high voltage, IGBT, solid state switch, bipolar transistor

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Authors: Biswarup Mukherjee, Aniruddha Ghoshal

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In this paper, we propose a new technique for implementing a low power high speed full adder using 8 transistors. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have high speed operation for the sub components. The explored method of implementation achieves a high speed low power design for the full adder. Simulated results indicate the superior performance of the proposed technique over conventional 28 transistor CMOS full adder. Detailed comparison of simulated results for the conventional and present method of implementation is presented.

Keywords: high speed low power full adder, 2-T MUX, 3-T XOR, 8-T FA, pass transistor logic, CMOS (complementary metal oxide semiconductor)

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Authors: Sang Hoon Lee, Tae Il Lee, Su Jeong Lee, Jae Min Myoung

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In order to manufacture short gap single Si nanowire (NW) field effect transistor (FET) by imprinting and transferring method, we introduce the method using Al2O3 sacrificial layer. The diameters of cylindrical Si NW addressed between Au electrodes by dielectrophoretic (DEP) alignment method are controlled to 106, 128, and 148 nm. After imprinting and transfer process, cylindrical Si NW is embedded in PVP adhesive and dielectric layer. By curing transferred cylindrical Si NW and Au electrodes on PVP-coated p++ Si substrate with 200nm-thick SiO2, 3μm gap Si NW FET fabrication was completed. As the diameter of embedded Si NW increases, the mobility of FET increases from 80.51 to 121.24 cm2/V•s and the threshold voltage moves from –7.17 to –2.44 V because the ratio of surface to volume gets reduced.

Keywords: Al2O3 sacrificial transfer layer, cylindrical silicon nanowires, dielectrophorestic alignment, field effect transistor

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Authors: Birinderjit Singh Kalyan, Inderpreet Kaur, Balwinder Singh Sohi

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In this paper, an equivalent model for floating gate transistor has been proposed. Using the floating gate voltage value, capacitive coupling coefficients has been found at different bias conditions. The amount of charge present on the gate has been then calculated using the transient models of hot electron programming and Fowler-Nordheim Tunnelling. The proposed model can be extended to the transient conditions as well. The SPICE equivalent model is designed and current-voltage characteristics and Transfer characteristics are comparatively analysed. The dc current-voltage characteristics, as well as dc transfer characteristics, have been plotted for an FGMOS with W/L=0.25μm/0.375μm, the inter-poly capacitance of 0.8fF for both programmed and erased states. The Comparative analysis has been made between the present model and capacitive coefficient coupling methods which were already available.

Keywords: FGMOS, floating gate transistor, capacitive coupling coefficient, SPICE model

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Authors: Sorayya Kazemi, Hamed Kharrati, Mehdi Abedinpour Fallah

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This paper presents the design and implementation of a novel electric pressure-sensitive toothbrush, capable of measuring the forces applied to the head of the brush. The developed device is used for gum recession measurement. In particular, the percentage of gum recession is measured by a Programmable Automation controller (PAC). Moreover, the brushing forces are measured by a Force Sensing Resistor (FSR) sensor. These forces are analog inputs of PAC. According to the applied forces during patient’s brushing and the patient’s percentage of gum recession, dentist sets the standard force range. The instrument alarms when the patient applies a force over the set range.

Keywords: gum recession, force sensing resistor, controller, toothbrush

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Authors: Su Jeong Lee, Tae Il Lee, Jung Han Kim, Chul-Hong Kim, Gee Sung Chae, Jae-Min Myoung

Abstract:

The contact resistance between source/drain electrodes and semiconductor layer is an important parameter affecting electron transporting performance in the thin film transistor (TFT). In this work, we introduced a transparent and the solution prossable single-walled carbon nanotube (SWCNT)/Al-doped ZnO nano particle (AZO NP) bilayer electrodes showing low contact resistance with indium-oxide (In2O3) sol gel thin film. By inserting low work function AZO NPs into the interface between the SWCNTs and the In2O3 which has a high energy barrier, we could obtain an electrical Ohmic contact between them. Finally, with the SWCNT-AZO NP bilayer electrodes, we successfully fabricated a TFT showing a field effect mobility of 5.38 cm2/V∙s at 250 °C.

Keywords: single-walled carbon nanotube (SWCNT), Al-doped ZnO (AZO) nanoparticle, contact resistance, thin-film transistor (TFT)

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Authors: Kashif Habib, Zeeshan Ayyub

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ZnO voltage dependent resistor was widely used as components of the electrical system for over-voltage protection. It has a wide application prospect in superconducting energy-removal, generator de-excitation, overvoltage protection of electrical & electronics equipment. At present, the research for the application of ZnO voltage dependent resistor stop, it uses just in the field of its nonlinear voltage current characteristic and overvoltage protection areas. There is no further study over the over-voltage breakdown characteristics, such as the combustion phenomena and the measure of the voltage/current when it breakdown, and the affect to its surrounding equipment. It is also a blind spot in its application. So, when we do the feature test of ZnO voltage dependent resistor, we need to design a reasonable test power supply, making the terminal voltage keep for sine wave, simulating the real use of PF voltage in power supply conditions. We put forward the solutions of using inverter to generate a controllable power. The paper mainly focuses on the breakdown characteristic test power supply of nonlinear ZnO voltage dependent resistor. According to the current mature switching power supply technology, we proposed power control system using the inverter as the core. The power mainly realize the sin-voltage output on the condition of three-phase PF-AC input, and 3 control modes (RMS, Peak, Average) of the current output. We choose TMS320F2812M as the control part of the hardware platform. It is used to convert the power from three-phase to a controlled single-phase sin-voltage through a rectifier, filter, and inverter. Design controller produce SPWM, to get the controlled voltage source via appropriate multi-loop control strategy, while execute data acquisition and display, system protection, start logic control, etc. The TMS320F2812M is able to complete the multi-loop control quickly and can be a good completion of the inverter output control.

Keywords: ZnO, multi-loop control, SPWM, non-linear load

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Authors: Zhao Weijie, Lin Xinjian, Liu Xiaojuan, Li Lihua

Abstract:

The Howland current pump is widely used in bio-impedance measurement. Much attention has been focused on the output impedance of the Howland circuit. Here we focus on the maximum load of the Howland source and discuss the relationship between the circuit parameters at maximum load. We conclude that the signal input terminal of the feedback resistor should be as large as possible, but that the current-limiting resistor should be smaller. The op-amp saturation voltage should also be high. The bandwidth of the circuit is proportional to the bandwidth of the op-amp. The Howland current pump was simulated using multisim12. When the AD8066AR was selected as the op-amp, the maximum load was 11.5 kΩ, and the Howland current pump had a stable output ipp to 2mAp up to 200 kHz. However, with an OPA847 op-amp and a load of 6.3 kΩ, the output current was also stable, and the frequency was as high as 3 MHz.

Keywords: bio-impedance, improved Howland current pump, load characteristics, bioengineering

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Authors: Abdelmadjid Mammeri, Fatima Zohra Mahi, Luca Varani, H. Marinchoi

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We propose an analytical model for the admittance and the noise calculations of the InGaAs transistor and diode. The development of the small-signal admittance takes into account the longitudinal and transverse electric fields through a pseudo two-dimensional approximation of the Poisson equation. The frequency-dependent of the small-signal admittance response is determined by the total currents and the potentials matrix relation between the gate and the drain terminals. The noise is evaluated by using the real part of the transistor/diode admittance under a small-signal perturbation. The analytical results show that the admittance spectrum exhibits a series of resonant peaks corresponding to the excitation of plasma waves. The appearance of the resonance is discussed and analyzed as functions of the channel length and the temperature. The model can be used, on one hand; to control the appearance of the plasma resonances, and on other hand; can give significant information about the noise frequency dependence in the InGaAs transistor and diode.

Keywords: InGaAs transistors, InGaAs diode, admittance, resonant peaks, plasma waves, analytical model

Procedia PDF Downloads 277

Authors: Jingqi Li

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A new vertical carbon nanotube field effect transistor (CNTFET) has been developed. The source, drain and gate are vertically stacked in this structure. The carbon nanotubes are put on the side wall of the vertical stack. Unique transfer characteristics which depend on both silicon type and the sign of drain voltage have been observed in silicon integrated CNTFETs. The significant advantage of this CNTFET is that the short channel of the transistor can be fabricated without using complicate lithography technique.

Keywords: carbon nanotubes, field-effect transistors, electrical property, short channel fabrication

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Authors: Min-ju Kwon, Chae-won Kim, Jeong-yun Seo, Hee-guk Chae, Yong-seo Koo

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In this paper, we presented the LDO (low-dropout) regulator which enhanced the PSRR by applying the constant current source generation technique through the BGR (Band Gap Reference) to form the noise sensing circuit. The current source through the BGR has a constant current value even if the applied voltage varies. Then, the noise sensing circuit, which is composed of the current source through the BGR, operated between the error amplifier and the pass transistor gate of the LDO regulator. As a result, the LDO regulator has a PSRR of -68.2 dB at 1k Hz, -45.85 dB at 1 MHz and -45 dB at 10 MHz. the other performance of the proposed LDO was maintained at the same level of the conventional LDO regulator.

Keywords: LDO regulator, noise sensing circuit, current reference, pass transistor

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Authors: Pejman Hosseinioun, Abolghasem Ghasempour, Elham Gholami, Hamed Sarbazi

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Considering the development in global semiconductor technology, it is anticipated that gadgets such as diodes and resonant transistor tunnels (RTD/RTT), Single electron transistors (SET) and quantum cellular automata (QCA) will substitute CMOS (Complementary Metallic Oxide Semiconductor) gadgets in many applications. Unfortunately, these new technologies cannot disembark the common Boolean logic efficiently and are only appropriate for liminal logic. Therefor there is no doubt that with the development of these new gadgets it is necessary to find new MacDraw technologies which are compatible with them. Resonant transistor tunnels (RTD/RTT) and circuit MacDraw with enhanced computing abilities are candida for accumulating Nano criterion in the future. Quantum cellular automata (QCA) are also advent Nano technological gadgets for electrical circuits. Advantages of these gadgets such as higher speed, smaller dimensions, and lower consumption loss are of great consideration. QCA are basic gadgets in manufacturing gates, fuses and memories. Regarding the complex Nano criterion physical entity, circuit designers can focus on logical and constructional design to decrease complication in MacDraw. Moreover Single electron technology (SET) is another noteworthy gadget considered in Nano technology. This article is a survey in future of Nano technology in digital MacDraw.

Keywords: nano technology, resonant transistor tunnels, quantum cellular automata, semiconductor

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Authors: P. Geetha, R. S. D. Wahida Banu

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The crowning advances in Silicon based electronic technology have dominated the computation world for the past decades. The captivating performance of Si devices lies in sustainable scaling down of the physical dimensions, by that increasing device density and improved performance. But, the fundamental limitations due to physical, technological, economical, and manufacture features restrict further miniaturization of Si based devices. The pit falls are due to scaling down of the devices such as process variation, short channel effects, high leakage currents, and reliability concerns. To fix the above-said problems, it is needed either to follow a new concept that will manage the current hitches or to support the available concept with different materials. The new concept is to design spintronics, quantum computation or two terminal molecular devices. Otherwise, presently used well known three terminal devices can be modified with different materials that suits to address the scaling down difficulties. The first approach will occupy in the far future since it needs considerable effort; the second path is a bright light towards the travel. Modelling paves way to know not only the current-voltage characteristics but also the performance of new devices. So, it is desirable to model a new device of suitable gate control and project the its abilities towards capability of handling high current, high power, high frequency, short delay, and high velocity with excellent electronic and optical properties. Carbon nanotube became a thriving material to replace silicon in nano devices. A well-planned optimized utilization of the carbon material leads to many more advantages. The unique nature of this organic material allows the recent developments in almost all fields of applications from an automobile industry to medical science, especially in electronics field-on which the automation industry depends. More research works were being done in this area. This paper reviews the carbon nanotube field effect transistor with various gate configurations, number of channel element, CNT wall configurations and different modelling techniques.

Keywords: array of channels, carbon nanotube field effect transistor, double gate transistor, gate wrap around transistor, modelling, multi-walled CNT, single-walled CNT

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Authors: M. Kessi

Abstract:

We investigated the effect of the magnetic field on carrier transport phenomena in the transistor channel region of Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). This explores the Lorentz force and basic physical properties of solids exposed to a constant external magnetic field. The magnetic field modulates the electrons and potential distribution in the case of silicon Tunnel FETs. This modulation shows up in the device's external electrical characteristics such as ON current (ION), subthreshold leakage current (IOF), the threshold voltage (VTH), the magneto-transconductance (gm) and the output magneto-conductance (gDS) of Tunnel FET. Moreover, the channel doping concentration and potential distribution are obtained using the numerical method by solving Poisson’s transport equation in 3D modules semiconductor magnetic sensors available in Silvaco TCAD tools. The numerical simulations of the magnetic nano-sensors are relatively new. In this work, we present the results of numerical simulations based on 3D magnetic sensors. The results show excellent accuracy comportment and good agreement compared with that obtained in the experimental study of MOSFETs technology.

Keywords: single-gate MOSFET, magnetic field, hall field, Lorentz force

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Authors: Samson Mil'shtein, Dhawal N. Asthana

Abstract:

The presented heterostructure n-p-n bipolar transistor is comprised of Ge/GaAs heterojunctions consisting of 0.15µm thick emitter and 0.65µm collector junctions. High diffusivity of carriers in GaAs base was major motivation of current design. We avoided grading of the base which is common in heterojunction bipolar transistors, in order to keep the electron diffusivity as high as possible. The electrons injected into the 0.25µm thick p-type GaAs base with not very high doping (1017cm-3). The designed HBT enables cut off frequency on the order of 150GHz. The Ge/GaAs heterojunctions presented in our paper have proved to work better than comparable HBTs having GaAs bases and emitter/collector junctions made, for example, of AlGaAs/GaAs or other III-V compound semiconductors. The difference in lattice constants between Ge and GaAs is less than 2%. Therefore, there is no need of transition layers between Ge emitter and GaAs base. Significant difference in energy gap of these two materials presents new scope for improving performance of the emitter. With the complete structure being modelled and simulated using TCAD SILVACO, the collector/ emitter offset voltage of the device has been limited to a reasonable value of 63 millivolts by the dint of low energy band gap value associated with Ge emitter. The efficiency of the emitter in our HBT is 86%. Use of Germanium in the emitter and collector regions presents new opportunities for integration of this vertical device structure into silicon substrate.

Keywords: Germanium, Gallium Arsenide, heterojunction bipolar transistor, high cut-off frequency

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Authors: Peihao Huang, Chun Zhao

Abstract:

Thin-film transistors(TFTs) have the advantages of low power consumption, short reaction time, and have high research value in the field of semiconductors, based on this reason, people have focused on gallium oxide-indium oxide thin-film transistors, a relatively common thin-film transistor, elaborated and analyzed his production process, "aqueous solution method", explained the purpose of each step of operation, and finally explored the influence of potassium ions doped in the channel layer on the electrical properties of the device, as well as the effect of oxygen vacancies on its switching ratio and memory, and summarized the conclusions.

Keywords: aqueous solution, oxygen vacancies, switch ratio, thin-film transistor(TFT)

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Authors: Phanumas Khumsat, Chalermchai Janmane

Abstract:

Low-voltage instrumentation amplifier has been proposed for 3-lead electrocardiogram measurement system. The circuit’s interference rejection technique is based upon common-mode feed-forwarding where common-mode currents have cancelled each other at the output nodes. The common-mode current for cancellation is generated by means of common-mode sensing and emitter or source followers with resistors employing only one transistor. Simultaneously this particular transistor also provides common-mode feedback to the patient’s right/left leg to further reduce interference entering the amplifier. The proposed designs have been verified with simulations in 0.18-µm CMOS process operating under 1.0-V supply with CMRR greater than 80dB. Moreover ECG signals have experimentally recorded with the proposed instrumentation amplifiers implemented from discrete BJT (BC547, BC558) and MOSFET (ALD1106, ALD1107) transistors working with 1.5-V supply.

Keywords: electrocardiogram, common-mode feedback, common-mode feedforward, communication engineering

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Authors: Hassane Ouazzani Chahdi, Omar Helli, Bourzgui Nour Eddine, Hassan Maher, Ali Soltani

Abstract:

The real-time knowledge of the NO, NO₂ concentration at high temperature, would allow manufacturers of automobiles to meet the upcoming stringent EURO7 anti-pollution measures for diesel engines. Knowledge of the concentration of each of these species will also enable engines to run leaner (i.e., more fuel efficient) while still meeting the anti-pollution requirements. Our proposed technology is promising in the field of automotive sensors. It consists of nanostructured semiconductors based on gallium nitride and zirconia dioxide. The development of new technologies for selective detection of NO and NO₂ gas species would be a critical enabler of superior depollution. The current response was well correlated to the NO concentration in the range of 0–2000 ppm, 0-2500 ppm NO₂, and 0-300 ppm NH₃ at a temperature of 600.

Keywords: NOₓ sensors, HEMT transistor, anti-pollution, gallium nitride, gas sensor

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Authors: Noha Al Majid, Said Mazer, Moulhime El Bekkali, Catherine Algani, Mahmoud Mehdi

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A low noise figure (NF) and high linearity V-band Low Noise Amplifier (LNA) is reported in this article. The LNA compromises a three-stage cascode configuration. This LNA will be used as a part of a WPAN (Wireless Personal Area Network) receiver in the millimeter-wave band at 60 GHz. It is designed according to the MMIC technology (Monolithic Microwave Integrated Circuit) in PH 15 process from UMS foundry and uses a 0.15 μm GaAs PHEMT (Pseudomorphic High Electron Mobility Transistor). The particularity of this LNA compared to other LNAs in literature is its very low noise figure which is equal to 1 dB and its high linearity (IIP3 is about 22 dB). The LNA consumes 0.24 Watts, achieving a high gain which is about 23 dB, an input return loss better than -10 dB and an output return loss better than -8 dB.

Keywords: low noise amplifier, V-band, MMIC technology, LNA, amplifier, cascode, pseudomorphic high electron mobility transistor (PHEMT), high linearity

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Authors: Vinit Srivastava, Abhay Singh Thakur, Shivam Dubey, Rahul Vaish, Bharat Singh Rajpurohit

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This study examines the problem of students' poor comprehension of the thermal dependence of resistance by investigating this idea using an evidence-based inquiry approach. It suggests a practical exercise to improve secondary school students' comprehension of how materials' resistance to temperature changes. The suggested exercise uses an Arduino and Peltier device to test the resistance of aluminum and graphite at various temperatures. The study attempts to close the knowledge gap between the theoretical and practical facets of the subject, which students frequently find difficult to grasp. With the help of a variety of resistors made of various materials and pencils of varying grades, the Arduino experiment investigates the resistance of a metallic conductor (aluminum) and a semiconductor (graphite) at various temperatures. The purpose of the research is to clarify for students the relationship between temperature and resistance and to emphasize the importance of resistor material choice and measurement methods in obtaining precise and stable resistance values over dynamic temperature variations. The findings show that while the resistance of graphite decreases with temperature, the resistance of metallic conductors rises with temperature. The results also show that as softer lead pencils or pencils of a lower quality are used, the resistance values of the resistors drop. In addition, resistors showed greater stability at lower temperatures when their temperature coefficients of resistance (TCR) were smaller. Overall, the results of this article show that the suggested experiment is a useful and practical method for teaching students about resistance's relationship to temperature. It emphasizes how crucial it is to take into account the resistor material selection and the resistance measurement technique when designing and picking out resistors for various uses. The results of the study are anticipated to guide the creation of more efficient teaching methods to close the gap between science education's theoretical and practical components.

Keywords: electrical resistance, temperature dependence, science education, inquiry-based activity, resistor stability

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