Search results for: negative bias voltage
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 6266

Search results for: negative bias voltage

6266 The Effects of Applied Negative Bias Voltage on Structure and Optical Properties of a-C:H Films

Authors: X. L. Zhou, S. Tunmee, I. Toda, K. Komatsu, S. Ohshio, H. Saitoh

Abstract:

Hydrogenated amorphous carbon (a-C:H) films have been synthesized by a radio frequency plasma enhanced chemical vapor deposition (rf-PECVD) technique with different bias voltage from 0.0 to -0.5 kV. The Raman spectra displayed the polymer-like hydrogenated amorphous carbon (PLCH) film with 0.0 to -0.1 and a-C:H films with -0.2 to -0.5 kV of bias voltages. The surface chemical information of all films were studied by X-ray photo electron spectroscopy (XPS) technique, presented to C-C (sp2 and sp3) and C-O bonds, and relative carbon (C) and oxygen (O) atomics contents. The O contamination had affected on structure and optical properties. The true density of PLCH and a-C:H films were characterized by X-ray refractivity (XRR) method, showed the result as in the range of 1.16-1.73 g/cm3 that depending on an increasing of bias voltage. The hardness was proportional to the true density of films. In addition, the optical properties i.e. refractive index (n) and extinction coefficient (k) of these films were determined by a spectroscopic ellipsometry (SE) method that give formation to in 1.62-2.10 (n) and 0.04-0.15 (k) respectively. These results indicated that the optical properties confirmed the Raman results as presenting the structure changed with applied bias voltage increased.

Keywords: negative bias voltage, a-C:H film, oxygen contamination, optical properties

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6265 Bias Optimization of Mach-Zehnder Modulator Considering RF Gain on OFDM Radio-Over-Fiber System

Authors: Ghazi Al Sukkar, Yazid Khattabi, Shifen Zhong

Abstract:

Most of the recent wireless LANs, broadband access networks, and digital broadcasting use Orthogonal Frequency Division Multiplexing techniques. In addition, the increasing demand of Data and Internet makes fiber optics an important technology, as fiber optics has many characteristics that make it the best solution for transferring huge frames of Data from a point to another. Radio over fiber is the place where high quality RF is converted to optical signals over single mode fiber. Optimum values for the bias level and the switching voltage for Mach-Zehnder modulator are important for the performance of radio over fiber links. In this paper, we propose a method to optimize the two parameters simultaneously; the bias and the switching voltage point of the external modulator of a radio over fiber system considering RF gain. Simulation results show the optimum gain value under these two parameters.

Keywords: OFDM, Mach Zehnder bias voltage, switching voltage, radio-over-fiber, RF gain

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6264 A Comparative Study on Electrical Characteristics of Au/n-SiC structure, with and Without Zn-Doped PVA Interfacial Layer at Room Temperature

Authors: M. H. Aldahrob, A. Kokce, S. Altindal, H. E. Lapa

Abstract:

In order to obtain the detailed information about the effect of (Zn-doped PVA) interfacial layer, surface states (Nss) and series resistance (Rs) on electrical characteristics, both Au/n- type 4H-SiC (MS) with and without (Zn doped PVA) interfacial layer were fabricated to compare. The main electrical parameters of them were investigated using forward and reverse bias current-voltage (I-V), capacitance-voltage (C-V) and conductance –voltage (G/W –V) measurements were performed at room temperature. Experimental results show that the value of ideality factor (n), zero –bias barrier height (ΦBo), Rs, rectifier rate (RR=IF/IR) and the density of Nss are strong functions interfacial layer and applied bias voltage. The energy distribution profile of Nss was obtained from forward bias I-V data by taking into account voltage dependent effective BH (ΦBo) and ideality factor (n(V)). Voltage dependent profile of Rs was also obtained both by using Ohm’s law and Nicollian and Brew methods. The other main diode parameters such as the concentration of doping donor atom (ND), Fermi energy level (EF).BH (ΦBo), depletion layer with (WD) were obtained by using the intercept and slope of the reverse bias C-2 vs V plots. It was found that (Zn-doped PVA) interfacial layer lead to a quite decrease in the values Nss, Rs and leakage current and increase in shunt resistance (Rsh) and RR. Therefore, we can say that the use of thin (Zn-doped PVA) interfacial layer can quite improved the performance of MS structure.

Keywords: interfacial polymer layer, thickness dependence, electric and dielectric properties, series resistance, interface state

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6263 Characterization of current–voltage (I–V) and capacitance–voltage–frequency (C–V–f) features of Au/GaN Schottky diodes

Authors: Abdelaziz Rabehi

Abstract:

The current–voltage (I–V) characteristics of Au/GaN Schottky diodes were measured at room temperature. In addition, capacitance–voltage–frequency (C–V–f) characteristics are investigated by considering the interface states (Nss) at frequency range 100 kHz to 1 MHz. From the I–V characteristics of the Schottky diode, ideality factor (n) and barrier height (Φb) values of 1.22 and 0.56 eV, respectively, were obtained from a forward bias I–V plot. In addition, the interface states distribution profile as a function of (Ess − Ev) was extracted from the forward bias I–V measurements by taking into account the bias dependence of the effective barrier height (Φe) for the Schottky diode. The C–V curves gave a barrier height value higher than those obtained from I–V measurements. This discrepancy is due to the different nature of the I–V and C–V measurement techniques.

Keywords: Schottky diodes, frequency dependence, barrier height, interface states

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6262 Influence of Measurement System on Negative Bias Temperature Instability Characterization: Fast BTI vs Conventional BTI vs Fast Wafer Level Reliability

Authors: Vincent King Soon Wong, Hong Seng Ng, Florinna Sim

Abstract:

Negative Bias Temperature Instability (NBTI) is one of the critical degradation mechanisms in semiconductor device reliability that causes shift in the threshold voltage (Vth). However, thorough understanding of this reliability failure mechanism is still unachievable due to a recovery characteristic known as NBTI recovery. This paper will demonstrate the severity of NBTI recovery as well as one of the effective methods used to mitigate, which is the minimization of measurement system delays. Comparison was done in between two measurement systems that have significant differences in measurement delays to show how NBTI recovery causes result deviations and how fast measurement systems can mitigate NBTI recovery. Another method to minimize NBTI recovery without the influence of measurement system known as Fast Wafer Level Reliability (FWLR) NBTI was also done to be used as reference.

Keywords: fast vs slow BTI, fast wafer level reliability (FWLR), negative bias temperature instability (NBTI), NBTI measurement system, metal-oxide-semiconductor field-effect transistor (MOSFET), NBTI recovery, reliability

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6261 Design of 900 MHz High Gain SiGe Power Amplifier with Linearity Improved Bias Circuit

Authors: Guiheng Zhang, Wei Zhang, Jun Fu, Yudong Wang

Abstract:

A 900 MHz three-stage SiGe power amplifier (PA) with high power gain is presented in this paper. Volterra Series is applied to analyze nonlinearity sources of SiGe HBT device model clearly. Meanwhile, the influence of operating current to IMD3 is discussed. Then a β-helper current mirror bias circuit is applied to improve linearity, since the β-helper current mirror bias circuit can offer stable base biasing voltage. Meanwhile, it can also work as predistortion circuit when biasing voltages of three bias circuits are fine-tuned, by this way, the power gain and operating current of PA are optimized for best linearity. The three power stages which fabricated by 0.18 μm SiGe technology are bonded to the printed circuit board (PCB) to obtain impedances by Load-Pull system, then matching networks are done for best linearity with discrete passive components on PCB. The final measured three-stage PA exhibits 21.1 dBm of output power at 1 dB compression point (OP1dB) with power added efficiency (PAE) of 20.6% and 33 dB power gain under 3.3 V power supply voltage.

Keywords: high gain power amplifier, linearization bias circuit, SiGe HBT model, Volterra series

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6260 Investigation of Threshold Voltage Shift in Gamma Irradiated N-Channel and P-Channel MOS Transistors of CD4007

Authors: S. Boorboor, S. A. H. Feghhi, H. Jafari

Abstract:

The ionizing radiations cause different kinds of damages in electronic components. MOSFETs, most common transistors in today’s digital and analog circuits, are severely sensitive to TID damage. In this work, the threshold voltage shift of CD4007 device, which is an integrated circuit including P-channel and N-channel MOS transistors, was investigated for low dose gamma irradiation under different gate bias voltages. We used linear extrapolation method to extract threshold voltage from ID-VG characteristic curve. The results showed that the threshold voltage shift was approximately 27.5 mV/Gy for N-channel and 3.5 mV/Gy for P-channel transistors at the gate bias of |9 V| after irradiation by Co-60 gamma ray source. Although the sensitivity of the devices under test were strongly dependent to biasing condition and transistor type, the threshold voltage shifted linearly versus accumulated dose in all cases. The overall results show that the application of CD4007 as an electronic buffer in a radiation therapy system is limited by TID damage. However, this integrated circuit can be used as a cheap and sensitive radiation dosimeter for accumulated dose measurement in radiation therapy systems.

Keywords: threshold voltage shift, MOS transistor, linear extrapolation, gamma irradiation

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6259 Analysis of Structural and Photocatalytical Properties of Anatase, Rutile and Mixed Phase TiO2 Films Deposited by Pulsed-Direct Current and Radio Frequency Magnetron Co-Sputtering

Authors: S. Varnagiris, M. Urbonavicius, S. Tuckute, M. Lelis, K. Bockute

Abstract:

Amongst many water purification techniques, TiO2 photocatalysis is recognized as one of the most promising sustainable methods. It is known that for photocatalytical applications anatase is the most suitable TiO2 phase, however heterojunction of anatase/rutile phases could improve the photocatalytical activity of TiO2 even further. Despite the relative simplicity of TiO2 different synthesis methods lead to the highly dispersed crystal phases and photocatalytic activity of the corresponding samples. Accordingly, suggestions and investigations of various innovative methods of TiO2 synthesis are still needed. In this work structural and photocatalytical properties of TiO2 films deposited by the unconventional method of simultaneous co-sputtering from two magnetrons powered by pulsed-Direct Current (pDC) and Radio Frequency (RF) power sources with negative bias voltage have been studied. More specifically, TiO2 film thickness, microstructure, surface roughness, crystal structure, optical transmittance and photocatalytical properties were investigated by profilometer, scanning electron microscope, atomic force microscope, X-ray diffractometer and UV-Vis spectrophotometer respectively. The proposed unconventional two magnetron co-sputtering based TiO2 film formation method showed very promising results for crystalline TiO2 film formation while keeping process temperatures below 100 °C. XRD analysis revealed that by using proper combination of power source type and bias voltage various TiO2 phases (amorphous, anatase, rutile or their mixture) can be synthesized selectively. Moreover, strong dependency between power source type and surface roughness, as well as between the bias voltage and band gap value of TiO2 films was observed. Interestingly, TiO2 films deposited by two magnetron co-sputtering without bias voltage had one of the highest band gap values between the investigated films but its photocatalytic activity was superior compared to all other samples. It is suggested that this is due to the dominating nanocrystalline anatase phase with various exposed surfaces including photocatalytically the most active {001}.

Keywords: films, magnetron co-sputtering, photocatalysis, TiO₂

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6258 Study of the Hysteretic I-V Characteristics in a Polystyrene/ZnO-Nanorods Stack Layer

Authors: You-Lin Wu, Yi-Hsing Sung, Shih-Hung Lin, Jing-Jenn Lin

Abstract:

Performance improvement in optoelectronic devices such as solar cells and photodetectors has been reported when a polymer/ZnO nanorods stack is used. Resistance switching of polymer/ZnO nanocrystals (or nanorods) hybrid has also gained a lot of research interests recently. It has been reported that high- and low-resistance states of a metal/insulator/metal (MIM) structure diode with a polystyrene (PS) and ZnO hybrid as the insulator layer can be switched by applied bias after a high-voltage forming process, while the same device structure merely with a PS layer does not show any forming behavior. In this work, we investigated the current-voltage (I-V) characteristics of an MIM device with a PS/ZnO nanorods stack deposited on fluorine-doped tin oxide (FTO) glass substrate. The ZnO nanorods were grown by a hydrothermal method using a mixture of zinc nitrate, hexamethylenetetramine, and DI water. Following that, a PS layer was deposited by spin coating. Finally, the device with a structure of Ti/ PS/ZnO nanorods/FTO was completed by e-gun evaporated Ti layer on top of the PS layer. Semiconductor parameters analyzer Agilent 4156C was then used to measure the I-V characteristics of the device by applying linear ramp sweep voltage with sweep sequence of 0V → 4V → 0V → 3V → 0V → 2V → 0V → 1V → 0V in both positive and negative directions. It is interesting to find that the I-V characteristics are bias dependent and hysteretic, indicating that the device Ti/PS/ZnO nanorods/FTO structure has ferroelectricity. Our results also show that the maximum hysteresis loop height of the I-V characteristics as well as the voltage at which the maximum hysteresis loop height of each scan occurs increase with increasing maximum sweep voltage. It should be noticed that, although ferroelectricity has been found in ZnO at its melting temperature (1975℃) and in Li- or Co-doped ZnO, neither PS nor ZnO has ferroelectricity at room temperature. Using the same structure but with a PS or ZnO layer only as the insulator does not give and hysteretic I-V characteristics. It is believed that a charge polarization layer is induced near the PS/ZnO nanorods stack interface and thus causes the ferroelectricity in the device with Ti/PS/ZnO nanorods/FTO structure. Our results show that the PS/ZnO stack can find a potential application in a resistive switching memory device with MIM structure.

Keywords: ferroelectricity, hysteresis, polystyrene, resistance switching, ZnO nanorods

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6257 A CMOS-Integrated Hall Plate with High Sensitivity

Authors: Jin Sup Kim, Min Seo

Abstract:

An improved cross-shaped hall plate with high sensitivity is described in this paper. Among different geometries that have been simulated and measured using Helmholtz coil. The paper describes the physical hall plate design and implementation in a 0.18-µm CMOS technology. In this paper, the biasing is a constant voltage mode. In the voltage mode, magnetic field is converted into an output voltage. The output voltage is typically in the order of micro- to millivolt and therefore, it must be amplified before being transmitted to the outside world. The study, design and performance optimization of hall plate has been carried out with the COMSOL Multiphysics. It is used to estimate the voltage distribution in the hall plate with and without magnetic field and to optimize the geometry. The simulation uses the nominal bias current of 1mA. The applied magnetic field is in the range from 0 mT to 20 mT. Measured results of the one structure over the 10 available samples show for the best sensitivity of 2.5 %/T at 20mT.

Keywords: cross-shaped hall plate, sensitivity, CMOS technology, Helmholtz coil

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6256 Numerical Investigation Including Mobility Model for the Performances of Piezoresistive Sensors

Authors: Abdelaziz Beddiaf

Abstract:

In this work, we present an analysis based on the study of mobility which is a very important electrical parameter of a piezoresistor and which is directly bound to the piezoresistivity effect in piezoresistive pressure sensors. We determine how the temperature affects mobility when the electric potential is applied. For this, a theoretical approach based on mobility in a p-type Silicon piezoresistor with that of a finite difference model for self-heating is developed. So, the evolution of mobility has been established versus time for different doping levels and with temperature rise provoked by self-heating using a numerical model combined with that of mobility. Furthermore, it has been calculated for some geometrical parameters of the sensor, such as membrane side length and thickness. Also, it is computed as a function of bias voltage. It was observed that mobility is strongly affected by the temperature rise induced by the applied potential when the sensor is actuated for a prolonged time as a consequence of drifting in the output response of the sensor. Finally, this work makes it possible to predict their temperature behavior due to self-heating and to improve this effect by optimizing the geometric properties of the device and by reducing the voltage source applied to the bridge.

Keywords: Sensors, Piezoresistivity, Mobility, Bias voltage

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6255 Multiple Negative-Differential Resistance Regions Based on AlN/GaN Resonant Tunneling Structures by the Vertical Growth of Molecular Beam Epitaxy

Authors: Yao Jiajia, Wu Guanlin, LIU Fang, Xue Junshuai, Zhang Jincheng, Hao Yue

Abstract:

Resonant tunneling diodes (RTDs) based on GaN have been extensively studied. However, no results of multiple logic states achieved by RTDs were reported by the methods of epitaxy in the GaN materials. In this paper, the multiple negative-differential resistance regions by combining two discrete double-barrier RTDs in series have been first demonstrated. Plasma-assisted molecular beam epitaxy (PA-MBE) was used to grow structures consisting of two vertical RTDs. The substrate was a GaN-on-sapphire template. Each resonant tunneling structure was composed of a double barrier of AlN and a single well of GaN with undoped 4-nm space layers of GaN on each side. The AlN barriers were 1.5 nm thick, and the GaN well was 2 nm thick. The resonant tunneling structures were separated from each other by 30-nm thick n+ GaN layers. The bottom and top layers of the structures, grown neighboring to the spacer layers that consist of 200-nm-thick n+ GaN. These devices with two tunneling structures exhibited uniform peaks and valleys current and also had two negative differential resistance NDR regions equally spaced in bias voltage. The current-voltage (I-V) characteristics of resonant tunneling structures with diameters of 1 and 2 μm were analyzed in this study. These structures exhibit three stable operating points, which are investigated in detail. This research demonstrates that using molecular beam epitaxy MBE to vertically grow multiple resonant tunneling structures is a promising method for achieving multiple negative differential resistance regions and stable logic states. These findings have significant implications for the development of digital circuits capable of multi-value logic, which can be achieved with a small number of devices.

Keywords: GaN, AlN, RTDs, MBE, logic state

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6254 Cell Elevator: A Novel Technique for Cell Sorting and Circulating Tumor Cell Detection and Discrimination

Authors: Kevin Zhao, Norman J. Horing

Abstract:

A methodology for cells sorting and circulating tumor cell detection and discrimination is presented in this paper. The technique is based on Dielectrophoresis and microfluidic device theory. Specifically, the sorting of the cells is realized by adjusting the relation among the sedimentation forces, the drag force provided by the fluid, and the Dielectrophortic force that is relevant to the bias voltage applied on the device. The relation leads to manipulation of the elevation of the cells of the same kind to a height by controlling the bias voltage. Once the cells have been lifted to a position next to the bottom of the cell collection channel, the buffer fluid flashes them into the cell collection channel. Repeated elevation of the cells leads to a complete sorting of the cells in the sample chamber. A proof-of-principle example is presented which verifies the feasibility of the methodology.

Keywords: cell sorter, CTC cell, detection and discrimination, dielectrophoresisords, simulation

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6253 Microstructure, Mechanical and Tribological Properties of (TiTaZrNb)Nx Medium Entropy Nitride Coatings: Influence of Nitrogen Content and Bias Voltage

Authors: Mario Alejandro Grisales, M. Daniela Chimá, Gilberto Bejarano Gaitán

Abstract:

High entropy alloys (HEA) and nitride (HEN) are currently very attractive to the automotive, aerospace, metalworking and materials forming manufacturing industry, among others, for exhibiting higher mechanical properties, wear resistance, and thermal stability than binary and ternary alloys. In this work medium-entropy coatings of TiTaZrNb and the nitrides of (TiTaZrNb)Nx were synthesized on to AISI 420 and M2 steel samples by the direct current magnetron sputtering technique. The influence of the bias voltage supplied to the substrate on the microstructure, chemical- and phase composition of the matrix coating was evaluated, and the effect of nitrogen flow on the microstructural, mechanical and tribological properties of the corresponding nitrides was studied. A change in the crystalline structure from BCC for TiTaZrNb coatings to FCC for (TiTaZrNb)Nx was observed, that is associated with the incorporation of nitrogen into the matrix and the consequent formation of a solid solution of (TiTaZrNb)Nx. An increase in hardness and residual stresses was observed with increasing bias voltage for TiTaZrNb, reaching 12.8 GPa for the coating deposited with a bias of -130V. In the case of (TiTaZrNb)Nx nitride, a greater hardness of 23 GPa is achieved for the coating deposited with a N2 flow of 12 sccm, which slightly drops to 21.7 GPa for that deposited with N2 flow of 15 sccm. The slight reduction in hardness could be associated with the precipitation of the TiN and ZrN phases that are formed at higher nitrogen flows. The specific wear rate of the deposited coatings ranged between 0.5xexp13 and 0.6xexp13 N/m2. The steel substrate exhibited an average hardness of 2.0 GPa and a specific wear rate of 203.2exp13 N/m2. Both the hardness and the specific wear rate of the synthesized nitride coatings were higher than that of the steel substrate, showing a protective effect of the steel against wear.

Keywords: medium entropy coatings, hard coatings, magnetron sputtering, tribology, wear resistance

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6252 Single-Inductor Multi-Output Converters with Four-Level Output Voltages

Authors: Yasunori Kobori, Murong Li, Feng Zhao, Shu Wu, Nobukazu Takai, Haruo Kobayashi

Abstract:

This paper proposes an electrolytic capacitor-less transformer-less AC-DC LED driver with a current ripple canceller. The proposed LED driver includes a diode bridge, a buck-boost converter, a negative feedback controller and a current ripple cancellation circuit. The current ripple canceller works as a bi-directional current converter using a sub-inductor, a sub-capacitor and two switches for controlling current flow. LED voltage is controlled in order to regulate LED current by the negative feedback controller using a current sense resistor. There are two capacitors with capacitance of 5 uF. We describe circuit topologies, operation principles and simulation results for our proposed circuit. In addition, we show the line regulation for input voltage variation from 85V to 130V. The output voltage ripple is 2V and the LED current ripple is 65 mA which is less than 20% of the average of LED current of 350 mA.

Keywords: DC-DC buck converter, four-level output voltage, single inductor multi output (SIMO), switching converter

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6251 Depletion Layer Parameters of Al-MoO3-P-CdTe-Al MOS Structures

Authors: A. C. Sarmah

Abstract:

The Al-MoO3-P-CdTe-Al MOS sandwich structures were fabricated by vacuum deposition method on cleaned glass substrates. Capacitance versus voltage measurements were performed at different frequencies and sweep rates of applied voltages for oxide and semiconductor films of different thicknesses. In the negative voltage region of the C-V curve a high differential capacitance of the semiconductor was observed and at high frequencies (<10 kHz) the transition from accumulation to depletion and further to deep depletion was observed as the voltage was swept from negative to positive. A study have been undertaken to determine the value of acceptor density and some depletion layer parameters such as depletion layer capacitance, depletion width, impurity concentration, flat band voltage, Debye length, flat band capacitance, diffusion or built-in-potential, space charge per unit area etc. These were determined from C-V measurements for different oxide and semiconductor thicknesses.

Keywords: debye length, depletion width, flat band capacitance, impurity concentration

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6250 SCR-Based Advanced ESD Protection Device for Low Voltage Application

Authors: Bo Bae Song, Byung Seok Lee, Hyun young Kim, Chung Kwang Lee, Yong Seo Koo

Abstract:

This paper proposed a silicon controller rectifier (SCR) based ESD protection device to protect low voltage ESD for integrated circuit. The proposed ESD protection device has low trigger voltage and high holding voltage compared with conventional SCR-based ESD protection devices. The proposed ESD protection circuit is verified and compared by TCAD simulation. This paper verified effective low voltage ESD characteristics with low trigger voltage of 5.79V and high holding voltage of 3.5V through optimization depending on design variables (D1, D2, D3, and D4).

Keywords: ESD, SCR, holding voltage, latch-up

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6249 DG Power Plants Placement and Evaluation of its Effect on Improving Voltage Security Margin in Radial Distribution Networks

Authors: Atabak Faramarzpour, Mohsen Mohammadian

Abstract:

In this article, we introduce the stability of power system voltage and state DG power plants placement and its effect on improving voltage security margin in radial distribution networks. For this purpose, first, important definitions in voltage stability area such as small and big voltage disturbances, instability, and voltage collapse, and voltage security definitions are stated. Then, according to voltage collapse time, voltage stability is classified and each one's characteristics are stated.

Keywords: DG power plants, evaluation, voltage security, radial distribution networks

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6248 Biocompatibility of Calcium Phosphate Coatings With Different Crystallinity Deposited by Sputtering

Authors: Ekaterina S. Marchenko, Gulsharat A. Baigonakova, Kirill M. Dubovikov, Igor A. Khlusov

Abstract:

NiTi alloys combine biomechanical and biochemical properties. This makes them a perfect candidate for medical applications. However, there is a serious problem with these alloys, such as the release of Ni from the matrix. Ni ions are known to be toxic to living tissues and leach from the matrix into the surrounding implant tissues due to corrosion after prolonged use. To prevent the release of Ni ions, corrosive strong coatings are usually used. Titanium nitride-based coatings are perfect corrosion inhibitors and also have good bioactive properties. However, there is an opportunity to improve the biochemical compatibility of the surface by depositing another layer. This layer can consist of elements such as calcium and phosphorus. The Ca and P ions form different calcium phosphate phases, which are present in the mineral part of human bones. We therefore believe that these elements must promote osteogenesis and osteointegration. In view of the above, the aim of this study is to investigate the effect of crystallinity on the biocompatibility of a two-layer coating deposited on NiTi substrate by sputtering. The first step of the research, apart from the NiTi polishing, is the layer-by-layer deposition of Ti-Ni-Ti by magnetron sputtering and the subsequent synthesis of this composite in an N atmosphere at 900 °C. The total thickness of the corrosion resistant layer is 150 nm. Plasma assisted RF sputtering was then used to deposit a bioactive film on the titanium nitride layer. A Ca-P powder target was used to obtain such a film. We deposited three types of Ca-P layers with different crystallinity and compared them in terms of cytotoxicity. One group of samples had no Ca-P coating and was used as a control. We obtained different crystallinity by varying the sputtering parameters such as bias voltage, plasma source current and pressure. XRD analysis showed that all coatings are calcium phosphate, but the sample obtained at maximum bias and plasma source current and minimum pressure has the most intense peaks from the coating phase. SEM and EDS showed that all three coatings have a homogeneous and dense structure without cracks and consist of calcium, phosphorus and oxygen. Cytotoxic tests carried out on three types of samples with Ca-P coatings and a control group showed that the control sample and the sample with Ca-P coating obtained at maximum bias voltage and plasma source current and minimum pressure had the lowest number of dead cells on the surface, around 11 ± 4%. Two other types of samples with Ca-P coating have 40 ± 9% and 21 ± 7% dead cells on the surface. It can therefore be concluded that these two sputtering modes have a negative effect on the corrosion resistance of the whole samples. The third sputtering mode does not affect the corrosion resistance and has the same level of cytotoxicity as the control. It can be concluded that the most suitable sputtering mode is the third with maximum bias voltage and plasma source current and minimum pressure.

Keywords: calcium phosphate coating, cytotoxicity, NiTi alloy, two-layer coating

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6247 A Study on ESD Protection Circuit Applying Silicon Controlled Rectifier-Based Stack Technology with High Holding Voltage

Authors: Hee-Guk Chae, Bo-Bae Song, Kyoung-Il Do, Jeong-Yun Seo, Yong-Seo Koo

Abstract:

In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage

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6246 Improved Small-Signal Characteristics of Infrared 850 nm Top-Emitting Vertical-Cavity Lasers

Authors: Ahmad Al-Omari, Osama Khreis, Ahmad M. K. Dagamseh, Abdullah Ababneh, Kevin Lear

Abstract:

High-speed infrared vertical-cavity surface-emitting laser diodes (VCSELs) with Cu-plated heat sinks were fabricated and tested. VCSELs with 10 mm aperture diameter and 4 mm of electroplated copper demonstrated a -3dB modulation bandwidth (f-3dB) of 14 GHz and a resonance frequency (fR) of 9.5 GHz at a bias current density (Jbias) of only 4.3 kA/cm2, which corresponds to an improved f-3dB2/Jbias ratio of 44 GHz2/kA/cm2. At higher and lower bias current densities, the f-3dB2/ Jbias ratio decreased to about 30 GHz2/kA/cm2 and 18 GHz2/kA/cm2, respectively. Examination of the analogue modulation response demonstrated that the presented VCSELs displayed a steady f-3dB/ fR ratio of 1.41±10% over the whole range of the bias current (1.3Ith to 6.2Ith). The devices also demonstrated a maximum modulation bandwidth (f-3dB max) of more than 16 GHz at a bias current less than the industrial bias current standard for reliability by 25%.

Keywords: current density, high-speed VCSELs, modulation bandwidth, small-signal characteristics, thermal impedance, vertical-cavity surface-emitting lasers

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6245 Spiking Behavior in Memristors with Shared Top Electrode Configuration

Authors: B. Manoj Kumar, C. Malavika, E. S. Kannan

Abstract:

The objective of this study is to investigate the switching behavior of two vertically aligned memristors connected by a shared top electrode, a configuration that significantly deviates from the conventional single oxide layer sandwiched between two electrodes. The device is fabricated by bridging copper electrodes with mechanically exfoliated van der Waals metal (specifically tantalum disulfide and tantalum diselenide). The device demonstrates threshold-switching behavior in its I-V characteristics. When the input voltage signal is ramped with voltages below the threshold, the output current shows spiking behavior, resembling integrated and firing actions without extra circuitry. We also investigated the self-reset behavior of the device. Using a continuous constant voltage bias, we activated the device to the firing state. After removing the bias and reapplying it shortly afterward, the current returned to its initial state. This indicates that the device can spontaneously return to its resting state. The outcome of this investigation offers a fresh perspective on memristor-based device design and an efficient method to construct hardware for neuromorphic computing systems.

Keywords: integrated and firing, memristor, spiking behavior, threshold switching

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6244 A Study on Unidirectional Analog Output Voltage Inverter for Capacitive Load

Authors: Sun-Ki Hong, Nam-HeeByeon, Jung-Seop Lee, Tae-Sam Kang

Abstract:

For Common R or R-L load to apply arbitrary voltage, the bridge traditional inverters don’t have any difficulties by PWM method. However for driving some piezoelectric actuator, arbitrary voltage not a pulse but a steady voltage should be applied. Piezoelectric load is considered as R-C load and its voltage does not decrease even though the applied voltage decreases. Therefore it needs some special inverter with circuit that can discharge the capacitive energy. Especially for unidirectional arbitrary voltage driving like as sine wave, it becomes more difficult problem. In this paper, a charge and discharge circuit for unidirectional arbitrary voltage driving for piezoelectric actuator is proposed. The circuit has charging and discharging switches for increasing and decreasing output voltage. With the proposed simple circuit, the load voltage can have any unidirectional level with tens of bandwidth because the load voltage can be adjusted by switching the charging and discharging switch appropriately. The appropriateness is proved from the simulation of the proposed circuit.

Keywords: DC-DC converter, analog output voltage, sinusoidal drive, piezoelectric load, discharging circuit

Procedia PDF Downloads 352
6243 SCR-Stacking Structure with High Holding Voltage for IO and Power Clamp

Authors: Hyun Young Kim, Chung Kwang Lee, Han Hee Cho, Sang Woon Cho, Yong Seo Koo

Abstract:

In this paper, we proposed a novel SCR (Silicon Controlled Rectifier) - based ESD (Electrostatic Discharge) protection device for I/O and power clamp. The proposed device has a higher holding voltage characteristic than conventional SCR. These characteristics enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. The proposed device was analyzed to figure out electrical characteristics and tolerance robustness in term of individual design parameters (D1, D2, D3). They are investigated by using the Synopsys TCAD simulator. As a result of simulation, holding voltage increased with different design parameters. The holding voltage of the proposed device changes from 3.3V to 7.9V. Also, N-Stack structure ESD device with the high holding voltage is proposed. In the simulation results, 2-stack has holding voltage of 6.8V and 3-stack has holding voltage of 10.5V. The simulation results show that holding voltage of stacking structure can be larger than the operation voltage of high-voltage application.

Keywords: ESD, SCR, holding voltage, stack, power clamp

Procedia PDF Downloads 525
6242 Study of Electrical Properties of An-Fl Based Organic Semiconducting Thin Film

Authors: A.G. S. Aldajani, N. Smida, M. G. Althobaiti, B. Zaidi

Abstract:

In order to exploit the good electrical properties of anthracene and the excellent properties of fluorescein, new hybrid material has been synthesized (An-Fl). Current-voltage measurements were done on a new single-layer ITO/An-FL/Al device of typically 100 nm thickness. Atypical diode behavior is observed with a turn-on voltage of 4.4 V, a dynamic resistance of 74.07 KΩ and a rectification ratio of 2.02 due to unbalanced transport. Results show also that the current-voltage characteristics present three different regimes of the power-law (J~Vᵐ) for which the conduction mechanism is well described with space-charge-limited current conduction mechanism (SCLC) with a charge carrier mobility of 2.38.10⁻⁵cm2V⁻¹S⁻¹. Moreover, the electrical transport properties of this device have been carried out using a dependent frequency study in the range (50 Hz–1.4 MHz) for different applied biases (from 0 to 6 V). At lower frequency, the σdc values increase with bias voltage rising, supporting that the mobile ion can hop successfully to its nearest vacant site. From σac and impedance measurements, the equivalent electrical circuit is evidenced, where the conductivity process is coherent with an exponential trap distribution caused by structural defects and/or chemical impurities.

Keywords: semiconducting polymer, conductivity, SCLC, impedance spectroscopy

Procedia PDF Downloads 148
6241 Analysis of SCR-Based ESD Protection Circuit on Holding Voltage Characteristics

Authors: Yong Seo Koo, Jong Ho Nam, Yong Nam Choi, Dae Yeol Yoo, Jung Woo Han

Abstract:

This paper presents a silicon controller rectifier (SCR) based ESD protection circuit for IC. The proposed ESD protection circuit has low trigger voltage and high holding voltage compared with conventional SCR ESD protection circuit. Electrical characteristics of the proposed ESD protection circuit are simulated and analyzed using TCAD simulator. The proposed ESD protection circuit verified effective low voltage ESD characteristics with low trigger voltage and high holding voltage.

Keywords: electro-static discharge (ESD), silicon controlled rectifier (SCR), holding voltage, protection circuit

Procedia PDF Downloads 342
6240 A Silicon Controlled Rectifier-Based ESD Protection Circuit with High Holding Voltage and High Robustness Characteristics

Authors: Kyoung-il Do, Byung-seok Lee, Hee-guk Chae, Jeong-yun Seo Yong-seo Koo

Abstract:

In this paper, a Silicon Controlled Rectifier (SCR)-based Electrostatic Discharge (ESD) protection circuit with high holding voltage and high robustness characteristics is proposed. Unlike conventional SCR, the proposed circuit has low trigger voltage and high holding voltage and provides effective ESD protection with latch-up immunity. In addition, the TCAD simulation results show that the proposed circuit has better electrical characteristics than the conventional SCR. A stack technology was used for voltage-specific applications. Consequentially, the proposed circuit has a trigger voltage of 17.60 V and a holding voltage of 3.64 V.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage

Procedia PDF Downloads 366
6239 Analog Voltage Inverter Drive for Capacitive Load with Adaptive Gain Control

Authors: Sun-Ki Hong, Yong-Ho Cho, Ki-Seok Kim, Tae-Sam Kang

Abstract:

Piezoelectric actuator is treated as RC load when it is modeled electrically. For some piezoelectric actuator applications, arbitrary voltage is required to actuate. Especially for unidirectional arbitrary voltage driving like as sine wave, some special inverter with circuit that can charge and discharge the capacitive energy can be used. In this case, the difference between power supply level and the object voltage level for RC load is varied. Because the control gain is constant, the controlled output is not uniform according to the voltage difference. In this paper, for charge and discharge circuit for unidirectional arbitrary voltage driving for piezoelectric actuator, the controller gain is controlled according to the voltage difference. With the proposed simple idea, the load voltage can have controlled smoothly although the voltage difference is varied. The appropriateness is proved from the simulation of the proposed circuit.

Keywords: analog voltage inverter, capacitive load, gain control, dc-dc converter, piezoelectric, voltage waveform

Procedia PDF Downloads 611
6238 Comparative Study of Line Voltage Stability Indices for Voltage Collapse Forecasting in Power Transmission System

Authors: H. H. Goh, Q. S. Chua, S. W. Lee, B. C. Kok, K. C. Goh, K. T. K. Teo

Abstract:

At present, the evaluation of voltage stability assessment experiences sizeable anxiety in the safe operation of power systems. This is due to the complications of a strain power system. With the snowballing of power demand by the consumers and also the restricted amount of power sources, therefore, the system has to perform at its maximum proficiency. Consequently, the noteworthy to discover the maximum ability boundary prior to voltage collapse should be undertaken. A preliminary warning can be perceived to evade the interruption of power system’s capacity. The effectiveness of line voltage stability indices (LVSI) is differentiated in this paper. The main purpose of the indices is used to predict the proximity of voltage instability of the electric power system. On the other hand, the indices are also able to decide the weakest load buses which are close to voltage collapse in the power system. The line stability indices are assessed using the IEEE 14 bus test system to validate its practicability. Results demonstrated that the implemented indices are practically relevant in predicting the manifestation of voltage collapse in the system. Therefore, essential actions can be taken to dodge the incident from arising.

Keywords: critical line, line outage, line voltage stability indices (LVSI), maximum loadability, voltage collapse, voltage instability, voltage stability analysis

Procedia PDF Downloads 319
6237 New Series Input Parallel Output LLC DC/DC Converter with the Input Voltage Balancing Capacitor for the Electric System of Electric Vehicles

Authors: Kang Hyun Yi

Abstract:

This paper presents a new parallel output LLC DC/DC converter for electric vehicle. The electric vehicle has two batteries. One is a high voltage battery for the powertrain of the vehicle and the other is a low voltage battery for the vehicle electric system. The low voltage is charged from the high voltage battery and the high voltage input and the high current output DC/DC converter is needed. Therefore, the new LLC converter with the input voltage compensation is proposed for the high voltage input and the low voltage output DC/DC converter. The proposed circuit has two LLC converters with the series input voltage from the battery for the powertrain and the parallel output low battery voltage for the vehicle electric system because the battery voltage for the powertrain and the electric power for the vehicle become high. Also, the input series voltage compensation capacitor is used for balancing the input current in the two LLC converters. The proposed converter has an equal electric stress of the semiconductor parts and the reactive components, high efficiency and good heat dissipation.

Keywords: electric vehicle, LLC DC/DC converter, input voltage balancing, parallel output

Procedia PDF Downloads 1018